llvm.org GIT mirror llvm / a8de1c1
Define classes for FP unary instructions and multiclasses for FP-to-fixed point conversion instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 8 years ago
2 changed file(s) with 71 addition(s) and 70 deletion(s). Raw diff Collapse all Expand all
7272 // Only S32 and D32 are supported right now.
7373 //===----------------------------------------------------------------------===//
7474
75 multiclass FFR1_1 funct, string asmstr>
76 {
77 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
78 !strconcat(asmstr, ".s\t$fd, $fs"), []>;
79
80 def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
81 !strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[NotFP64bit]>;
75 // Instructions that convert an FP value to 32-bit fixed point.
76 multiclass FFR1_W_M funct, string opstr> {
77 def _S : FFR1;
78 def _D32 : FFR1,
79 Requires<[NotFP64bit]>;
80 def _D64 : FFR1,
81 Requires<[IsFP64bit]>;
82 }
83
84 // Instructions that convert an FP value to 64-bit fixed point.
85 let Predicates = [IsFP64bit] in
86 multiclass FFR1_L_M funct, string opstr> {
87 def _S : FFR1;
88 def _D64 : FFR1;
8289 }
8390
8491 multiclass FFR1_2 funct, string asmstr, SDNode FOp>
8592 {
86 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
87 !strconcat(asmstr, ".s\t$fd, $fs"),
88 [(set FGR32:$fd, (FOp FGR32:$fs))]>;
89
90 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
91 !strconcat(asmstr, ".d\t$fd, $fs"),
92 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[NotFP64bit]>;
93 }
94
95 class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc,
96 RegisterClass RcDst, string asmstr>:
97 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
98 !strconcat(asmstr, "\t$fd, $fs"), []>;
99
93 def _S32 : FFR1P;
94 def _D32 : FFR1P,
95 Requires<[NotFP64bit]>;
96 }
10097
10198 multiclass FFR1_4 funct, string asmstr, SDNode FOp, bit isComm = 0> {
10299 let isCommutable = isComm in {
116113 //===----------------------------------------------------------------------===//
117114 // Floating Point Instructions
118115 //===----------------------------------------------------------------------===//
116 defm ROUND_W : FFR1_W_M<0xc, "round">;
117 defm ROUND_L : FFR1_L_M<0x8, "round">;
118 defm TRUNC_W : FFR1_W_M<0xd, "trunc">;
119 defm TRUNC_L : FFR1_L_M<0x9, "trunc">;
120 defm CEIL_W : FFR1_W_M<0xe, "ceil">;
121 defm CEIL_L : FFR1_L_M<0xa, "ceil">;
122 defm FLOOR_W : FFR1_W_M<0xf, "floor">;
123 defm FLOOR_L : FFR1_L_M<0xb, "floor">;
124 defm CVT_W : FFR1_W_M<0x24, "cvt">;
125 defm CVT_L : FFR1_L_M<0x25, "cvt">;
126
127 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
128
129 let Predicates = [NotFP64bit] in {
130 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
131 def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
132 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
133 }
134
135 let Predicates = [IsFP64bit] in {
136 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
137 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
138 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
139 def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>;
140 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
141 }
119142
120143 let ft = 0 in {
121 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
122 defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
123 defm ROUND_W : FFR1_1<0b001100, "round.w">;
124 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
125 defm CVTW : FFR1_1<0b100100, "cvt.w">;
126
127144 defm FABS : FFR1_2<0b000101, "abs", fabs>;
128145 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
129146 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
130
131 /// Convert to Single Precison
132 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
133
134 let Predicates = [IsNotSingleFloat] in {
135 /// Ceil to long signed integer
136 def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
137 def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
138
139 /// Round to long signed integer
140 def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
141 def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
142
143 /// Floor to long signed integer
144 def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
145 def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
146
147 /// Trunc to long signed integer
148 def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
149 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
150
151 /// Convert to long signed integer
152 def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
153 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
154
155 /// Convert to Double Precison
156 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
157 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
158 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
159
160 /// Convert to Single Precison
161 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
162 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
163 }
164147 }
165148
166149 // The odd-numbered registers are only referenced when doing loads,
351334 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
352335 def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
353336
354 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
355 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
356
357 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
337 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
338 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
339
340 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
358341 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
359342
360343 let Predicates = [NotFP64bit] in {
361 def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
362 def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
363 }
364
344 def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
345 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
346 }
347
225225 let Inst{15-11} = fs;
226226 let Inst{10-6} = fd;
227227 let Inst{5-0} = 17;
228 }
228 }
229
230 // FP unary instructions without patterns.
231 class FFR1 funct, bits<5> fmt, string opstr, string fmtstr,
232 RegisterClass DstRC, RegisterClass SrcRC> :
233 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
234 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
235 let ft = 0;
236 }
237
238 // FP unary instructions with patterns.
239 class FFR1P funct, bits<5> fmt, string opstr, string fmtstr,
240 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
241 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
242 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
243 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
244 let ft = 0;
245 }
246