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check in the BigBlock local register allocator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37703 91177308-0d34-0410-b5e6-96231b3b80d8 Duraid Madina 12 years ago
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2929
3030 (void) llvm::createSimpleRegisterAllocator();
3131 (void) llvm::createLocalRegisterAllocator();
32 (void) llvm::createBigBlockRegisterAllocator();
3233 (void) llvm::createLinearScanRegisterAllocator();
3334
3435 (void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL);
6969 ///
7070 FunctionPass *createLocalRegisterAllocator();
7171
72 /// BigBlockRegisterAllocation Pass - The BigBlock register allocator
73 /// munches single basic blocks at a time, like the local register
74 /// allocator. While the BigBlock allocator is a little slower, and uses
75 /// somewhat more memory than the local register allocator, it tends to
76 /// yield the best allocations (of any of the allocators) for blocks that
77 /// have hundreds or thousands of instructions in sequence.
78 ///
79 FunctionPass *createBigBlockRegisterAllocator();
80
7281 /// LinearScanRegisterAllocation Pass - This pass implements the linear scan
7382 /// register allocation algorithm, a global register allocator.
7483 ///
0 //===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the LLVM research group and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This register allocator is derived from RegAllocLocal.cpp. Like it, this
10 // allocator works on one basic block at a time, oblivious to others.
11 // However, the algorithm used here is suited for long blocks of
12 // instructions - registers are spilled by greedily choosing those holding
13 // values that will not be needed for the longest amount of time. This works
14 // particularly well for blocks with 10 or more times as many instructions
15 // as machine registers, but can be used for general code.
16 //
17 //===----------------------------------------------------------------------===//
18 //
19 // TODO: - automagically invoke linearscan for (groups of) small BBs?
20 // - break ties when picking regs? (probably not worth it in a
21 // JIT context)
22 //
23 //===----------------------------------------------------------------------===//
24
25 #define DEBUG_TYPE "regalloc"
26 #include "llvm/BasicBlock.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/SSARegMap.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/LiveVariables.h"
33 #include "llvm/CodeGen/RegAllocRegistry.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/ADT/IndexedMap.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/SmallVector.h"
42 #include "llvm/ADT/Statistic.h"
43 #include
44 using namespace llvm;
45
46 STATISTIC(NumStores, "Number of stores added");
47 STATISTIC(NumLoads , "Number of loads added");
48 STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
49
50 namespace {
51 static RegisterRegAlloc
52 bigBlockRegAlloc("bigblock", " Big-block register allocator",
53 createBigBlockRegisterAllocator);
54
55 struct VRegKeyInfo {
56 static inline unsigned getEmptyKey() { return -1U; }
57 static inline unsigned getTombstoneKey() { return -2U; }
58 static unsigned getHashValue(const unsigned &Key) { return Key; }
59 };
60
61 class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
62 public:
63 static char ID;
64 RABigBlock() : MachineFunctionPass((intptr_t)&ID) {}
65 private:
66 const TargetMachine *TM;
67 MachineFunction *MF;
68 const MRegisterInfo *RegInfo;
69 LiveVariables *LV;
70
71 // InsnTimes - maps machine instructions to their "execute times"
72 std::map InsnTimes;
73
74 // VRegReadTable - maps VRegs in a BB to the set of times they are read
75 DenseMap*, VRegKeyInfo> VRegReadTable;
76
77 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
78 // values are spilled.
79 std::map StackSlotForVirtReg;
80
81 // Virt2PhysRegMap - This map contains entries for each virtual register
82 // that is currently available in a physical register.
83 IndexedMap Virt2PhysRegMap;
84
85 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
86 return Virt2PhysRegMap[VirtReg];
87 }
88
89 // PhysRegsUsed - This array is effectively a map, containing entries for
90 // each physical register that currently has a value (ie, it is in
91 // Virt2PhysRegMap). The value mapped to is the virtual register
92 // corresponding to the physical register (the inverse of the
93 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
94 // because it is used by a future instruction, and to -2 if it is not
95 // allocatable. If the entry for a physical register is -1, then the
96 // physical register is "not in the map".
97 //
98 std::vector PhysRegsUsed;
99
100 // PhysRegsUseOrder - This contains a list of the physical registers that
101 // currently have a virtual register value in them. This list provides an
102 // ordering of registers, imposing a reallocation order. This list is only
103 // used if all registers are allocated and we have to spill one, in which
104 // case we spill the least recently used register. Entries at the front of
105 // the list are the least recently used registers, entries at the back are
106 // the most recently used.
107 //
108 std::vector PhysRegsUseOrder;
109
110 // VirtRegModified - This bitset contains information about which virtual
111 // registers need to be spilled back to memory when their registers are
112 // scavenged. If a virtual register has simply been rematerialized, there
113 // is no reason to spill it to memory when we need the register back.
114 //
115 std::vector VirtRegModified;
116
117 void markVirtRegModified(unsigned Reg, bool Val = true) {
118 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
119 Reg -= MRegisterInfo::FirstVirtualRegister;
120 if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1);
121 VirtRegModified[Reg] = Val;
122 }
123
124 bool isVirtRegModified(unsigned Reg) const {
125 assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
126 assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
127 && "Illegal virtual register!");
128 return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
129 }
130
131 void MarkPhysRegRecentlyUsed(unsigned Reg) {
132 if (PhysRegsUseOrder.empty() ||
133 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
134
135 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
136 if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
137 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
138 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
139 // Add it to the end of the list
140 PhysRegsUseOrder.push_back(RegMatch);
141 if (RegMatch == Reg)
142 return; // Found an exact match, exit early
143 }
144 }
145
146 public:
147 virtual const char *getPassName() const {
148 return "BigBlock Register Allocator";
149 }
150
151 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
152 AU.addRequired();
153 AU.addRequiredID(PHIEliminationID);
154 AU.addRequiredID(TwoAddressInstructionPassID);
155 MachineFunctionPass::getAnalysisUsage(AU);
156 }
157
158 private:
159 /// runOnMachineFunction - Register allocate the whole function
160 bool runOnMachineFunction(MachineFunction &Fn);
161
162 /// AllocateBasicBlock - Register allocate the specified basic block.
163 void AllocateBasicBlock(MachineBasicBlock &MBB);
164
165 /// FillVRegReadTable - Fill out the table of vreg read times given a BB
166 void FillVRegReadTable(MachineBasicBlock &MBB);
167
168 /// areRegsEqual - This method returns true if the specified registers are
169 /// related to each other. To do this, it checks to see if they are equal
170 /// or if the first register is in the alias set of the second register.
171 ///
172 bool areRegsEqual(unsigned R1, unsigned R2) const {
173 if (R1 == R2) return true;
174 for (const unsigned *AliasSet = RegInfo->getAliasSet(R2);
175 *AliasSet; ++AliasSet) {
176 if (*AliasSet == R1) return true;
177 }
178 return false;
179 }
180
181 /// getStackSpaceFor - This returns the frame index of the specified virtual
182 /// register on the stack, allocating space if necessary.
183 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
184
185 /// removePhysReg - This method marks the specified physical register as no
186 /// longer being in use.
187 ///
188 void removePhysReg(unsigned PhysReg);
189
190 /// spillVirtReg - This method spills the value specified by PhysReg into
191 /// the virtual register slot specified by VirtReg. It then updates the RA
192 /// data structures to indicate the fact that PhysReg is now available.
193 ///
194 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
195 unsigned VirtReg, unsigned PhysReg);
196
197 /// spillPhysReg - This method spills the specified physical register into
198 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
199 /// true, then the request is ignored if the physical register does not
200 /// contain a virtual register.
201 ///
202 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
203 unsigned PhysReg, bool OnlyVirtRegs = false);
204
205 /// assignVirtToPhysReg - This method updates local state so that we know
206 /// that PhysReg is the proper container for VirtReg now. The physical
207 /// register must not be used for anything else when this is called.
208 ///
209 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
210
211 /// liberatePhysReg - Make sure the specified physical register is available
212 /// for use. If there is currently a value in it, it is either moved out of
213 /// the way or spilled to memory.
214 ///
215 void liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
216 unsigned PhysReg);
217
218 /// isPhysRegAvailable - Return true if the specified physical register is
219 /// free and available for use. This also includes checking to see if
220 /// aliased registers are all free...
221 ///
222 bool isPhysRegAvailable(unsigned PhysReg) const;
223
224 /// getFreeReg - Look to see if there is a free register available in the
225 /// specified register class. If not, return 0.
226 ///
227 unsigned getFreeReg(const TargetRegisterClass *RC);
228
229 /// chooseReg - Pick a physical register to hold the specified
230 /// virtual register by choosing the one which will be read furthest
231 /// in the future.
232 ///
233 unsigned chooseReg(MachineBasicBlock &MBB, MachineInstr *MI,
234 unsigned VirtReg);
235
236 /// reloadVirtReg - This method transforms the specified specified virtual
237 /// register use to refer to a physical register. This method may do this
238 /// in one of several ways: if the register is available in a physical
239 /// register already, it uses that physical register. If the value is not
240 /// in a physical register, and if there are physical registers available,
241 /// it loads it into a register. If register pressure is high, and it is
242 /// possible, it tries to fold the load of the virtual register into the
243 /// instruction itself. It avoids doing this if register pressure is low to
244 /// improve the chance that subsequent instructions can use the reloaded
245 /// value. This method returns the modified instruction.
246 ///
247 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
248 unsigned OpNum);
249
250 };
251 char RABigBlock::ID = 0;
252 }
253
254 /// getStackSpaceFor - This allocates space for the specified virtual register
255 /// to be held on the stack.
256 int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
257 // Find the location Reg would belong...
258 std::map::iterator I =StackSlotForVirtReg.lower_bound(VirtReg);
259
260 if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
261 return I->second; // Already has space allocated?
262
263 // Allocate a new stack object for this spill location...
264 int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
265 RC->getAlignment());
266
267 // Assign the slot...
268 StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
269 return FrameIdx;
270 }
271
272
273 /// removePhysReg - This method marks the specified physical register as no
274 /// longer being in use.
275 ///
276 void RABigBlock::removePhysReg(unsigned PhysReg) {
277 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
278
279 std::vector::iterator It =
280 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
281 if (It != PhysRegsUseOrder.end())
282 PhysRegsUseOrder.erase(It);
283 }
284
285
286 /// spillVirtReg - This method spills the value specified by PhysReg into the
287 /// virtual register slot specified by VirtReg. It then updates the RA data
288 /// structures to indicate the fact that PhysReg is now available.
289 ///
290 void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator I,
292 unsigned VirtReg, unsigned PhysReg) {
293 assert(VirtReg && "Spilling a physical register is illegal!"
294 " Must not have appropriate kill for the register or use exists beyond"
295 " the intended one.");
296 DOUT << " Spilling register " << RegInfo->getName(PhysReg)
297 << " containing %reg" << VirtReg;
298 if (!isVirtRegModified(VirtReg))
299 DOUT << " which has not been modified, so no store necessary!";
300
301 // Otherwise, there is a virtual register corresponding to this physical
302 // register. We only need to spill it into its stack slot if it has been
303 // modified.
304 if (isVirtRegModified(VirtReg)) {
305 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
306 int FrameIndex = getStackSpaceFor(VirtReg, RC);
307 DOUT << " to stack slot #" << FrameIndex;
308 RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
309 ++NumStores; // Update statistics
310 }
311
312 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
313
314 DOUT << "\n";
315 removePhysReg(PhysReg);
316 }
317
318
319 /// spillPhysReg - This method spills the specified physical register into the
320 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
321 /// then the request is ignored if the physical register does not contain a
322 /// virtual register.
323 ///
324 void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
325 unsigned PhysReg, bool OnlyVirtRegs) {
326 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
327 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
328 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
329 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
330 } else {
331 // If the selected register aliases any other registers, we must make
332 // sure that one of the aliases isn't alive.
333 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
334 *AliasSet; ++AliasSet)
335 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
336 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
337 if (PhysRegsUsed[*AliasSet] == 0) {
338 // This must have been a dead def due to something like this:
339 // %EAX :=
340 // := op %AL
341 // No more use of %EAX, %AH, etc.
342 // %EAX isn't dead upon definition, but %AH is. However %AH isn't
343 // an operand of definition MI so it's not marked as such.
344 DOUT << " Register " << RegInfo->getName(*AliasSet)
345 << " [%reg" << *AliasSet
346 << "] is never used, removing it frame live list\n";
347 removePhysReg(*AliasSet);
348 } else
349 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
350 }
351 }
352
353
354 /// assignVirtToPhysReg - This method updates local state so that we know
355 /// that PhysReg is the proper container for VirtReg now. The physical
356 /// register must not be used for anything else when this is called.
357 ///
358 void RABigBlock::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
359 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
360 // Update information to note the fact that this register was just used, and
361 // it holds VirtReg.
362 PhysRegsUsed[PhysReg] = VirtReg;
363 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
364 PhysRegsUseOrder.push_back(PhysReg); // New use of PhysReg
365 }
366
367
368 /// isPhysRegAvailable - Return true if the specified physical register is free
369 /// and available for use. This also includes checking to see if aliased
370 /// registers are all free...
371 ///
372 bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const {
373 if (PhysRegsUsed[PhysReg] != -1) return false;
374
375 // If the selected register aliases any other allocated registers, it is
376 // not free!
377 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
378 *AliasSet; ++AliasSet)
379 if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
380 return false; // Can't use this reg then.
381 return true;
382 }
383
384
385 //////// FIX THIS:
386 /// getFreeReg - Look to see if there is a free register available in the
387 /// specified register class. If not, return 0.
388 ///
389 unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) {
390 // Get iterators defining the range of registers that are valid to allocate in
391 // this class, which also specifies the preferred allocation order.
392 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
393 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
394
395 for (; RI != RE; ++RI)
396 if (isPhysRegAvailable(*RI)) { // Is reg unused?
397 assert(*RI != 0 && "Cannot use register!");
398 return *RI; // Found an unused register!
399 }
400 return 0;
401 }
402
403
404 /// liberatePhysReg - Make sure the specified physical register is available for
405 /// use. If there is currently a value in it, it is either moved out of the way
406 /// or spilled to memory.
407 ///
408 void RABigBlock::liberatePhysReg(MachineBasicBlock &MBB,
409 MachineBasicBlock::iterator &I,
410 unsigned PhysReg) {
411 spillPhysReg(MBB, I, PhysReg);
412 }
413
414 /// chooseReg - Pick a physical register to hold the specified
415 /// virtual register by choosing the one whose value will be read
416 /// furthest in the future.
417 ///
418 unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
419 unsigned VirtReg) {
420 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
421 // First check to see if we have a free register of the requested type...
422 unsigned PhysReg = getFreeReg(RC);
423
424 // If we didn't find an unused register, find the one which will be
425 // read at the most distant point in time.
426 if (PhysReg == 0) {
427 unsigned delay=0, longest_delay=0;
428 SmallVector *ReadTimes;
429
430 unsigned curTime = InsnTimes[I];
431
432 // for all physical regs in the RC,
433 for(TargetRegisterClass::iterator pReg = RC->begin();
434 pReg != RC->end(); ++pReg) {
435 // how long until they're read?
436 if(PhysRegsUsed[*pReg]>0) { // ignore non-allocatable regs
437 ReadTimes = VRegReadTable[PhysRegsUsed[*pReg]];
438 SmallVector::iterator pt =
439 std::lower_bound(ReadTimes->begin(),
440 ReadTimes->end(),
441 curTime);
442 delay = *pt - curTime;
443
444 if(delay > longest_delay) {
445 longest_delay = delay;
446 PhysReg = *pReg;
447 }
448 }
449 }
450
451 assert(PhysReg && "couldn't grab a register from the table?");
452 // TODO: assert that RC->contains(PhysReg) / handle aliased registers
453
454 // since we needed to look in the table we need to spill this register.
455 spillPhysReg(MBB, I, PhysReg);
456 }
457
458 // assign the vreg to our chosen physical register
459 assignVirtToPhysReg(VirtReg, PhysReg);
460 return PhysReg; // and return it
461 }
462
463
464 /// reloadVirtReg - This method transforms an instruction with a virtual
465 /// register use to one that references a physical register. It does this as
466 /// follows:
467 ///
468 /// 1) If the register is already in a physical register, it uses it.
469 /// 2) Otherwise, if there is a free physical register, it uses that.
470 /// 3) Otherwise, it calls chooseReg() to get the physical register
471 /// holding the most distantly needed value, generating a spill in
472 /// the process.
473 ///
474 /// This method returns the modified instruction.
475 MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
476 unsigned OpNum) {
477 unsigned VirtReg = MI->getOperand(OpNum).getReg();
478
479 // If the virtual register is already available in a physical register,
480 // just update the instruction and return.
481 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
482 MI->getOperand(OpNum).setReg(PR);
483 return MI;
484 }
485
486 // Otherwise, if we have free physical registers available to hold the
487 // value, use them.
488 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
489 unsigned PhysReg = getFreeReg(RC);
490 int FrameIndex = getStackSpaceFor(VirtReg, RC);
491
492 if (PhysReg) { // we have a free register, so use it.
493 assignVirtToPhysReg(VirtReg, PhysReg);
494 } else { // no free registers available.
495 // try to fold the spill into the instruction
496 if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)) {
497 ++NumFolded;
498 // Since we changed the address of MI, make sure to update live variables
499 // to know that the new instruction has the properties of the old one.
500 LV->instructionChanged(MI, FMI);
501 return MBB.insert(MBB.erase(MI), FMI);
502 }
503
504 // determine which of the physical registers we'll kill off, since we
505 // couldn't fold.
506 PhysReg = chooseReg(MBB, MI, VirtReg);
507 }
508
509 // this virtual register is now unmodified (since we just reloaded it)
510 markVirtRegModified(VirtReg, false);
511
512 DOUT << " Reloading %reg" << VirtReg << " into "
513 << RegInfo->getName(PhysReg) << "\n";
514
515 // Add move instruction(s)
516 RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
517 ++NumLoads; // Update statistics
518
519 MF->setPhysRegUsed(PhysReg);
520 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
521 return MI;
522 }
523
524 /// Fill out the vreg read timetable. Since ReadTime increases
525 /// monotonically, the individual readtime sets will be sorted
526 /// in ascending order.
527 void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) {
528 // loop over each instruction
529 MachineBasicBlock::iterator MII;
530 unsigned ReadTime;
531
532 for(ReadTime=0, MII = MBB.begin(); MII != MBB.end(); ++ReadTime, ++MII) {
533 MachineInstr *MI = MII;
534
535 InsnTimes[MI] = ReadTime;
536
537 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
538 MachineOperand& MO = MI->getOperand(i);
539 // look for vreg reads..
540 if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
541 MRegisterInfo::isVirtualRegister(MO.getReg())) {
542 // ..and add them to the read table.
543 if(!VRegReadTable[MO.getReg()])
544 VRegReadTable[MO.getReg()] = new SmallVector;
545
546 VRegReadTable[MO.getReg()]->push_back(ReadTime);
547 }
548 }
549
550 }
551
552 }
553
554 void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
555 // loop over each instruction
556 MachineBasicBlock::iterator MII = MBB.begin();
557 const TargetInstrInfo &TII = *TM->getInstrInfo();
558
559 DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
560 if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
561
562 // If this is the first basic block in the machine function, add live-in
563 // registers as active.
564 if (&MBB == &*MF->begin()) {
565 for (MachineFunction::livein_iterator I = MF->livein_begin(),
566 E = MF->livein_end(); I != E; ++I) {
567 unsigned Reg = I->first;
568 MF->setPhysRegUsed(Reg);
569 PhysRegsUsed[Reg] = 0; // It is free and reserved now
570 PhysRegsUseOrder.push_back(Reg);
571 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
572 *AliasSet; ++AliasSet) {
573 if (PhysRegsUsed[*AliasSet] != -2) {
574 PhysRegsUseOrder.push_back(*AliasSet);
575 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
576 MF->setPhysRegUsed(*AliasSet);
577 }
578 }
579 }
580 }
581
582 // Otherwise, sequentially allocate each instruction in the MBB.
583 while (MII != MBB.end()) {
584 MachineInstr *MI = MII++;
585 const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
586 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
587 DOUT << " Regs have values: ";
588 for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
589 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
590 DOUT << "[" << RegInfo->getName(i)
591 << ",%reg" << PhysRegsUsed[i] << "] ";
592 DOUT << "\n");
593
594 // Loop over the implicit uses, making sure that they are at the head of the
595 // use order list, so they don't get reallocated.
596 if (TID.ImplicitUses) {
597 for (const unsigned *ImplicitUses = TID.ImplicitUses;
598 *ImplicitUses; ++ImplicitUses)
599 MarkPhysRegRecentlyUsed(*ImplicitUses);
600 }
601
602 SmallVector Kills;
603 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
604 MachineOperand& MO = MI->getOperand(i);
605 if (MO.isRegister() && MO.isKill())
606 Kills.push_back(MO.getReg());
607 }
608
609 // Get the used operands into registers. This has the potential to spill
610 // incoming values if we are out of registers. Note that we completely
611 // ignore physical register uses here. We assume that if an explicit
612 // physical register is referenced by the instruction, that it is guaranteed
613 // to be live-in, or the input is badly hosed.
614 //
615 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
616 MachineOperand& MO = MI->getOperand(i);
617 // here we are looking for only used operands (never def&use)
618 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
619 MRegisterInfo::isVirtualRegister(MO.getReg()))
620 MI = reloadVirtReg(MBB, MI, i);
621 }
622
623 // If this instruction is the last user of this register, kill the
624 // value, freeing the register being used, so it doesn't need to be
625 // spilled to memory.
626 //
627 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
628 unsigned VirtReg = Kills[i];
629 unsigned PhysReg = VirtReg;
630 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
631 // If the virtual register was never materialized into a register, it
632 // might not be in the map, but it won't hurt to zero it out anyway.
633 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
634 PhysReg = PhysRegSlot;
635 PhysRegSlot = 0;
636 } else if (PhysRegsUsed[PhysReg] == -2) {
637 // Unallocatable register dead, ignore.
638 continue;
639 }
640
641 if (PhysReg) {
642 DOUT << " Last use of " << RegInfo->getName(PhysReg)
643 << "[%reg" << VirtReg <<"], removing it from live set\n";
644 removePhysReg(PhysReg);
645 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
646 *AliasSet; ++AliasSet) {
647 if (PhysRegsUsed[*AliasSet] != -2) {
648 DOUT << " Last use of "
649 << RegInfo->getName(*AliasSet)
650 << "[%reg" << VirtReg <<"], removing it from live set\n";
651 removePhysReg(*AliasSet);
652 }
653 }
654 }
655 }
656
657 // Loop over all of the operands of the instruction, spilling registers that
658 // are defined, and marking explicit destinations in the PhysRegsUsed map.
659 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
660 MachineOperand& MO = MI->getOperand(i);
661 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
662 MRegisterInfo::isPhysicalRegister(MO.getReg())) {
663 unsigned Reg = MO.getReg();
664 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
665
666 MF->setPhysRegUsed(Reg);
667 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
668 PhysRegsUsed[Reg] = 0; // It is free and reserved now
669 PhysRegsUseOrder.push_back(Reg);
670 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
671 *AliasSet; ++AliasSet) {
672 if (PhysRegsUsed[*AliasSet] != -2) {
673 PhysRegsUseOrder.push_back(*AliasSet);
674 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
675 MF->setPhysRegUsed(*AliasSet);
676 }
677 }
678 }
679 }
680
681 // Loop over the implicit defs, spilling them as well.
682 if (TID.ImplicitDefs) {
683 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
684 *ImplicitDefs; ++ImplicitDefs) {
685 unsigned Reg = *ImplicitDefs;
686 bool IsNonAllocatable = PhysRegsUsed[Reg] == -2;
687 if (!IsNonAllocatable) {
688 spillPhysReg(MBB, MI, Reg, true);
689 PhysRegsUseOrder.push_back(Reg);
690 PhysRegsUsed[Reg] = 0; // It is free and reserved now
691 }
692 MF->setPhysRegUsed(Reg);
693
694 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
695 *AliasSet; ++AliasSet) {
696 if (PhysRegsUsed[*AliasSet] != -2) {
697 if (!IsNonAllocatable) {
698 PhysRegsUseOrder.push_back(*AliasSet);
699 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
700 }
701 MF->setPhysRegUsed(*AliasSet);
702 }
703 }
704 }
705 }
706
707 SmallVector DeadDefs;
708 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
709 MachineOperand& MO = MI->getOperand(i);
710 if (MO.isRegister() && MO.isDead())
711 DeadDefs.push_back(MO.getReg());
712 }
713
714 // Okay, we have allocated all of the source operands and spilled any values
715 // that would be destroyed by defs of this instruction. Loop over the
716 // explicit defs and assign them to a register, spilling incoming values if
717 // we need to scavenge a register.
718 //
719 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
720 MachineOperand& MO = MI->getOperand(i);
721 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
722 MRegisterInfo::isVirtualRegister(MO.getReg())) {
723 unsigned DestVirtReg = MO.getReg();
724 unsigned DestPhysReg;
725
726 // If DestVirtReg already has a value, use it.
727 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
728 DestPhysReg = chooseReg(MBB, MI, DestVirtReg);
729 MF->setPhysRegUsed(DestPhysReg);
730 markVirtRegModified(DestVirtReg);
731 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
732 }
733 }
734
735 // If this instruction defines any registers that are immediately dead,
736 // kill them now.
737 //
738 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
739 unsigned VirtReg = DeadDefs[i];
740 unsigned PhysReg = VirtReg;
741 if (MRegisterInfo::isVirtualRegister(VirtReg)) {
742 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
743 PhysReg = PhysRegSlot;
744 assert(PhysReg != 0);
745 PhysRegSlot = 0;
746 } else if (PhysRegsUsed[PhysReg] == -2) {
747 // Unallocatable register dead, ignore.
748 continue;
749 }
750
751 if (PhysReg) {
752 DOUT << " Register " << RegInfo->getName(PhysReg)
753 << " [%reg" << VirtReg
754 << "] is never used, removing it frame live list\n";
755 removePhysReg(PhysReg);
756 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
757 *AliasSet; ++AliasSet) {
758 if (PhysRegsUsed[*AliasSet] != -2) {
759 DOUT << " Register " << RegInfo->getName(*AliasSet)
760 << " [%reg" << *AliasSet
761 << "] is never used, removing it frame live list\n";
762 removePhysReg(*AliasSet);
763 }
764 }
765 }
766 }
767
768 // Finally, if this is a noop copy instruction, zap it.
769 unsigned SrcReg, DstReg;
770 if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
771 LV->removeVirtualRegistersKilled(MI);
772 LV->removeVirtualRegistersDead(MI);
773 MBB.erase(MI);
774 }
775 }
776
777 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
778
779 // Spill all physical registers holding virtual registers now.
780 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
781 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
782 if (unsigned VirtReg = PhysRegsUsed[i])
783 spillVirtReg(MBB, MI, VirtReg, i);
784 else
785 removePhysReg(i);
786
787 #if 0
788 // This checking code is very expensive.
789 bool AllOk = true;
790 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
791 e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i)
792 if (unsigned PR = Virt2PhysRegMap[i]) {
793 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
794 AllOk = false;
795 }
796 assert(AllOk && "Virtual registers still in phys regs?");
797 #endif
798
799 // Clear any physical register which appear live at the end of the basic
800 // block, but which do not hold any virtual registers. e.g., the stack
801 // pointer.
802 PhysRegsUseOrder.clear();
803 }
804
805 /// runOnMachineFunction - Register allocate the whole function
806 ///
807 bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
808 DOUT << "Machine Function " << "\n";
809 MF = &Fn;
810 TM = &Fn.getTarget();
811 RegInfo = TM->getRegisterInfo();
812 LV = &getAnalysis();
813
814 PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
815
816 // At various places we want to efficiently check to see whether a register
817 // is allocatable. To handle this, we mark all unallocatable registers as
818 // being pinned down, permanently.
819 {
820 BitVector Allocable = RegInfo->getAllocatableSet(Fn);
821 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
822 if (!Allocable[i])
823 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
824 }
825
826 // initialize the virtual->physical register map to have a 'null'
827 // mapping for all virtual registers
828 Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
829
830 // Loop over all of the basic blocks, eliminating virtual register references
831 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
832 MBB != MBBe; ++MBB) {
833 // fill out the read timetable
834 FillVRegReadTable(*MBB);
835 // use it to allocate the BB
836 AllocateBasicBlock(*MBB);
837 // clear it
838 VRegReadTable.clear();
839 }
840
841 StackSlotForVirtReg.clear();
842 PhysRegsUsed.clear();
843 VirtRegModified.clear();
844 Virt2PhysRegMap.clear();
845 return true;
846 }
847
848 FunctionPass *llvm::createBigBlockRegisterAllocator() {
849 return new RABigBlock();
850 }
851