llvm.org GIT mirror llvm / a87e40f
More refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135939 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
12 changed file(s) with 2112 addition(s) and 2112 deletion(s). Raw diff Collapse all Expand all
1313
1414 set(sources
1515 SSEDomainFix.cpp
16 X86AsmBackend.cpp
1716 X86AsmPrinter.cpp
1817 X86COFFMachineModuleInfo.cpp
1918 X86CodeEmitter.cpp
2524 X86ISelLowering.cpp
2625 X86InstrInfo.cpp
2726 X86JITInfo.cpp
28 X86MachObjectWriter.cpp
29 X86MCCodeEmitter.cpp
3027 X86MCInstLower.cpp
3128 X86RegisterInfo.cpp
3229 X86SelectionDAGInfo.cpp
0 add_llvm_library(LLVMX86Desc
1 X86AsmBackend.cpp
12 X86MCTargetDesc.cpp
23 X86MCAsmInfo.cpp
4 X86MCCodeEmitter.cpp
5 X86MachObjectWriter.cpp
36 )
47
58 # Hack: we need to include 'main' target directory to grab private headers
0 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/MC/TargetAsmBackend.h"
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionCOFF.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Object/MachOFormat.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegistry.h"
28 using namespace llvm;
29
30 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
31 // is useful when running bitwise comparison experiments on Darwin. We should be
32 // able to remove this once PR9807 is resolved.
33 static cl::opt
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
36
37 static unsigned getFixupKindLog2Size(unsigned Kind) {
38 switch (Kind) {
39 default: assert(0 && "invalid fixup kind!");
40 case FK_PCRel_1:
41 case FK_Data_1: return 0;
42 case FK_PCRel_2:
43 case FK_Data_2: return 1;
44 case FK_PCRel_4:
45 case X86::reloc_riprel_4byte:
46 case X86::reloc_riprel_4byte_movq_load:
47 case X86::reloc_signed_4byte:
48 case X86::reloc_global_offset_table:
49 case FK_Data_4: return 2;
50 case FK_PCRel_8:
51 case FK_Data_8: return 3;
52 }
53 }
54
55 namespace {
56
57 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
58 public:
59 X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
60 bool HasRelocationAddend)
61 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
62 };
63
64 class X86AsmBackend : public TargetAsmBackend {
65 public:
66 X86AsmBackend(const Target &T)
67 : TargetAsmBackend() {}
68
69 unsigned getNumFixupKinds() const {
70 return X86::NumTargetFixupKinds;
71 }
72
73 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
74 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
75 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
76 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
77 { "reloc_signed_4byte", 0, 4 * 8, 0},
78 { "reloc_global_offset_table", 0, 4 * 8, 0}
79 };
80
81 if (Kind < FirstTargetFixupKind)
82 return TargetAsmBackend::getFixupKindInfo(Kind);
83
84 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
85 "Invalid kind!");
86 return Infos[Kind - FirstTargetFixupKind];
87 }
88
89 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
90 uint64_t Value) const {
91 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
92
93 assert(Fixup.getOffset() + Size <= DataSize &&
94 "Invalid fixup offset!");
95 for (unsigned i = 0; i != Size; ++i)
96 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
97 }
98
99 bool MayNeedRelaxation(const MCInst &Inst) const;
100
101 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
102
103 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
104 };
105 } // end anonymous namespace
106
107 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
108 switch (Op) {
109 default:
110 return Op;
111
112 case X86::JAE_1: return X86::JAE_4;
113 case X86::JA_1: return X86::JA_4;
114 case X86::JBE_1: return X86::JBE_4;
115 case X86::JB_1: return X86::JB_4;
116 case X86::JE_1: return X86::JE_4;
117 case X86::JGE_1: return X86::JGE_4;
118 case X86::JG_1: return X86::JG_4;
119 case X86::JLE_1: return X86::JLE_4;
120 case X86::JL_1: return X86::JL_4;
121 case X86::JMP_1: return X86::JMP_4;
122 case X86::JNE_1: return X86::JNE_4;
123 case X86::JNO_1: return X86::JNO_4;
124 case X86::JNP_1: return X86::JNP_4;
125 case X86::JNS_1: return X86::JNS_4;
126 case X86::JO_1: return X86::JO_4;
127 case X86::JP_1: return X86::JP_4;
128 case X86::JS_1: return X86::JS_4;
129 }
130 }
131
132 static unsigned getRelaxedOpcodeArith(unsigned Op) {
133 switch (Op) {
134 default:
135 return Op;
136
137 // IMUL
138 case X86::IMUL16rri8: return X86::IMUL16rri;
139 case X86::IMUL16rmi8: return X86::IMUL16rmi;
140 case X86::IMUL32rri8: return X86::IMUL32rri;
141 case X86::IMUL32rmi8: return X86::IMUL32rmi;
142 case X86::IMUL64rri8: return X86::IMUL64rri32;
143 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
144
145 // AND
146 case X86::AND16ri8: return X86::AND16ri;
147 case X86::AND16mi8: return X86::AND16mi;
148 case X86::AND32ri8: return X86::AND32ri;
149 case X86::AND32mi8: return X86::AND32mi;
150 case X86::AND64ri8: return X86::AND64ri32;
151 case X86::AND64mi8: return X86::AND64mi32;
152
153 // OR
154 case X86::OR16ri8: return X86::OR16ri;
155 case X86::OR16mi8: return X86::OR16mi;
156 case X86::OR32ri8: return X86::OR32ri;
157 case X86::OR32mi8: return X86::OR32mi;
158 case X86::OR64ri8: return X86::OR64ri32;
159 case X86::OR64mi8: return X86::OR64mi32;
160
161 // XOR
162 case X86::XOR16ri8: return X86::XOR16ri;
163 case X86::XOR16mi8: return X86::XOR16mi;
164 case X86::XOR32ri8: return X86::XOR32ri;
165 case X86::XOR32mi8: return X86::XOR32mi;
166 case X86::XOR64ri8: return X86::XOR64ri32;
167 case X86::XOR64mi8: return X86::XOR64mi32;
168
169 // ADD
170 case X86::ADD16ri8: return X86::ADD16ri;
171 case X86::ADD16mi8: return X86::ADD16mi;
172 case X86::ADD32ri8: return X86::ADD32ri;
173 case X86::ADD32mi8: return X86::ADD32mi;
174 case X86::ADD64ri8: return X86::ADD64ri32;
175 case X86::ADD64mi8: return X86::ADD64mi32;
176
177 // SUB
178 case X86::SUB16ri8: return X86::SUB16ri;
179 case X86::SUB16mi8: return X86::SUB16mi;
180 case X86::SUB32ri8: return X86::SUB32ri;
181 case X86::SUB32mi8: return X86::SUB32mi;
182 case X86::SUB64ri8: return X86::SUB64ri32;
183 case X86::SUB64mi8: return X86::SUB64mi32;
184
185 // CMP
186 case X86::CMP16ri8: return X86::CMP16ri;
187 case X86::CMP16mi8: return X86::CMP16mi;
188 case X86::CMP32ri8: return X86::CMP32ri;
189 case X86::CMP32mi8: return X86::CMP32mi;
190 case X86::CMP64ri8: return X86::CMP64ri32;
191 case X86::CMP64mi8: return X86::CMP64mi32;
192
193 // PUSH
194 case X86::PUSHi8: return X86::PUSHi32;
195 case X86::PUSHi16: return X86::PUSHi32;
196 case X86::PUSH64i8: return X86::PUSH64i32;
197 case X86::PUSH64i16: return X86::PUSH64i32;
198 }
199 }
200
201 static unsigned getRelaxedOpcode(unsigned Op) {
202 unsigned R = getRelaxedOpcodeArith(Op);
203 if (R != Op)
204 return R;
205 return getRelaxedOpcodeBranch(Op);
206 }
207
208 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
209 // Branches can always be relaxed.
210 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
211 return true;
212
213 if (MCDisableArithRelaxation)
214 return false;
215
216 // Check if this instruction is ever relaxable.
217 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
218 return false;
219
220
221 // Check if it has an expression and is not RIP relative.
222 bool hasExp = false;
223 bool hasRIP = false;
224 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
225 const MCOperand &Op = Inst.getOperand(i);
226 if (Op.isExpr())
227 hasExp = true;
228
229 if (Op.isReg() && Op.getReg() == X86::RIP)
230 hasRIP = true;
231 }
232
233 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
234 // how we do relaxations?
235 return hasExp && !hasRIP;
236 }
237
238 // FIXME: Can tblgen help at all here to verify there aren't other instructions
239 // we can relax?
240 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
241 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
242 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
243
244 if (RelaxedOp == Inst.getOpcode()) {
245 SmallString<256> Tmp;
246 raw_svector_ostream OS(Tmp);
247 Inst.dump_pretty(OS);
248 OS << "\n";
249 report_fatal_error("unexpected instruction to relax: " + OS.str());
250 }
251
252 Res = Inst;
253 Res.setOpcode(RelaxedOp);
254 }
255
256 /// WriteNopData - Write optimal nops to the output file for the \arg Count
257 /// bytes. This returns the number of bytes written. It may return 0 if
258 /// the \arg Count is more than the maximum optimal nops.
259 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
260 static const uint8_t Nops[10][10] = {
261 // nop
262 {0x90},
263 // xchg %ax,%ax
264 {0x66, 0x90},
265 // nopl (%[re]ax)
266 {0x0f, 0x1f, 0x00},
267 // nopl 0(%[re]ax)
268 {0x0f, 0x1f, 0x40, 0x00},
269 // nopl 0(%[re]ax,%[re]ax,1)
270 {0x0f, 0x1f, 0x44, 0x00, 0x00},
271 // nopw 0(%[re]ax,%[re]ax,1)
272 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
273 // nopl 0L(%[re]ax)
274 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
275 // nopl 0L(%[re]ax,%[re]ax,1)
276 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
277 // nopw 0L(%[re]ax,%[re]ax,1)
278 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
279 // nopw %cs:0L(%[re]ax,%[re]ax,1)
280 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
281 };
282
283 // Write an optimal sequence for the first 15 bytes.
284 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
285 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
286 for (uint64_t i = 0, e = Prefixes; i != e; i++)
287 OW->Write8(0x66);
288 const uint64_t Rest = OptimalCount - Prefixes;
289 for (uint64_t i = 0, e = Rest; i != e; i++)
290 OW->Write8(Nops[Rest - 1][i]);
291
292 // Finish with single byte nops.
293 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
294 OW->Write8(0x90);
295
296 return true;
297 }
298
299 /* *** */
300
301 namespace {
302 class ELFX86AsmBackend : public X86AsmBackend {
303 public:
304 Triple::OSType OSType;
305 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
306 : X86AsmBackend(T), OSType(_OSType) {
307 HasReliableSymbolDifference = true;
308 }
309
310 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
311 const MCSectionELF &ES = static_cast(Section);
312 return ES.getFlags() & ELF::SHF_MERGE;
313 }
314 };
315
316 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
317 public:
318 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
319 : ELFX86AsmBackend(T, OSType) {}
320
321 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
322 return createELFObjectWriter(createELFObjectTargetWriter(),
323 OS, /*IsLittleEndian*/ true);
324 }
325
326 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
327 return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
328 }
329 };
330
331 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
332 public:
333 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
334 : ELFX86AsmBackend(T, OSType) {}
335
336 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
337 return createELFObjectWriter(createELFObjectTargetWriter(),
338 OS, /*IsLittleEndian*/ true);
339 }
340
341 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
342 return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
343 }
344 };
345
346 class WindowsX86AsmBackend : public X86AsmBackend {
347 bool Is64Bit;
348
349 public:
350 WindowsX86AsmBackend(const Target &T, bool is64Bit)
351 : X86AsmBackend(T)
352 , Is64Bit(is64Bit) {
353 }
354
355 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
356 return createWinCOFFObjectWriter(OS, Is64Bit);
357 }
358 };
359
360 class DarwinX86AsmBackend : public X86AsmBackend {
361 public:
362 DarwinX86AsmBackend(const Target &T)
363 : X86AsmBackend(T) { }
364 };
365
366 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
367 public:
368 DarwinX86_32AsmBackend(const Target &T)
369 : DarwinX86AsmBackend(T) {}
370
371 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
372 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
373 object::mach::CTM_i386,
374 object::mach::CSX86_ALL);
375 }
376 };
377
378 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
379 public:
380 DarwinX86_64AsmBackend(const Target &T)
381 : DarwinX86AsmBackend(T) {
382 HasReliableSymbolDifference = true;
383 }
384
385 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
386 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
387 object::mach::CTM_x86_64,
388 object::mach::CSX86_ALL);
389 }
390
391 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
392 // Temporary labels in the string literals sections require symbols. The
393 // issue is that the x86_64 relocation format does not allow symbol +
394 // offset, and so the linker does not have enough information to resolve the
395 // access to the appropriate atom unless an external relocation is used. For
396 // non-cstring sections, we expect the compiler to use a non-temporary label
397 // for anything that could have an addend pointing outside the symbol.
398 //
399 // See .
400 const MCSectionMachO &SMO = static_cast(Section);
401 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
402 }
403
404 virtual bool isSectionAtomizable(const MCSection &Section) const {
405 const MCSectionMachO &SMO = static_cast(Section);
406 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
407 switch (SMO.getType()) {
408 default:
409 return true;
410
411 case MCSectionMachO::S_4BYTE_LITERALS:
412 case MCSectionMachO::S_8BYTE_LITERALS:
413 case MCSectionMachO::S_16BYTE_LITERALS:
414 case MCSectionMachO::S_LITERAL_POINTERS:
415 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
416 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
417 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
418 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
419 case MCSectionMachO::S_INTERPOSING:
420 return false;
421 }
422 }
423 };
424
425 } // end anonymous namespace
426
427 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
428 const std::string &TT) {
429 Triple TheTriple(TT);
430
431 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
432 return new DarwinX86_32AsmBackend(T);
433
434 if (TheTriple.isOSWindows())
435 return new WindowsX86AsmBackend(T, false);
436
437 return new ELFX86_32AsmBackend(T, TheTriple.getOS());
438 }
439
440 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
441 const std::string &TT) {
442 Triple TheTriple(TT);
443
444 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
445 return new DarwinX86_64AsmBackend(T);
446
447 if (TheTriple.isOSWindows())
448 return new WindowsX86AsmBackend(T, true);
449
450 return new ELFX86_64AsmBackend(T, TheTriple.getOS());
451 }
0 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86MCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "mccodeemitter"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86FixupKinds.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/raw_ostream.h"
25
26 using namespace llvm;
27
28 namespace {
29 class X86MCCodeEmitter : public MCCodeEmitter {
30 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
31 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
32 const MCInstrInfo &MCII;
33 const MCSubtargetInfo &STI;
34 MCContext &Ctx;
35 public:
36 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
37 MCContext &ctx)
38 : MCII(mcii), STI(sti), Ctx(ctx) {
39 }
40
41 ~X86MCCodeEmitter() {}
42
43 bool is64BitMode() const {
44 // FIXME: Can tablegen auto-generate this?
45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
46 }
47
48 static unsigned GetX86RegNum(const MCOperand &MO) {
49 return X86_MC::getX86RegNum(MO.getReg());
50 }
51
52 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
53 // 0-7 and the difference between the 2 groups is given by the REX prefix.
54 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
55 // in 1's complement form, example:
56 //
57 // ModRM field => XMM9 => 1
58 // VEX.VVVV => XMM9 => ~9
59 //
60 // See table 4-35 of Intel AVX Programming Reference for details.
61 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
62 unsigned OpNum) {
63 unsigned SrcReg = MI.getOperand(OpNum).getReg();
64 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
65 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
66 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
67 SrcRegNum += 8;
68
69 // The registers represented through VEX_VVVV should
70 // be encoded in 1's complement form.
71 return (~SrcRegNum) & 0xf;
72 }
73
74 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
75 OS << (char)C;
76 ++CurByte;
77 }
78
79 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
80 raw_ostream &OS) const {
81 // Output the constant in little endian byte order.
82 for (unsigned i = 0; i != Size; ++i) {
83 EmitByte(Val & 255, CurByte, OS);
84 Val >>= 8;
85 }
86 }
87
88 void EmitImmediate(const MCOperand &Disp,
89 unsigned ImmSize, MCFixupKind FixupKind,
90 unsigned &CurByte, raw_ostream &OS,
91 SmallVectorImpl &Fixups,
92 int ImmOffset = 0) const;
93
94 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
95 unsigned RM) {
96 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
97 return RM | (RegOpcode << 3) | (Mod << 6);
98 }
99
100 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
101 unsigned &CurByte, raw_ostream &OS) const {
102 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
103 }
104
105 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
106 unsigned &CurByte, raw_ostream &OS) const {
107 // SIB byte is in the same format as the ModRMByte.
108 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
109 }
110
111
112 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
113 unsigned RegOpcodeField,
114 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
115 SmallVectorImpl &Fixups) const;
116
117 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
118 SmallVectorImpl &Fixups) const;
119
120 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
121 const MCInst &MI, const MCInstrDesc &Desc,
122 raw_ostream &OS) const;
123
124 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
125 int MemOperand, const MCInst &MI,
126 raw_ostream &OS) const;
127
128 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
129 const MCInst &MI, const MCInstrDesc &Desc,
130 raw_ostream &OS) const;
131 };
132
133 } // end anonymous namespace
134
135
136 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
137 const MCSubtargetInfo &STI,
138 MCContext &Ctx) {
139 return new X86MCCodeEmitter(MCII, STI, Ctx);
140 }
141
142 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
143 /// sign-extended field.
144 static bool isDisp8(int Value) {
145 return Value == (signed char)Value;
146 }
147
148 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
149 /// in an instruction with the specified TSFlags.
150 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
151 unsigned Size = X86II::getSizeOfImm(TSFlags);
152 bool isPCRel = X86II::isImmPCRel(TSFlags);
153
154 return MCFixup::getKindForSize(Size, isPCRel);
155 }
156
157 namespace llvm {
158 // FIXME: TableGen this?
159 extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc.
160 }
161
162 /// Is32BitMemOperand - Return true if the specified instruction with a memory
163 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
164 /// memory operand. Op specifies the operand # of the memoperand.
165 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
167 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
168
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
171 (IndexReg.getReg() != 0 &&
172 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
173 return true;
174 return false;
175 }
176
177 /// StartsWithGlobalOffsetTable - Return true for the simple cases where this
178 /// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
179 /// PIC on ELF i386 as that symbol is magic. We check only simple case that
180 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
181 /// of a binary expression.
182 static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
183 if (Expr->getKind() == MCExpr::Binary) {
184 const MCBinaryExpr *BE = static_cast(Expr);
185 Expr = BE->getLHS();
186 }
187
188 if (Expr->getKind() != MCExpr::SymbolRef)
189 return false;
190
191 const MCSymbolRefExpr *Ref = static_cast(Expr);
192 const MCSymbol &S = Ref->getSymbol();
193 return S.getName() == "_GLOBAL_OFFSET_TABLE_";
194 }
195
196 void X86MCCodeEmitter::
197 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
198 unsigned &CurByte, raw_ostream &OS,
199 SmallVectorImpl &Fixups, int ImmOffset) const {
200 const MCExpr *Expr = NULL;
201 if (DispOp.isImm()) {
202 // If this is a simple integer displacement that doesn't require a relocation,
203 // emit it now.
204 if (FixupKind != FK_PCRel_1 &&
205 FixupKind != FK_PCRel_2 &&
206 FixupKind != FK_PCRel_4) {
207 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
208 return;
209 }
210 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
211 } else {
212 Expr = DispOp.getExpr();
213 }
214
215 // If we have an immoffset, add it to the expression.
216 if ((FixupKind == FK_Data_4 ||
217 FixupKind == MCFixupKind(X86::reloc_signed_4byte)) &&
218 StartsWithGlobalOffsetTable(Expr)) {
219 assert(ImmOffset == 0);
220
221 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
222 ImmOffset = CurByte;
223 }
224
225 // If the fixup is pc-relative, we need to bias the value to be relative to
226 // the start of the field, not the end of the field.
227 if (FixupKind == FK_PCRel_4 ||
228 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
229 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
230 ImmOffset -= 4;
231 if (FixupKind == FK_PCRel_2)
232 ImmOffset -= 2;
233 if (FixupKind == FK_PCRel_1)
234 ImmOffset -= 1;
235
236 if (ImmOffset)
237 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
238 Ctx);
239
240 // Emit a symbolic constant as a fixup and 4 zeros.
241 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
242 EmitConstant(0, Size, CurByte, OS);
243 }
244
245 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
246 unsigned RegOpcodeField,
247 uint64_t TSFlags, unsigned &CurByte,
248 raw_ostream &OS,
249 SmallVectorImpl &Fixups) const{
250 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
251 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
252 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
253 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
254 unsigned BaseReg = Base.getReg();
255
256 // Handle %rip relative addressing.
257 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
258 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
259 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
260 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
261
262 unsigned FixupKind = X86::reloc_riprel_4byte;
263
264 // movq loads are handled with a special relocation form which allows the
265 // linker to eliminate some loads for GOT references which end up in the
266 // same linkage unit.
267 if (MI.getOpcode() == X86::MOV64rm)
268 FixupKind = X86::reloc_riprel_4byte_movq_load;
269
270 // rip-relative addressing is actually relative to the *next* instruction.
271 // Since an immediate can follow the mod/rm byte for an instruction, this
272 // means that we need to bias the immediate field of the instruction with
273 // the size of the immediate field. If we have this case, add it into the
274 // expression to emit.
275 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
276
277 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
278 CurByte, OS, Fixups, -ImmSize);
279 return;
280 }
281
282 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
283
284 // Determine whether a SIB byte is needed.
285 // If no BaseReg, issue a RIP relative instruction only if the MCE can
286 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
287 // 2-7) and absolute references.
288
289 if (// The SIB byte must be used if there is an index register.
290 IndexReg.getReg() == 0 &&
291 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
292 // encode to an R/M value of 4, which indicates that a SIB byte is
293 // present.
294 BaseRegNo != N86::ESP &&
295 // If there is no base register and we're in 64-bit mode, we need a SIB
296 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
297 (!is64BitMode() || BaseReg != 0)) {
298
299 if (BaseReg == 0) { // [disp32] in X86-32 mode
300 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
301 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
302 return;
303 }
304
305 // If the base is not EBP/ESP and there is no displacement, use simple
306 // indirect register encoding, this handles addresses like [EAX]. The
307 // encoding for [EBP] with no displacement means [disp32] so we handle it
308 // by emitting a displacement of 0 below.
309 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
310 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
311 return;
312 }
313
314 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
315 if (Disp.isImm() && isDisp8(Disp.getImm())) {
316 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
317 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
318 return;
319 }
320
321 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
322 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
323 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
324 Fixups);
325 return;
326 }
327
328 // We need a SIB byte, so start by outputting the ModR/M byte first
329 assert(IndexReg.getReg() != X86::ESP &&
330 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
331
332 bool ForceDisp32 = false;
333 bool ForceDisp8 = false;
334 if (BaseReg == 0) {
335 // If there is no base register, we emit the special case SIB byte with
336 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
337 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
338 ForceDisp32 = true;
339 } else if (!Disp.isImm()) {
340 // Emit the normal disp32 encoding.
341 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
342 ForceDisp32 = true;
343 } else if (Disp.getImm() == 0 &&
344 // Base reg can't be anything that ends up with '5' as the base
345 // reg, it is the magic [*] nomenclature that indicates no base.
346 BaseRegNo != N86::EBP) {
347 // Emit no displacement ModR/M byte
348 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
349 } else if (isDisp8(Disp.getImm())) {
350 // Emit the disp8 encoding.
351 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
352 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
353 } else {
354 // Emit the normal disp32 encoding.
355 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
356 }
357
358 // Calculate what the SS field value should be...
359 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
360 unsigned SS = SSTable[Scale.getImm()];
361
362 if (BaseReg == 0) {
363 // Handle the SIB byte for the case where there is no base, see Intel
364 // Manual 2A, table 2-7. The displacement has already been output.
365 unsigned IndexRegNo;
366 if (IndexReg.getReg())
367 IndexRegNo = GetX86RegNum(IndexReg);
368 else // Examples: [ESP+1*+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
369 IndexRegNo = 4;
370 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
371 } else {
372 unsigned IndexRegNo;
373 if (IndexReg.getReg())
374 IndexRegNo = GetX86RegNum(IndexReg);
375 else
376 IndexRegNo = 4; // For example [ESP+1*+4]
377 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
378 }
379
380 // Do we need to output a displacement?
381 if (ForceDisp8)
382 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
383 else if (ForceDisp32 || Disp.getImm() != 0)
384 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
385 Fixups);
386 }
387
388 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
389 /// called VEX.
390 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
391 int MemOperand, const MCInst &MI,
392 const MCInstrDesc &Desc,
393 raw_ostream &OS) const {
394 bool HasVEX_4V = false;
395 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
396 HasVEX_4V = true;
397
398 // VEX_R: opcode externsion equivalent to REX.R in
399 // 1's complement (inverted) form
400 //
401 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
402 // 0: Same as REX_R=1 (64 bit mode only)
403 //
404 unsigned char VEX_R = 0x1;
405
406 // VEX_X: equivalent to REX.X, only used when a
407 // register is used for index in SIB Byte.
408 //
409 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
410 // 0: Same as REX.X=1 (64-bit mode only)
411 unsigned char VEX_X = 0x1;
412
413 // VEX_B:
414 //
415 // 1: Same as REX_B=0 (ignored in 32-bit mode)
416 // 0: Same as REX_B=1 (64 bit mode only)
417 //
418 unsigned char VEX_B = 0x1;
419
420 // VEX_W: opcode specific (use like REX.W, or used for
421 // opcode extension, or ignored, depending on the opcode byte)
422 unsigned char VEX_W = 0;
423
424 // VEX_5M (VEX m-mmmmm field):
425 //
426 // 0b00000: Reserved for future use
427 // 0b00001: implied 0F leading opcode
428 // 0b00010: implied 0F 38 leading opcode bytes
429 // 0b00011: implied 0F 3A leading opcode bytes
430 // 0b00100-0b11111: Reserved for future use
431 //
432 unsigned char VEX_5M = 0x1;
433
434 // VEX_4V (VEX vvvv field): a register specifier
435 // (in 1's complement form) or 1111 if unused.
436 unsigned char VEX_4V = 0xf;
437
438 // VEX_L (Vector Length):
439 //
440 // 0: scalar or 128-bit vector
441 // 1: 256-bit vector
442 //
443 unsigned char VEX_L = 0;
444
445 // VEX_PP: opcode extension providing equivalent
446 // functionality of a SIMD prefix
447 //
448 // 0b00: None
449 // 0b01: 66
450 // 0b10: F3
451 // 0b11: F2
452 //
453 unsigned char VEX_PP = 0;
454
455 // Encode the operand size opcode prefix as needed.
456 if (TSFlags & X86II::OpSize)
457 VEX_PP = 0x01;
458
459 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
460 VEX_W = 1;
461
462 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
463 VEX_L = 1;
464
465 switch (TSFlags & X86II::Op0Mask) {
466 default: assert(0 && "Invalid prefix!");
467 case X86II::T8: // 0F 38
468 VEX_5M = 0x2;
469 break;
470 case X86II::TA: // 0F 3A
471 VEX_5M = 0x3;
472 break;
473 case X86II::TF: // F2 0F 38
474 VEX_PP = 0x3;
475 VEX_5M = 0x2;
476 break;
477 case X86II::XS: // F3 0F
478 VEX_PP = 0x2;
479 break;
480 case X86II::XD: // F2 0F
481 VEX_PP = 0x3;
482 break;
483 case X86II::A6: // Bypass: Not used by VEX
484 case X86II::A7: // Bypass: Not used by VEX
485 case X86II::TB: // Bypass: Not used by VEX
486 case 0:
487 break; // No prefix!
488 }
489
490 // Set the vector length to 256-bit if YMM0-YMM15 is used
491 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
492 if (!MI.getOperand(i).isReg())
493 continue;
494 unsigned SrcReg = MI.getOperand(i).getReg();
495 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
496 VEX_L = 1;
497 }
498
499 unsigned NumOps = MI.getNumOperands();
500 unsigned CurOp = 0;
501 bool IsDestMem = false;
502
503 switch (TSFlags & X86II::FormMask) {
504 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
505 case X86II::MRMDestMem:
506 IsDestMem = true;
507 // The important info for the VEX prefix is never beyond the address
508 // registers. Don't check beyond that.
509 NumOps = CurOp = X86::AddrNumOperands;
510 case X86II::MRM0m: case X86II::MRM1m:
511 case X86II::MRM2m: case X86II::MRM3m:
512 case X86II::MRM4m: case X86II::MRM5m:
513 case X86II::MRM6m: case X86II::MRM7m:
514 case X86II::MRMSrcMem:
515 case X86II::MRMSrcReg:
516 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
517 X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
518 VEX_R = 0x0;
519 CurOp++;
520
521 if (HasVEX_4V) {
522 VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
523 CurOp++;
524 }
525
526 // To only check operands before the memory address ones, start
527 // the search from the beginning
528 if (IsDestMem)
529 CurOp = 0;
530
531 // If the last register should be encoded in the immediate field
532 // do not use any bit from VEX prefix to this register, ignore it
533 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
534 NumOps--;
535
536 for (; CurOp != NumOps; ++CurOp) {
537 const MCOperand &MO = MI.getOperand(CurOp);
538 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
539 VEX_B = 0x0;
540 if (!VEX_B && MO.isReg() &&
541 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
542 X86II::isX86_64ExtendedReg(MO.getReg()))
543 VEX_X = 0x0;
544 }
545 break;
546 default: // MRMDestReg, MRM0r-MRM7r, RawFrm
547 if (!MI.getNumOperands())
548 break;
549
550 if (MI.getOperand(CurOp).isReg() &&
551 X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
552 VEX_B = 0;
553
554 if (HasVEX_4V)
555 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
556
557 CurOp++;
558 for (; CurOp != NumOps; ++CurOp) {
559 const MCOperand &MO = MI.getOperand(CurOp);
560 if (MO.isReg() && !HasVEX_4V &&
561 X86II::isX86_64ExtendedReg(MO.getReg()))
562 VEX_R = 0x0;
563 }
564 break;
565 }
566
567 // Emit segment override opcode prefix as needed.
568 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
569
570 // VEX opcode prefix can have 2 or 3 bytes
571 //
572 // 3 bytes:
573 // +-----+ +--------------+ +-------------------+
574 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
575 // +-----+ +--------------+ +-------------------+
576 // 2 bytes:
577 // +-----+ +-------------------+
578 // | C5h | | R | vvvv | L | pp |
579 // +-----+ +-------------------+
580 //
581 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
582
583 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
584 EmitByte(0xC5, CurByte, OS);
585 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
586 return;
587 }
588
589 // 3 byte VEX prefix
590 EmitByte(0xC4, CurByte, OS);
591 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
592 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
593 }
594
595 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
596 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
597 /// size, and 3) use of X86-64 extended registers.
598 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
599 const MCInstrDesc &Desc) {
600 unsigned REX = 0;
601 if (TSFlags & X86II::REX_W)
602 REX |= 1 << 3; // set REX.W
603
604 if (MI.getNumOperands() == 0) return REX;
605
606 unsigned NumOps = MI.getNumOperands();
607 // FIXME: MCInst should explicitize the two-addrness.
608 bool isTwoAddr = NumOps > 1 &&
609 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
610
611 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
612 unsigned i = isTwoAddr ? 1 : 0;
613 for (; i != NumOps; ++i) {
614 const MCOperand &MO = MI.getOperand(i);
615 if (!MO.isReg()) continue;
616 unsigned Reg = MO.getReg();
617 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
618 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
619 // that returns non-zero.
620 REX |= 0x40; // REX fixed encoding prefix
621 break;
622 }
623
624 switch (TSFlags & X86II::FormMask) {
625 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
626 case X86II::MRMSrcReg:
627 if (MI.getOperand(0).isReg() &&
628 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
629 REX |= 1 << 2; // set REX.R
630 i = isTwoAddr ? 2 : 1;
631 for (; i != NumOps; ++i) {
632 const MCOperand &MO = MI.getOperand(i);
633 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
634 REX |= 1 << 0; // set REX.B
635 }
636 break;
637 case X86II::MRMSrcMem: {
638 if (MI.getOperand(0).isReg() &&
639 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
640 REX |= 1 << 2; // set REX.R
641 unsigned Bit = 0;
642 i = isTwoAddr ? 2 : 1;
643 for (; i != NumOps; ++i) {
644 const MCOperand &MO = MI.getOperand(i);
645 if (MO.isReg()) {
646 if (X86II::isX86_64ExtendedReg(MO.getReg()))
647 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
648 Bit++;
649 }
650 }
651 break;
652 }
653 case X86II::MRM0m: case X86II::MRM1m:
654 case X86II::MRM2m: case X86II::MRM3m:
655 case X86II::MRM4m: case X86II::MRM5m:
656 case X86II::MRM6m: case X86II::MRM7m:
657 case X86II::MRMDestMem: {
658 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
659 i = isTwoAddr ? 1 : 0;
660 if (NumOps > e && MI.getOperand(e).isReg() &&
661 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
662 REX |= 1 << 2; // set REX.R
663 unsigned Bit = 0;
664 for (; i != e; ++i) {
665 const MCOperand &MO = MI.getOperand(i);
666 if (MO.isReg()) {
667 if (X86II::isX86_64ExtendedReg(MO.getReg()))
668 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
669 Bit++;
670 }
671 }
672 break;
673 }
674 default:
675 if (MI.getOperand(0).isReg() &&
676 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
677 REX |= 1 << 0; // set REX.B
678 i = isTwoAddr ? 2 : 1;
679 for (unsigned e = NumOps; i != e; ++i) {
680 const MCOperand &MO = MI.getOperand(i);
681 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
682 REX |= 1 << 2; // set REX.R
683 }
684 break;
685 }
686 return REX;
687 }
688
689 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
690 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
691 unsigned &CurByte, int MemOperand,
692 const MCInst &MI,
693 raw_ostream &OS) const {
694 switch (TSFlags & X86II::SegOvrMask) {
695 default: assert(0 && "Invalid segment!");
696 case 0:
697 // No segment override, check for explicit one on memory operand.
698 if (MemOperand != -1) { // If the instruction has a memory operand.
699 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
700 default: assert(0 && "Unknown segment register!");
701 case 0: break;
702 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
703 case X86::SS: EmitByte(0x36, CurByte, OS); break;
704 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
705 case X86::ES: EmitByte(0x26, CurByte, OS); break;
706 case X86::FS: EmitByte(0x64, CurByte, OS); break;
707 case X86::GS: EmitByte(0x65, CurByte, OS); break;
708 }
709 }
710 break;
711 case X86II::FS:
712 EmitByte(0x64, CurByte, OS);
713 break;
714 case X86II::GS:
715 EmitByte(0x65, CurByte, OS);
716 break;
717 }
718 }
719
720 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
721 ///
722 /// MemOperand is the operand # of the start of a memory operand if present. If
723 /// Not present, it is -1.
724 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
725 int MemOperand, const MCInst &MI,
726 const MCInstrDesc &Desc,
727 raw_ostream &OS) const {
728
729 // Emit the lock opcode prefix as needed.
730 if (TSFlags & X86II::LOCK)
731 EmitByte(0xF0, CurByte, OS);
732
733 // Emit segment override opcode prefix as needed.
734 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
735
736 // Emit the repeat opcode prefix as needed.
737 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
738 EmitByte(0xF3, CurByte, OS);
739
740 // Emit the address size opcode prefix as needed.
741 if ((TSFlags & X86II::AdSize) ||
742 (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand)))
743 EmitByte(0x67, CurByte, OS);
744
745 // Emit the operand size opcode prefix as needed.
746 if (TSFlags & X86II::OpSize)
747 EmitByte(0x66, CurByte, OS);
748
749 bool Need0FPrefix = false;
750 switch (TSFlags & X86II::Op0Mask) {
751 default: assert(0 && "Invalid prefix!");
752 case 0: break; // No prefix!
753 case X86II::REP: break; // already handled.
754 case X86II::TB: // Two-byte opcode prefix
755 case X86II::T8: // 0F 38
756 case X86II::TA: // 0F 3A
757 case X86II::A6: // 0F A6
758 case X86II::A7: // 0F A7
759 Need0FPrefix = true;
760 break;
761 case X86II::TF: // F2 0F 38
762 EmitByte(0xF2, CurByte, OS);
763 Need0FPrefix = true;
764 break;
765 case X86II::XS: // F3 0F
766 EmitByte(0xF3, CurByte, OS);
767 Need0FPrefix = true;
768 break;
769 case X86II::XD: // F2 0F
770 EmitByte(0xF2, CurByte, OS);
771 Need0FPrefix = true;
772 break;
773 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
774 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
775 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
776 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
777 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
778 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
779 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
780 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
781 }
782
783 // Handle REX prefix.
784 // FIXME: Can this come before F2 etc to simplify emission?
785 if (is64BitMode()) {
786 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
787 EmitByte(0x40 | REX, CurByte, OS);
788 }
789
790 // 0x0F escape code must be emitted just before the opcode.
791 if (Need0FPrefix)
792 EmitByte(0x0F, CurByte, OS);
793
794 // FIXME: Pull this up into previous switch if REX can be moved earlier.
795 switch (TSFlags & X86II::Op0Mask) {
796 case X86II::TF: // F2 0F 38
797 case X86II::T8: // 0F 38
798 EmitByte(0x38, CurByte, OS);
799 break;
800 case X86II::TA: // 0F 3A
801 EmitByte(0x3A, CurByte, OS);
802 break;
803 case X86II::A6: // 0F A6
804 EmitByte(0xA6, CurByte, OS);
805 break;
806 case X86II::A7: // 0F A7
807 EmitByte(0xA7, CurByte, OS);
808 break;
809 }
810 }
811
812 void X86MCCodeEmitter::
813 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
814 SmallVectorImpl &Fixups) const {
815 unsigned Opcode = MI.getOpcode();
816 const MCInstrDesc &Desc = MCII.get(Opcode);
817 uint64_t TSFlags = Desc.TSFlags;
818
819 // Pseudo instructions don't get encoded.
820 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
821 return;
822
823 // If this is a two-address instruction, skip one of the register operands.
824 // FIXME: This should be handled during MCInst lowering.
825 unsigned NumOps = Desc.getNumOperands();
826 unsigned CurOp = 0;
827 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
828 ++CurOp;
829 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0)
830 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
831 --NumOps;
832
833 // Keep track of the current byte being emitted.
834 unsigned CurByte = 0;
835
836 // Is this instruction encoded using the AVX VEX prefix?
837 bool HasVEXPrefix = false;
838
839 // It uses the VEX.VVVV field?
840 bool HasVEX_4V = false;
841
842 if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
843 HasVEXPrefix = true;
844 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
845 HasVEX_4V = true;
846
847
848 // Determine where the memory operand starts, if present.
849 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
850 if (MemoryOperand != -1) MemoryOperand += CurOp;
851
852 if (!HasVEXPrefix)
853 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
854 else
855 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
856
857
858 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
859
860 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
861 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
862
863 unsigned SrcRegNum = 0;
864 switch (TSFlags & X86II::FormMask) {
865 case X86II::MRMInitReg:
866 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
867 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
868 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
869 case X86II::Pseudo:
870 assert(0 && "Pseudo instruction shouldn't be emitted");
871 case X86II::RawFrm:
872 EmitByte(BaseOpcode, CurByte, OS);
873 break;
874
875 case X86II::RawFrmImm8:
876 EmitByte(BaseOpcode, CurByte, OS);
877 EmitImmediate(MI.getOperand(CurOp++),
878 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
879 CurByte, OS, Fixups);
880 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
881 break;
882 case X86II::RawFrmImm16:
883 EmitByte(BaseOpcode, CurByte, OS);
884 EmitImmediate(MI.getOperand(CurOp++),
885 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
886 CurByte, OS, Fixups);
887 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
888 break;
889
890 case X86II::AddRegFrm:
891 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
892 break;
893
894 case X86II::MRMDestReg:
895 EmitByte(BaseOpcode, CurByte, OS);
896 EmitRegModRMByte(MI.getOperand(CurOp),
897 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
898 CurOp += 2;
899 break;
900
901 case X86II::MRMDestMem:
902 EmitByte(BaseOpcode, CurByte, OS);
903 SrcRegNum = CurOp + X86::AddrNumOperands;
904
905 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
906 SrcRegNum++;
907
908 EmitMemModRMByte(MI, CurOp,
909 GetX86RegNum(MI.getOperand(SrcRegNum)),
910 TSFlags, CurByte, OS, Fixups);
911 CurOp = SrcRegNum + 1;
912 break;
913
914 case X86II::MRMSrcReg:
915 EmitByte(BaseOpcode, CurByte, OS);
916 SrcRegNum = CurOp + 1;
917
918 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
919 SrcRegNum++;
920
921 EmitRegModRMByte(MI.getOperand(SrcRegNum),
922 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
923 CurOp = SrcRegNum + 1;
924 break;
925
926 case X86II::MRMSrcMem: {
927 int AddrOperands = X86::AddrNumOperands;
928 unsigned FirstMemOp = CurOp+1;
929 if (HasVEX_4V) {
930 ++AddrOperands;
931 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
932 }
933
934 EmitByte(BaseOpcode, CurByte, OS);
935
936 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
937 TSFlags, CurByte, OS, Fixups);
938 CurOp += AddrOperands + 1;
939 break;
940 }
941
942 case X86II::MRM0r: case X86II::MRM1r:
943 case X86II::MRM2r: case X86II::MRM3r:
944 case X86II::MRM4r: case X86II::MRM5r:
945 case X86II::MRM6r: case X86II::MRM7r:
946 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
947 CurOp++;
948 EmitByte(BaseOpcode, CurByte, OS);
949 EmitRegModRMByte(MI.getOperand(CurOp++),
950 (TSFlags & X86II::FormMask)-X86II::MRM0r,
951 CurByte, OS);
952 break;
953 case X86II::MRM0m: case X86II::MRM1m:
954 case X86II::MRM2m: case X86II::MRM3m:
955 case X86II::MRM4m: case X86II::MRM5m:
956 case X86II::MRM6m: case X86II::MRM7m:
957 EmitByte(BaseOpcode, CurByte, OS);
958 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
959 TSFlags, CurByte, OS, Fixups);
960 CurOp += X86::AddrNumOperands;
961 break;
962 case X86II::MRM_C1:
963 EmitByte(BaseOpcode, CurByte, OS);
964 EmitByte(0xC1, CurByte, OS);
965 break;
966 case X86II::MRM_C2:
967 EmitByte(BaseOpcode, CurByte, OS);
968 EmitByte(0xC2, CurByte, OS);
969 break;
970 case X86II::MRM_C3:
971 EmitByte(BaseOpcode, CurByte, OS);
972 EmitByte(0xC3, CurByte, OS);
973 break;
974 case X86II::MRM_C4:
975 EmitByte(BaseOpcode, CurByte, OS);
976 EmitByte(0xC4, CurByte, OS);
977 break;
978 case X86II::MRM_C8:
979 EmitByte(BaseOpcode, CurByte, OS);
980 EmitByte(0xC8, CurByte, OS);
981 break;
982 case X86II::MRM_C9:
983 EmitByte(BaseOpcode, CurByte, OS);
984 EmitByte(0xC9, CurByte, OS);
985 break;
986 case X86II::MRM_E8:
987 EmitByte(BaseOpcode, CurByte, OS);
988 EmitByte(0xE8, CurByte, OS);
989 break;
990 case X86II::MRM_F0:
991 EmitByte(BaseOpcode, CurByte, OS);
992 EmitByte(0xF0, CurByte, OS);
993 break;
994 case X86II::MRM_F8:
995 EmitByte(BaseOpcode, CurByte, OS);
996 EmitByte(0xF8, CurByte, OS);
997 break;
998 case X86II::MRM_F9:
999 EmitByte(BaseOpcode, CurByte, OS);
1000 EmitByte(0xF9, CurByte, OS);
1001 break;
1002 case X86II::MRM_D0:
1003 EmitByte(BaseOpcode, CurByte, OS);
1004 EmitByte(0xD0, CurByte, OS);
1005 break;
1006 case X86II::MRM_D1:
1007 EmitByte(BaseOpcode, CurByte, OS);
1008 EmitByte(0xD1, CurByte, OS);
1009 break;
1010 }
1011
1012 // If there is a remaining operand, it must be a trailing immediate. Emit it
1013 // according to the right size for the instruction.
1014 if (CurOp != NumOps) {
1015 // The last source register of a 4 operand instruction in AVX is encoded
1016 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
1017 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1018 const MCOperand &MO = MI.getOperand(CurOp++);
1019 bool IsExtReg =
1020 X86II::isX86_64ExtendedReg(MO.getReg());
1021 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1022 RegNum |= GetX86RegNum(MO) << 4;
1023 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
1024 Fixups);
1025 } else {
1026 unsigned FixupKind;
1027 // FIXME: Is there a better way to know that we need a signed relocation?
1028 if (MI.getOpcode() == X86::ADD64ri32 ||
1029 MI.getOpcode() == X86::MOV64ri32 ||
1030 MI.getOpcode() == X86::MOV64mi32 ||
1031 MI.getOpcode() == X86::PUSH64i32)
1032 FixupKind = X86::reloc_signed_4byte;
1033 else
1034 FixupKind = getImmFixupKind(TSFlags);
1035 EmitImmediate(MI.getOperand(CurOp++),
1036 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1037 CurByte, OS, Fixups);
1038 }
1039 }
1040
1041 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1042 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1043
1044
1045 #ifndef NDEBUG
1046 // FIXME: Verify.
1047 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1048 errs() << "Cannot encode all operands of: ";
1049 MI.dump();
1050 errs() << '\n';
1051 abort();
1052 }
1053 #endif
1054 }
1515 #include "llvm/MC/MachineLocation.h"
1616 #include "llvm/MC/MCInstrInfo.h"
1717 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/MC/MCStreamer.h"
1819 #include "llvm/MC/MCSubtargetInfo.h"
1920 #include "llvm/Target/TargetRegistry.h"
2021 #include "llvm/ADT/Triple.h"
362363 return X;
363364 }
364365
366 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
367 MCContext &Ctx, TargetAsmBackend &TAB,
368 raw_ostream &_OS,
369 MCCodeEmitter *_Emitter,
370 bool RelaxAll,
371 bool NoExecStack) {
372 Triple TheTriple(TT);
373
374 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
375 return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
376
377 if (TheTriple.isOSWindows())
378 return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
379
380 return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack);
381 }
382
365383 // Force static initialization.
366384 extern "C" void LLVMInitializeX86TargetMC() {
367385 // Register the MC asm info.
385403 X86_MC::createX86MCSubtargetInfo);
386404 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
387405 X86_MC::createX86MCSubtargetInfo);
388 }
406
407 // Register the code emitter.
408 TargetRegistry::RegisterCodeEmitter(TheX86_32Target,
409 createX86MCCodeEmitter);
410 TargetRegistry::RegisterCodeEmitter(TheX86_64Target,
411 createX86MCCodeEmitter);
412
413 // Register the asm backend.
414 TargetRegistry::RegisterAsmBackend(TheX86_32Target,
415 createX86_32AsmBackend);
416 TargetRegistry::RegisterAsmBackend(TheX86_64Target,
417 createX86_64AsmBackend);
418
419 // Register the object streamer.
420 TargetRegistry::RegisterObjectStreamer(TheX86_32Target,
421 createMCStreamer);
422 TargetRegistry::RegisterObjectStreamer(TheX86_64Target,
423 createMCStreamer);
424 }
1919 class MCCodeEmitter;
2020 class MCContext;
2121 class MCInstrInfo;
22 class MCObjectWriter;
2223 class MCRegisterInfo;
2324 class MCSubtargetInfo;
2425 class Target;
26 class TargetAsmBackend;
2527 class StringRef;
28 class raw_ostream;
2629
2730 extern Target TheX86_32Target, TheX86_64Target;
2831
6972 const MCSubtargetInfo &STI,
7073 MCContext &Ctx);
7174
75 TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &);
76 TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &);
77
78 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
79 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
80 bool Is64Bit,
81 uint32_t CPUType,
82 uint32_t CPUSubtype);
7283
7384 } // End llvm namespace
7485
0 //===-- X86MachObjectWriter.cpp - X86 Mach-O Writer -----------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/X86FixupKinds.h"
10 #include "MCTargetDesc/X86MCTargetDesc.h"
11 #include "llvm/MC/MCAssembler.h"
12 #include "llvm/MC/MCAsmLayout.h"
13 #include "llvm/MC/MCMachObjectWriter.h"
14 #include "llvm/MC/MCSectionMachO.h"
15 #include "llvm/MC/MCValue.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/Support/ErrorHandling.h"
18 #include "llvm/Object/MachOFormat.h"
19
20 using namespace llvm;
21 using namespace llvm::object;
22
23 namespace {
24 class X86MachObjectWriter : public MCMachObjectTargetWriter {
25 void RecordScatteredRelocation(MachObjectWriter *Writer,
26 const MCAssembler &Asm,
27 const MCAsmLayout &Layout,
28 const MCFragment *Fragment,
29 const MCFixup &Fixup,
30 MCValue Target,
31 unsigned Log2Size,
32 uint64_t &FixedValue);
33 void RecordTLVPRelocation(MachObjectWriter *Writer,
34 const MCAssembler &Asm,
35 const MCAsmLayout &Layout,
36 const MCFragment *Fragment,
37 const MCFixup &Fixup,
38 MCValue Target,
39 uint64_t &FixedValue);
40
41 void RecordX86Relocation(MachObjectWriter *Writer,
42 const MCAssembler &Asm,
43 const MCAsmLayout &Layout,
44 const MCFragment *Fragment,
45 const MCFixup &Fixup,
46 MCValue Target,
47 uint64_t &FixedValue);
48 void RecordX86_64Relocation(MachObjectWriter *Writer,
49 const MCAssembler &Asm,
50 const MCAsmLayout &Layout,
51 const MCFragment *Fragment,
52 const MCFixup &Fixup,
53 MCValue Target,
54 uint64_t &FixedValue);
55 public:
56 X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
57 uint32_t CPUSubtype)
58 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
59 /*UseAggressiveSymbolFolding=*/Is64Bit) {}
60
61 void RecordRelocation(MachObjectWriter *Writer,
62 const MCAssembler &Asm, const MCAsmLayout &Layout,
63 const MCFragment *Fragment, const MCFixup &Fixup,
64 MCValue Target, uint64_t &FixedValue) {
65 if (Writer->is64Bit())
66 RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
67 FixedValue);
68 else
69 RecordX86Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
70 FixedValue);
71 }
72 };
73 }
74
75 static bool isFixupKindRIPRel(unsigned Kind) {
76 return Kind == X86::reloc_riprel_4byte ||
77 Kind == X86::reloc_riprel_4byte_movq_load;
78 }
79
80 static unsigned getFixupKindLog2Size(unsigned Kind) {
81 switch (Kind) {
82 default:
83 llvm_unreachable("invalid fixup kind!");
84 case FK_PCRel_1:
85 case FK_Data_1: return 0;
86 case FK_PCRel_2:
87 case FK_Data_2: return 1;
88 case FK_PCRel_4:
89 // FIXME: Remove these!!!
90 case X86::reloc_riprel_4byte:
91 case X86::reloc_riprel_4byte_movq_load:
92 case X86::reloc_signed_4byte:
93 case FK_Data_4: return 2;
94 case FK_Data_8: return 3;
95 }
96 }
97
98 void X86MachObjectWriter::RecordX86_64Relocation(MachObjectWriter *Writer,
99 const MCAssembler &Asm,
100 const MCAsmLayout &Layout,
101 const MCFragment *Fragment,
102 const MCFixup &Fixup,
103 MCValue Target,
104 uint64_t &FixedValue) {
105 unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
106 unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
107 unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
108
109 // See .
110 uint32_t FixupOffset =
111 Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
112 uint32_t FixupAddress =
113 Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
114 int64_t Value = 0;
115 unsigned Index = 0;
116 unsigned IsExtern = 0;
117 unsigned Type = 0;
118
119 Value = Target.getConstant();
120
121 if (IsPCRel) {
122 // Compensate for the relocation offset, Darwin x86_64 relocations only have
123 // the addend and appear to have attempted to define it to be the actual
124 // expression addend without the PCrel bias. However, instructions with data
125 // following the relocation are not accommodated for (see comment below
126 // regarding SIGNED{1,2,4}), so it isn't exactly that either.
127 Value += 1LL << Log2Size;
128 }
129
130 if (Target.isAbsolute()) { // constant
131 // SymbolNum of 0 indicates the absolute section.
132 Type = macho::RIT_X86_64_Unsigned;
133 Index = 0;
134
135 // FIXME: I believe this is broken, I don't think the linker can understand
136 // it. I think it would require a local relocation, but I'm not sure if that
137 // would work either. The official way to get an absolute PCrel relocation
138 // is to use an absolute symbol (which we don't support yet).
139 if (IsPCRel) {
140 IsExtern = 1;
141 Type = macho::RIT_X86_64_Branch;
142 }
143 } else if (Target.getSymB()) { // A - B + constant
144 const MCSymbol *A = &Target.getSymA()->getSymbol();
145 MCSymbolData &A_SD = Asm.getSymbolData(*A);
146 const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
147
148 const MCSymbol *B = &Target.getSymB()->getSymbol();
149 MCSymbolData &B_SD = Asm.getSymbolData(*B);
150 const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
151
152 // Neither symbol can be modified.
153 if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
154 Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
155 report_fatal_error("unsupported relocation of modified symbol");
156
157 // We don't support PCrel relocations of differences. Darwin 'as' doesn't
158 // implement most of these correctly.
159 if (IsPCRel)
160 report_fatal_error("unsupported pc-relative relocation of difference");
161
162 // The support for the situation where one or both of the symbols would
163 // require a local relocation is handled just like if the symbols were
164 // external. This is certainly used in the case of debug sections where the
165 // section has only temporary symbols and thus the symbols don't have base
166 // symbols. This is encoded using the section ordinal and non-extern
167 // relocation entries.
168
169 // Darwin 'as' doesn't emit correct relocations for this (it ends up with a
170 // single SIGNED relocation); reject it for now. Except the case where both
171 // symbols don't have a base, equal but both NULL.
172 if (A_Base == B_Base && A_Base)
173 report_fatal_error("unsupported relocation with identical base");
174
175 Value += Writer->getSymbolAddress(&A_SD, Layout) -
176 (A_Base == NULL ? 0 : Writer->getSymbolAddress(A_Base, Layout));
177 Value -= Writer->getSymbolAddress(&B_SD, Layout) -
178 (B_Base == NULL ? 0 : Writer->getSymbolAddress(B_Base, Layout));
179
180 if (A_Base) {
181 Index = A_Base->getIndex();
182 IsExtern = 1;
183 }
184 else {
185 Index = A_SD.getFragment()->getParent()->getOrdinal() + 1;
186 IsExtern = 0;
187 }
188 Type = macho::RIT_X86_64_Unsigned;
189
190 macho::RelocationEntry MRE;
191 MRE.Word0 = FixupOffset;
192 MRE.Word1 = ((Index << 0) |
193 (IsPCRel << 24) |
194 (Log2Size << 25) |
195 (IsExtern << 27) |
196 (Type << 28));
197 Writer->addRelocation(Fragment->getParent(), MRE);
198
199 if (B_Base) {
200 Index = B_Base->getIndex();
201 IsExtern = 1;
202 }
203 else {
204 Index = B_SD.getFragment()->getParent()->getOrdinal() + 1;
205 IsExtern = 0;
206 }
207 Type = macho::RIT_X86_64_Subtractor;
208 } else {
209 const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
210 MCSymbolData &SD = Asm.getSymbolData(*Symbol);
211 const MCSymbolData *Base = Asm.getAtom(&SD);
212
213 // Relocations inside debug sections always use local relocations when
214 // possible. This seems to be done because the debugger doesn't fully
215 // understand x86_64 relocation entries, and expects to find values that
216 // have already been fixed up.
217 if (Symbol->isInSection()) {
218 const MCSectionMachO &Section = static_cast(
219 Fragment->getParent()->getSection());
220 if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG))
221 Base = 0;
222 }
223
224 // x86_64 almost always uses external relocations, except when there is no
225 // symbol to use as a base address (a local symbol with no preceding
226 // non-local symbol).
227 if (Base) {
228 Index = Base->getIndex();
229 IsExtern = 1;
230
231 // Add the local offset, if needed.
232 if (Base != &SD)
233 Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
234 } else if (Symbol->isInSection() && !Symbol->isVariable()) {
235 // The index is the section ordinal (1-based).
236 Index = SD.getFragment()->getParent()->getOrdinal() + 1;
237 IsExtern = 0;
238 Value += Writer->getSymbolAddress(&SD, Layout);
239
240 if (IsPCRel)
241 Value -= FixupAddress + (1 << Log2Size);
242 } else if (Symbol->isVariable()) {
243 const MCExpr *Value = Symbol->getVariableValue();
244 int64_t Res;
245 bool isAbs = Value->EvaluateAsAbsolute(Res, Layout,
246 Writer->getSectionAddressMap());
247 if (isAbs) {
248 FixedValue = Res;
249 return;
250 } else {
251 report_fatal_error("unsupported relocation of variable '" +
252 Symbol->getName() + "'");
253 }
254 } else {
255 report_fatal_error("unsupported relocation of undefined symbol '" +
256 Symbol->getName() + "'");
257 }
258
259 MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
260 if (IsPCRel) {
261 if (IsRIPRel) {
262 if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
263 // x86_64 distinguishes movq foo@GOTPCREL so that the linker can
264 // rewrite the movq to an leaq at link time if the symbol ends up in
265 // the same linkage unit.
266 if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
267 Type = macho::RIT_X86_64_GOTLoad;
268 else
269 Type = macho::RIT_X86_64_GOT;
270 } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
271 Type = macho::RIT_X86_64_TLV;
272 } else if (Modifier != MCSymbolRefExpr::VK_None) {
273 report_fatal_error("unsupported symbol modifier in relocation");
274 } else {
275 Type = macho::RIT_X86_64_Signed;
276
277 // The Darwin x86_64 relocation format has a problem where it cannot
278 // encode an address (L + ) which is outside the atom
279 // containing L. Generally, this shouldn't occur but it does
280 // happen when we have a RIPrel instruction with data following the
281 // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel
282 // adjustment Darwin x86_64 uses, the offset is still negative and the
283 // linker has no way to recognize this.
284 //
285 // To work around this, Darwin uses several special relocation types
286 // to indicate the offsets. However, the specification or
287 // implementation of these seems to also be incomplete; they should
288 // adjust the addend as well based on the actual encoded instruction
289 // (the additional bias), but instead appear to just look at the final
290 // offset.
291 switch (-(Target.getConstant() + (1LL << Log2Size))) {
292 case 1: Type = macho::RIT_X86_64_Signed1; break;
293 case 2: Type = macho::RIT_X86_64_Signed2; break;
294 case 4: Type = macho::RIT_X86_64_Signed4; break;
295 }
296 }
297 } else {
298 if (Modifier != MCSymbolRefExpr::VK_None)
299 report_fatal_error("unsupported symbol modifier in branch "
300 "relocation");
301
302 Type = macho::RIT_X86_64_Branch;
303 }
304 } else {
305 if (Modifier == MCSymbolRefExpr::VK_GOT) {
306 Type = macho::RIT_X86_64_GOT;
307 } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
308 // GOTPCREL is allowed as a modifier on non-PCrel instructions, in which
309 // case all we do is set the PCrel bit in the relocation entry; this is
310 // used with exception handling, for example. The source is required to
311 // include any necessary offset directly.
312 Type = macho::RIT_X86_64_GOT;
313 IsPCRel = 1;
314 } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
315 report_fatal_error("TLVP symbol modifier should have been rip-rel");
316 } else if (Modifier != MCSymbolRefExpr::VK_None)
317 report_fatal_error("unsupported symbol modifier in relocation");
318 else
319 Type = macho::RIT_X86_64_Unsigned;
320 }
321 }
322
323 // x86_64 always writes custom values into the fixups.
324 FixedValue = Value;
325
326 // struct relocation_info (8 bytes)
327 macho::RelocationEntry MRE;
328 MRE.Word0 = FixupOffset;
329 MRE.Word1 = ((Index << 0) |
330 (IsPCRel << 24) |
331 (Log2Size << 25) |
332 (IsExtern << 27) |
333 (Type << 28));
334 Writer->addRelocation(Fragment->getParent(), MRE);
335 }
336
337 void X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
338 const MCAssembler &Asm,
339 const MCAsmLayout &Layout,
340 const MCFragment *Fragment,
341 const MCFixup &Fixup,
342 MCValue Target,
343 unsigned Log2Size,
344 uint64_t &FixedValue) {
345 uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
346 unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
347 unsigned Type = macho::RIT_Vanilla;
348
349 // See .
350 const MCSymbol *A = &Target.getSymA()->getSymbol();
351 MCSymbolData *A_SD = &Asm.getSymbolData(*A);
352
353 if (!A_SD->getFragment())
354 report_fatal_error("symbol '" + A->getName() +
355 "' can not be undefined in a subtraction expression");
356
357 uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
358 uint64_t SecAddr = Writer->getSectionAddress(A_SD->getFragment()->getParent());
359 FixedValue += SecAddr;
360 uint32_t Value2 = 0;
361
362 if (const MCSymbolRefExpr *B = Target.getSymB()) {
363 MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
364
365 if (!B_SD->getFragment())
366 report_fatal_error("symbol '" + B->getSymbol().getName() +
367 "' can not be undefined in a subtraction expression");
368
369 // Select the appropriate difference relocation type.
370 //
371 // Note that there is no longer any semantic difference between these two
372 // relocation types from the linkers point of view, this is done solely for
373 // pedantic compatibility with 'as'.
374 Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference :
375 (unsigned)macho::RIT_Generic_LocalDifference;
376 Value2 = Writer->getSymbolAddress(B_SD, Layout);
377 FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
378 }
379
380 // Relocations are written out in reverse order, so the PAIR comes first.
381 if (Type == macho::RIT_Difference ||
382 Type == macho::RIT_Generic_LocalDifference) {
383 macho::RelocationEntry MRE;
384 MRE.Word0 = ((0 << 0) |
385 (macho::RIT_Pair << 24) |
386 (Log2Size << 28) |
387 (IsPCRel << 30) |
388 macho::RF_Scattered);
389 MRE.Word1 = Value2;
390 Writer->addRelocation(Fragment->getParent(), MRE);
391 }
392
393 macho::RelocationEntry MRE;
394 MRE.Word0 = ((FixupOffset << 0) |
395 (Type << 24) |
396 (Log2Size << 28) |
397 (IsPCRel << 30) |
398 macho::RF_Scattered);
399 MRE.Word1 = Value;
400 Writer->addRelocation(Fragment->getParent(), MRE);
401 }
402
403 void X86MachObjectWriter::RecordTLVPRelocation(MachObjectWriter *Writer,
404 const MCAssembler &Asm,
405 const MCAsmLayout &Layout,
406 const MCFragment *Fragment,
407 const MCFixup &Fixup,
408 MCValue Target,
409 uint64_t &FixedValue) {
410 assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
411 !is64Bit() &&
412 "Should only be called with a 32-bit TLVP relocation!");
413
414 unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
415 uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
416 unsigned IsPCRel = 0;
417
418 // Get the symbol data.
419 MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol());
420 unsigned Index = SD_A->getIndex();
421
422 // We're only going to have a second symbol in pic mode and it'll be a
423 // subtraction from the picbase. For 32-bit pic the addend is the difference
424 // between the picbase and the next address. For 32-bit static the addend is
425 // zero.
426 if (Target.getSymB()) {
427 // If this is a subtraction then we're pcrel.
428 uint32_t FixupAddress =
429 Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
430 MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol());
431 IsPCRel = 1;
432 FixedValue = (FixupAddress - Writer->getSymbolAddress(SD_B, Layout) +
433 Target.getConstant());
434 FixedValue += 1ULL << Log2Size;
435 } else {
436 FixedValue = 0;
437 }
438
439 // struct relocation_info (8 bytes)
440 macho::RelocationEntry MRE;
441 MRE.Word0 = Value;
442 MRE.Word1 = ((Index << 0) |
443 (IsPCRel << 24) |
444 (Log2Size << 25) |
445 (1 << 27) | // Extern
446 (macho::RIT_Generic_TLV << 28)); // Type
447 Writer->addRelocation(Fragment->getParent(), MRE);
448 }
449
450 void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer,
451 const MCAssembler &Asm,
452 const MCAsmLayout &Layout,
453 const MCFragment *Fragment,
454 const MCFixup &Fixup,
455 MCValue Target,
456 uint64_t &FixedValue) {
457 unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
458 unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
459
460 // If this is a 32-bit TLVP reloc it's handled a bit differently.
461 if (Target.getSymA() &&
462 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) {
463 RecordTLVPRelocation(Writer, Asm, Layout, Fragment, Fixup, Target,
464 FixedValue);
465 return;
466 }
467
468 // If this is a difference or a defined symbol plus an offset, then we need a
469 // scattered relocation entry. Differences always require scattered
470 // relocations.
471 if (Target.getSymB())
472 return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
473 Target, Log2Size, FixedValue);
474
475 // Get the symbol data, if any.
476 MCSymbolData *SD = 0;
477 if (Target.getSymA())
478 SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
479
480 // If this is an internal relocation with an offset, it also needs a scattered
481 // relocation entry.
482 uint32_t Offset = Target.getConstant();
483 if (IsPCRel)
484 Offset += 1 << Log2Size;
485 if (Offset && SD && !Writer->doesSymbolRequireExternRelocation(SD))
486 return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
487 Target, Log2Size, FixedValue);
488
489 // See .
490 uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
491 unsigned Index = 0;
492 unsigned IsExtern = 0;
493 unsigned Type = 0;
494
495 if (Target.isAbsolute()) { // constant
496 // SymbolNum of 0 indicates the absolute section.
497 //
498 // FIXME: Currently, these are never generated (see code below). I cannot
499 // find a case where they are actually emitted.
500 Type = macho::RIT_Vanilla;
501 } else {
502 // Resolve constant variables.
503 if (SD->getSymbol().isVariable()) {
504 int64_t Res;
505 if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
506 Res, Layout, Writer->getSectionAddressMap())) {
507 FixedValue = Res;
508 return;
509 }
510 }
511
512 // Check whether we need an external or internal relocation.
513 if (Writer->doesSymbolRequireExternRelocation(SD)) {
514 IsExtern = 1;
515 Index = SD->getIndex();
516 // For external relocations, make sure to offset the fixup value to
517 // compensate for the addend of the symbol address, if it was
518 // undefined. This occurs with weak definitions, for example.
519 if (!SD->Symbol->isUndefined())
520 FixedValue -= Layout.getSymbolOffset(SD);
521 } else {
522 // The index is the section ordinal (1-based).
523 const MCSectionData &SymSD = Asm.getSectionData(
524 SD->getSymbol().getSection());
525 Index = SymSD.getOrdinal() + 1;
526 FixedValue += Writer->getSectionAddress(&SymSD);
527 }
528 if (IsPCRel)
529 FixedValue -= Writer->getSectionAddress(Fragment->getParent());
530
531 Type = macho::RIT_Vanilla;
532 }
533
534 // struct relocation_info (8 bytes)
535 macho::RelocationEntry MRE;
536 MRE.Word0 = FixupOffset;
537 MRE.Word1 = ((Index << 0) |
538 (IsPCRel << 24) |
539 (Log2Size << 25) |
540 (IsExtern << 27) |
541 (Type << 28));
542 Writer->addRelocation(Fragment->getParent(), MRE);
543 }
544
545 MCObjectWriter *llvm::createX86MachObjectWriter(raw_ostream &OS,
546 bool Is64Bit,
547 uint32_t CPUType,
548 uint32_t CPUSubtype) {
549 return createMachObjectWriter(new X86MachObjectWriter(Is64Bit,
550 CPUType,
551 CPUSubtype),
552 OS, /*IsLittleEndian=*/true);
553 }
6060 FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
6161 JITCodeEmitter &JCE);
6262
63 TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &);
64 TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &);
65
6663 /// createX86EmitCodeToMemory - Returns a pass that converts a register
6764 /// allocated function into raw machine code in a dynamically
6865 /// allocated chunk of memory.
7572 ///
7673 FunctionPass *createX86MaxStackAlignmentHeuristicPass();
7774
78
79 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
80 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
81 bool Is64Bit,
82 uint32_t CPUType,
83 uint32_t CPUSubtype);
84
8575 } // End llvm namespace
8676
8777 #endif
+0
-452
lib/Target/X86/X86AsmBackend.cpp less more
None //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/MC/TargetAsmBackend.h"
10 #include "X86.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionCOFF.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Object/MachOFormat.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegistry.h"
28 using namespace llvm;
29
30 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
31 // is useful when running bitwise comparison experiments on Darwin. We should be
32 // able to remove this once PR9807 is resolved.
33 static cl::opt
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
36
37 static unsigned getFixupKindLog2Size(unsigned Kind) {
38 switch (Kind) {
39 default: assert(0 && "invalid fixup kind!");
40 case FK_PCRel_1:
41 case FK_Data_1: return 0;
42 case FK_PCRel_2:
43 case FK_Data_2: return 1;
44 case FK_PCRel_4:
45 case X86::reloc_riprel_4byte:
46 case X86::reloc_riprel_4byte_movq_load:
47 case X86::reloc_signed_4byte:
48 case X86::reloc_global_offset_table:
49 case FK_Data_4: return 2;
50 case FK_PCRel_8:
51 case FK_Data_8: return 3;
52 }
53 }
54
55 namespace {
56
57 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
58 public:
59 X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
60 bool HasRelocationAddend)
61 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
62 };
63
64 class X86AsmBackend : public TargetAsmBackend {
65 public:
66 X86AsmBackend(const Target &T)
67 : TargetAsmBackend() {}
68
69 unsigned getNumFixupKinds() const {
70 return X86::NumTargetFixupKinds;
71 }
72
73 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
74 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
75 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
76 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
77 { "reloc_signed_4byte", 0, 4 * 8, 0},
78 { "reloc_global_offset_table", 0, 4 * 8, 0}
79 };
80
81 if (Kind < FirstTargetFixupKind)
82 return TargetAsmBackend::getFixupKindInfo(Kind);
83
84 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
85 "Invalid kind!");
86 return Infos[Kind - FirstTargetFixupKind];
87 }
88
89 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
90 uint64_t Value) const {
91 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
92
93 assert(Fixup.getOffset() + Size <= DataSize &&
94 "Invalid fixup offset!");
95 for (unsigned i = 0; i != Size; ++i)
96 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
97 }
98
99 bool MayNeedRelaxation(const MCInst &Inst) const;
100
101 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
102
103 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
104 };
105 } // end anonymous namespace
106
107 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
108 switch (Op) {
109 default:
110 return Op;
111
112 case X86::JAE_1: return X86::JAE_4;
113 case X86::JA_1: return X86::JA_4;
114 case X86::JBE_1: return X86::JBE_4;
115 case X86::JB_1: return X86::JB_4;
116 case X86::JE_1: return X86::JE_4;
117 case X86::JGE_1: return X86::JGE_4;
118 case X86::JG_1: return X86::JG_4;
119 case X86::JLE_1: return X86::JLE_4;
120 case X86::JL_1: return X86::JL_4;
121 case X86::JMP_1: return X86::JMP_4;
122 case X86::JNE_1: return X86::JNE_4;
123 case X86::JNO_1: return X86::JNO_4;
124 case X86::JNP_1: return X86::JNP_4;
125 case X86::JNS_1: return X86::JNS_4;
126 case X86::JO_1: return X86::JO_4;
127 case X86::JP_1: return X86::JP_4;
128 case X86::JS_1: return X86::JS_4;
129 }
130 }
131
132 static unsigned getRelaxedOpcodeArith(unsigned Op) {
133 switch (Op) {
134 default:
135 return Op;
136
137 // IMUL
138 case X86::IMUL16rri8: return X86::IMUL16rri;
139 case X86::IMUL16rmi8: return X86::IMUL16rmi;
140 case X86::IMUL32rri8: return X86::IMUL32rri;
141 case X86::IMUL32rmi8: return X86::IMUL32rmi;
142 case X86::IMUL64rri8: return X86::IMUL64rri32;
143 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
144
145 // AND
146 case X86::AND16ri8: return X86::AND16ri;
147 case X86::AND16mi8: return X86::AND16mi;
148 case X86::AND32ri8: return X86::AND32ri;
149 case X86::AND32mi8: return X86::AND32mi;
150 case X86::AND64ri8: return X86::AND64ri32;
151 case X86::AND64mi8: return X86::AND64mi32;
152
153 // OR
154 case X86::OR16ri8: return X86::OR16ri;
155 case X86::OR16mi8: return X86::OR16mi;
156 case X86::OR32ri8: return X86::OR32ri;
157 case X86::OR32mi8: return X86::OR32mi;
158 case X86::OR64ri8: return X86::OR64ri32;
159 case X86::OR64mi8: return X86::OR64mi32;
160
161 // XOR
162 case X86::XOR16ri8: return X86::XOR16ri;
163 case X86::XOR16mi8: return X86::XOR16mi;
164 case X86::XOR32ri8: return X86::XOR32ri;
165 case X86::XOR32mi8: return X86::XOR32mi;
166 case X86::XOR64ri8: return X86::XOR64ri32;
167 case X86::XOR64mi8: return X86::XOR64mi32;
168
169 // ADD
170 case X86::ADD16ri8: return X86::ADD16ri;
171 case X86::ADD16mi8: return X86::ADD16mi;
172 case X86::ADD32ri8: return X86::ADD32ri;
173 case X86::ADD32mi8: return X86::ADD32mi;
174 case X86::ADD64ri8: return X86::ADD64ri32;
175 case X86::ADD64mi8: return X86::ADD64mi32;
176
177 // SUB
178 case X86::SUB16ri8: return X86::SUB16ri;
179 case X86::SUB16mi8: return X86::SUB16mi;
180 case X86::SUB32ri8: return X86::SUB32ri;
181 case X86::SUB32mi8: return X86::SUB32mi;
182 case X86::SUB64ri8: return X86::SUB64ri32;
183 case X86::SUB64mi8: return X86::SUB64mi32;
184
185 // CMP
186 case X86::CMP16ri8: return X86::CMP16ri;
187 case X86::CMP16mi8: return X86::CMP16mi;
188 case X86::CMP32ri8: return X86::CMP32ri;
189 case X86::CMP32mi8: return X86::CMP32mi;
190 case X86::CMP64ri8: return X86::CMP64ri32;
191 case X86::CMP64mi8: return X86::CMP64mi32;
192
193 // PUSH
194 case X86::PUSHi8: return X86::PUSHi32;
195 case X86::PUSHi16: return X86::PUSHi32;
196 case X86::PUSH64i8: return X86::PUSH64i32;
197 case X86::PUSH64i16: return X86::PUSH64i32;
198 }
199 }
200
201 static unsigned getRelaxedOpcode(unsigned Op) {
202 unsigned R = getRelaxedOpcodeArith(Op);
203 if (R != Op)
204 return R;
205 return getRelaxedOpcodeBranch(Op);
206 }
207
208 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
209 // Branches can always be relaxed.
210 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
211 return true;
212
213 if (MCDisableArithRelaxation)
214 return false;
215
216 // Check if this instruction is ever relaxable.
217 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
218 return false;
219
220
221 // Check if it has an expression and is not RIP relative.
222 bool hasExp = false;
223 bool hasRIP = false;
224 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
225 const MCOperand &Op = Inst.getOperand(i);
226 if (Op.isExpr())
227 hasExp = true;
228
229 if (Op.isReg() && Op.getReg() == X86::RIP)
230 hasRIP = true;
231 }
232
233 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
234 // how we do relaxations?
235 return hasExp && !hasRIP;
236 }
237
238 // FIXME: Can tblgen help at all here to verify there aren't other instructions
239 // we can relax?
240 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
241 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
242 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
243
244 if (RelaxedOp == Inst.getOpcode()) {
245 SmallString<256> Tmp;
246 raw_svector_ostream OS(Tmp);
247 Inst.dump_pretty(OS);
248 OS << "\n";
249 report_fatal_error("unexpected instruction to relax: " + OS.str());
250 }
251
252 Res = Inst;
253 Res.setOpcode(RelaxedOp);
254 }
255
256 /// WriteNopData - Write optimal nops to the output file for the \arg Count
257 /// bytes. This returns the number of bytes written. It may return 0 if
258 /// the \arg Count is more than the maximum optimal nops.
259 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
260 static const uint8_t Nops[10][10] = {
261 // nop
262 {0x90},
263 // xchg %ax,%ax
264 {0x66, 0x90},
265 // nopl (%[re]ax)
266 {0x0f, 0x1f, 0x00},
267 // nopl 0(%[re]ax)
268 {0x0f, 0x1f, 0x40, 0x00},
269 // nopl 0(%[re]ax,%[re]ax,1)
270 {0x0f, 0x1f, 0x44, 0x00, 0x00},
271 // nopw 0(%[re]ax,%[re]ax,1)
272 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
273 // nopl 0L(%[re]ax)
274 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
275 // nopl 0L(%[re]ax,%[re]ax,1)
276 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
277 // nopw 0L(%[re]ax,%[re]ax,1)
278 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
279 // nopw %cs:0L(%[re]ax,%[re]ax,1)
280 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
281 };
282
283 // Write an optimal sequence for the first 15 bytes.
284 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
285 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
286 for (uint64_t i = 0, e = Prefixes; i != e; i++)
287 OW->Write8(0x66);
288 const uint64_t Rest = OptimalCount - Prefixes;
289 for (uint64_t i = 0, e = Rest; i != e; i++)
290 OW->Write8(Nops[Rest - 1][i]);
291
292 // Finish with single byte nops.
293 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
294 OW->Write8(0x90);
295
296 return true;
297 }
298
299 /* *** */
300
301 namespace {
302 class ELFX86AsmBackend : public X86AsmBackend {
303 public:
304 Triple::OSType OSType;
305 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
306 : X86AsmBackend(T), OSType(_OSType) {
307 HasReliableSymbolDifference = true;
308 }
309
310 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
311 const MCSectionELF &ES = static_cast(Section);
312 return ES.getFlags() & ELF::SHF_MERGE;
313 }
314 };
315
316 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
317 public:
318 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
319 : ELFX86AsmBackend(T, OSType) {}
320
321 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
322 return createELFObjectWriter(createELFObjectTargetWriter(),
323 OS, /*IsLittleEndian*/ true);
324 }
325
326 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
327 return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
328 }
329 };
330
331 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
332 public:
333 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
334 : ELFX86AsmBackend(T, OSType) {}
335
336 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
337 return createELFObjectWriter(createELFObjectTargetWriter(),
338 OS, /*IsLittleEndian*/ true);
339 }
340
341 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
342 return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
343 }
344 };
345
346 class WindowsX86AsmBackend : public X86AsmBackend {
347 bool Is64Bit;
348
349 public:
350 WindowsX86AsmBackend(const Target &T, bool is64Bit)
351 : X86AsmBackend(T)
352 , Is64Bit(is64Bit) {
353 }
354
355 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
356 return createWinCOFFObjectWriter(OS, Is64Bit);
357 }
358 };
359
360 class DarwinX86AsmBackend : public X86AsmBackend {
361 public:
362 DarwinX86AsmBackend(const Target &T)
363 : X86AsmBackend(T) { }
364 };
365
366 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
367 public:
368 DarwinX86_32AsmBackend(const Target &T)
369 : DarwinX86AsmBackend(T) {}
370
371 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
372 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
373 object::mach::CTM_i386,
374 object::mach::CSX86_ALL);
375 }
376 };
377
378 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
379 public:
380 DarwinX86_64AsmBackend(const Target &T)
381 : DarwinX86AsmBackend(T) {
382 HasReliableSymbolDifference = true;
383 }
384
385 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
386 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
387 object::mach::CTM_x86_64,
388 object::mach::CSX86_ALL);
389 }
390
391 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
392 // Temporary labels in the string literals sections require symbols. The
393 // issue is that the x86_64 relocation format does not allow symbol +
394 // offset, and so the linker does not have enough information to resolve the
395 // access to the appropriate atom unless an external relocation is used. For
396 // non-cstring sections, we expect the compiler to use a non-temporary label
397 // for anything that could have an addend pointing outside the symbol.
398 //
399 // See .
400 const MCSectionMachO &SMO = static_cast(Section);
401 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
402 }
403
404 virtual bool isSectionAtomizable(const MCSection &Section) const {
405 const MCSectionMachO &SMO = static_cast(Section);
406 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
407 switch (SMO.getType()) {
408 default:
409 return true;
410
411 case MCSectionMachO::S_4BYTE_LITERALS:
412 case MCSectionMachO::S_8BYTE_LITERALS:
413 case MCSectionMachO::S_16BYTE_LITERALS:
414 case MCSectionMachO::S_LITERAL_POINTERS:
415 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
416 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
417 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
418 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
419 case MCSectionMachO::S_INTERPOSING:
420 return false;
421 }
422 }
423 };
424
425 } // end anonymous namespace
426
427 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
428 const std::string &TT) {
429 Triple TheTriple(TT);
430
431 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
432 return new DarwinX86_32AsmBackend(T);
433
434 if (TheTriple.isOSWindows())
435 return new WindowsX86AsmBackend(T, false);
436
437 return new ELFX86_32AsmBackend(T, TheTriple.getOS());
438 }
439
440 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
441 const std::string &TT) {
442 Triple TheTriple(TT);
443
444 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
445 return new DarwinX86_64AsmBackend(T);
446
447 if (TheTriple.isOSWindows())
448 return new WindowsX86AsmBackend(T, true);
449
450 return new ELFX86_64AsmBackend(T, TheTriple.getOS());
451 }
+0
-1055
lib/Target/X86/X86MCCodeEmitter.cpp less more
None //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86MCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "mccodeemitter"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86FixupKinds.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/raw_ostream.h"
25
26 using namespace llvm;
27
28 namespace {
29 class X86MCCodeEmitter : public MCCodeEmitter {
30 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
31 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
32 const MCInstrInfo &MCII;
33 const MCSubtargetInfo &STI;
34 MCContext &Ctx;
35 public:
36 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
37 MCContext &ctx)
38 : MCII(mcii), STI(sti), Ctx(ctx) {
39 }
40
41 ~X86MCCodeEmitter() {}
42
43 bool is64BitMode() const {
44 // FIXME: Can tablegen auto-generate this?
45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
46 }
47
48 static unsigned GetX86RegNum(const MCOperand &MO) {
49 return X86_MC::getX86RegNum(MO.getReg());
50 }
51
52 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
53 // 0-7 and the difference between the 2 groups is given by the REX prefix.
54 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
55 // in 1's complement form, example:
56 //
57 // ModRM field => XMM9 => 1
58 // VEX.VVVV => XMM9 => ~9
59 //
60 // See table 4-35 of Intel AVX Programming Reference for details.
61 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
62 unsigned OpNum) {
63 unsigned SrcReg = MI.getOperand(OpNum).getReg();
64 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
65 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
66 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
67 SrcRegNum += 8;
68
69 // The registers represented through VEX_VVVV should
70 // be encoded in 1's complement form.
71 return (~SrcRegNum) & 0xf;
72 }
73
74 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
75 OS << (char)C;
76 ++CurByte;
77 }
78
79 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
80 raw_ostream &OS) const {
81 // Output the constant in little endian byte order.
82 for (unsigned i = 0; i != Size; ++i) {
83 EmitByte(Val & 255, CurByte, OS);
84 Val >>= 8;
85 }
86 }
87
88 void EmitImmediate(const MCOperand &Disp,
89 unsigned ImmSize, MCFixupKind FixupKind,
90 unsigned &CurByte, raw_ostream &OS,
91 SmallVectorImpl &Fixups,
92 int ImmOffset = 0) const;
93
94 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
95 unsigned RM) {
96 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
97 return RM | (RegOpcode << 3) | (Mod << 6);
98 }
99
100 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
101 unsigned &CurByte, raw_ostream &OS) const {
102 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
103 }
104
105 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
106 unsigned &CurByte, raw_ostream &OS) const {
107 // SIB byte is in the same format as the ModRMByte.
108 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
109 }
110
111
112 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
113 unsigned RegOpcodeField,
114 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
115 SmallVectorImpl &Fixups) const;
116
117 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
118 SmallVectorImpl &Fixups) const;
119
120 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
121 const MCInst &MI, const MCInstrDesc &Desc,
122 raw_ostream &OS) const;
123
124 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
125 int MemOperand, const MCInst &MI,
126 raw_ostream &OS) const;
127
128 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
129 const MCInst &MI, const MCInstrDesc &Desc,
130 raw_ostream &OS) const;
131 };
132
133 } // end anonymous namespace
134
135
136 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
137 const MCSubtargetInfo &STI,
138 MCContext &Ctx) {
139 return new X86MCCodeEmitter(MCII, STI, Ctx);
140 }
141
142 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
143 /// sign-extended field.
144 static bool isDisp8(int Value) {
145 return Value == (signed char)Value;
146 }
147
148 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
149 /// in an instruction with the specified TSFlags.
150 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
151 unsigned Size = X86II::getSizeOfImm(TSFlags);
152 bool isPCRel = X86II::isImmPCRel(TSFlags);
153
154 return MCFixup::getKindForSize(Size, isPCRel);
155 }
156
157 namespace llvm {
158 // FIXME: TableGen this?
159 extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc.
160 }
161
162 /// Is32BitMemOperand - Return true if the specified instruction with a memory
163 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
164 /// memory operand. Op specifies the operand # of the memoperand.
165 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
167 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
168
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
171 (IndexReg.getReg() != 0 &&
172 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
173 return true;
174 return false;
175 }
176
177 /// StartsWithGlobalOffsetTable - Return true for the simple cases where this
178 /// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
179 /// PIC on ELF i386 as that symbol is magic. We check only simple case that
180 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
181 /// of a binary expression.
182 static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
183 if (Expr->getKind() == MCExpr::Binary) {
184 const MCBinaryExpr *BE = static_cast(Expr);
185 Expr = BE->getLHS();
186 }
187
188 if (Expr->getKind() != MCExpr::SymbolRef)
189 return false;
190
191 const MCSymbolRefExpr *Ref = static_cast(Expr);
192 const MCSymbol &S = Ref->getSymbol();
193 return S.getName() == "_GLOBAL_OFFSET_TABLE_";
194 }
195
196 void X86MCCodeEmitter::
197 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
198 unsigned &CurByte, raw_ostream &OS,
199 SmallVectorImpl &Fixups, int ImmOffset) const {
200 const MCExpr *Expr = NULL;
201 if (DispOp.isImm()) {
202 // If this is a simple integer displacement that doesn't require a relocation,
203 // emit it now.
204 if (FixupKind != FK_PCRel_1 &&
205 FixupKind != FK_PCRel_2 &&
206 FixupKind != FK_PCRel_4) {
207 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
208 return;
209 }
210 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
211 } else {
212 Expr = DispOp.getExpr();
213 }
214
215 // If we have an immoffset, add it to the expression.
216 if ((FixupKind == FK_Data_4 ||
217 FixupKind == MCFixupKind(X86::reloc_signed_4byte)) &&
218 StartsWithGlobalOffsetTable(Expr)) {
219 assert(ImmOffset == 0);
220
221 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
222 ImmOffset = CurByte;
223 }
224
225 // If the fixup is pc-relative, we need to bias the value to be relative to
226 // the start of the field, not the end of the field.
227 if (FixupKind == FK_PCRel_4 ||
228 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
229 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
230 ImmOffset -= 4;
231 if (FixupKind == FK_PCRel_2)
232 ImmOffset -= 2;
233 if (FixupKind == FK_PCRel_1)
234 ImmOffset -= 1;
235
236 if (ImmOffset)
237 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
238 Ctx);
239
240 // Emit a symbolic constant as a fixup and 4 zeros.
241 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
242 EmitConstant(0, Size, CurByte, OS);
243 }
244
245 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
246 unsigned RegOpcodeField,
247 uint64_t TSFlags, unsigned &CurByte,
248 raw_ostream &OS,
249 SmallVectorImpl &Fixups) const{
250 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
251 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
252 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
253 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
254 unsigned BaseReg = Base.getReg();
255
256 // Handle %rip relative addressing.
257 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
258 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
259 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
260 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
261
262 unsigned FixupKind = X86::reloc_riprel_4byte;
263
264 // movq loads are handled with a special relocation form which allows the
265 // linker to eliminate some loads for GOT references which end up in the
266 // same linkage unit.
267 if (MI.getOpcode() == X86::MOV64rm)
268 FixupKind = X86::reloc_riprel_4byte_movq_load;
269
270 // rip-relative addressing is actually relative to the *next* instruction.
271 // Since an immediate can follow the mod/rm byte for an instruction, this
272 // means that we need to bias the immediate field of the instruction with
273 // the size of the immediate field. If we have this case, add it into the
274 // expression to emit.
275 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
276
277 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
278 CurByte, OS, Fixups, -ImmSize);
279 return;
280 }
281
282 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
283
284 // Determine whether a SIB byte is needed.
285 // If no BaseReg, issue a RIP relative instruction only if the MCE can
286 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
287 // 2-7) and absolute references.
288
289 if (// The SIB byte must be used if there is an index register.
290 IndexReg.getReg() == 0 &&
291 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
292 // encode to an R/M value of 4, which indicates that a SIB byte is
293 // present.
294 BaseRegNo != N86::ESP &&
295 // If there is no base register and we're in 64-bit mode, we need a SIB
296 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
297 (!is64BitMode() || BaseReg != 0)) {
298
299 if (BaseReg == 0) { // [disp32] in X86-32 mode
300 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
301 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
302 return;
303 }
304
305 // If the base is not EBP/ESP and there is no displacement, use simple
306 // indirect register encoding, this handles addresses like [EAX]. The
307 // encoding for [EBP] with no displacement means [disp32] so we handle it
308 // by emitting a displacement of 0 below.
309 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
310 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
311 return;
312 }
313
314 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
315 if (Disp.isImm() && isDisp8(Disp.getImm())) {
316 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
317 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
318 return;
319 }
320
321 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
322 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
323 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
324 Fixups);
325 return;
326 }
327
328 // We need a SIB byte, so start by outputting the ModR/M byte first
329 assert(IndexReg.getReg() != X86::ESP &&
330 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
331
332 bool ForceDisp32 = false;
333 bool ForceDisp8 = false;
334 if (BaseReg == 0) {
335 // If there is no base register, we emit the special case SIB byte with
336 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
337 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
338 ForceDisp32 = true;
339 } else if (!Disp.isImm()) {
340 // Emit the normal disp32 encoding.
341 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
342 ForceDisp32 = true;
343 } else if (Disp.getImm() == 0 &&
344 // Base reg can't be anything that ends up with '5' as the base
345 // reg, it is the magic [*] nomenclature that indicates no base.
346 BaseRegNo != N86::EBP) {
347 // Emit no displacement ModR/M byte
348 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
349 } else if (isDisp8(Disp.getImm())) {
350 // Emit the disp8 encoding.
351 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
352 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
353 } else {
354 // Emit the normal disp32 encoding.
355 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
356 }
357
358 // Calculate what the SS field value should be...
359 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
360 unsigned SS = SSTable[Scale.getImm()];
361
362 if (BaseReg == 0) {
363 // Handle the SIB byte for the case where there is no base, see Intel
364 // Manual 2A, table 2-7. The displacement has already been output.
365 unsigned IndexRegNo;
366 if (IndexReg.getReg())
367 IndexRegNo = GetX86RegNum(IndexReg);
368 else // Examples: [ESP+1*+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
369 IndexRegNo = 4;
370 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
371 } else {
372 unsigned IndexRegNo;
373 if (IndexReg.getReg())
374 IndexRegNo = GetX86RegNum(IndexReg);
375 else
376 IndexRegNo = 4; // For example [ESP+1*+4]
377 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
378 }
379
380 // Do we need to output a displacement?
381 if (ForceDisp8)
382 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
383 else if (ForceDisp32 || Disp.getImm() != 0)
384 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
385 Fixups);
386 }
387
388 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
389 /// called VEX.
390 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
391 int MemOperand, const MCInst &MI,
392 const MCInstrDesc &Desc,
393 raw_ostream &OS) const {
394 bool HasVEX_4V = false;
395 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
396 HasVEX_4V = true;
397
398 // VEX_R: opcode externsion equivalent to REX.R in
399 // 1's complement (inverted) form
400 //
401 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
402 // 0: Same as REX_R=1 (64 bit mode only)
403 //
404 unsigned char VEX_R = 0x1;
405
406 // VEX_X: equivalent to REX.X, only used when a
407 // register is used for index in SIB Byte.
408 //
409 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
410 // 0: Same as REX.X=1 (64-bit mode only)
411 unsigned char VEX_X = 0x1;
412
413 // VEX_B:
414 //
415 // 1: Same as REX_B=0 (ignored in 32-bit mode)
416 // 0: Same as REX_B=1 (64 bit mode only)
417 //
418 unsigned char VEX_B = 0x1;
419
420 // VEX_W: opcode specific (use like REX.W, or used for
421 // opcode extension, or ignored, depending on the opcode byte)
422 unsigned char VEX_W = 0;
423
424 // VEX_5M (VEX m-mmmmm field):
425 //
426 // 0b00000: Reserved for future use
427 // 0b00001: implied 0F leading opcode
428 // 0b00010: implied 0F 38 leading opcode bytes
429 // 0b00011: implied 0F 3A leading opcode bytes
430 // 0b00100-0b11111: Reserved for future use
431 //
432 unsigned char VEX_5M = 0x1;
433
434 // VEX_4V (VEX vvvv field): a register specifier
435 // (in 1's complement form) or 1111 if unused.
436 unsigned char VEX_4V = 0xf;
437
438 // VEX_L (Vector Length):
439 //
440 // 0: scalar or 128-bit vector
441 // 1: 256-bit vector
442 //
443 unsigned char VEX_L = 0;
444
445 // VEX_PP: opcode extension providing equivalent
446 // functionality of a SIMD prefix
447 //
448 // 0b00: None
449 // 0b01: 66
450 // 0b10: F3
451 // 0b11: F2
452 //
453 unsigned char VEX_PP = 0;
454
455 // Encode the operand size opcode prefix as needed.
456 if (TSFlags & X86II::OpSize)
457 VEX_PP = 0x01;
458
459 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
460 VEX_W = 1;
461
462 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
463 VEX_L = 1;
464
465 switch (TSFlags & X86II::Op0Mask) {
466 default: assert(0 && "Invalid prefix!");
467 case X86II::T8: // 0F 38
468 VEX_5M = 0x2;
469 break;
470 case X86II::TA: // 0F 3A
471 VEX_5M = 0x3;
472 break;
473 case X86II::TF: // F2 0F 38
474 VEX_PP = 0x3;
475 VEX_5M = 0x2;
476 break;
477 case X86II::XS: // F3 0F
478 VEX_PP = 0x2;
479 break;
480 case X86II::XD: // F2 0F
481 VEX_PP = 0x3;
482 break;
483 case X86II::A6: // Bypass: Not used by VEX
484 case X86II::A7: // Bypass: Not used by VEX
485 case X86II::TB: // Bypass: Not used by VEX
486 case 0:
487 break; // No prefix!
488 }
489
490 // Set the vector length to 256-bit if YMM0-YMM15 is used
491 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
492 if (!MI.getOperand(i).isReg())
493 continue;
494 unsigned SrcReg = MI.getOperand(i).getReg();
495 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
496 VEX_L = 1;
497 }
498
499 unsigned NumOps = MI.getNumOperands();
500 unsigned CurOp = 0;
501 bool IsDestMem = false;
502
503 switch (TSFlags & X86II::FormMask) {
504 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
505 case X86II::MRMDestMem:
506 IsDestMem = true;
507 // The important info for the VEX prefix is never beyond the address
508 // registers. Don't check beyond that.
509 NumOps = CurOp = X86::AddrNumOperands;
510 case X86II::MRM0m: case X86II::MRM1m:
511 case X86II::MRM2m: case X86II::MRM3m:
512 case X86II::MRM4m: case X86II::MRM5m:
513 case X86II::MRM6m: case X86II::MRM7m:
514 case X86II::MRMSrcMem:
515 case X86II::MRMSrcReg:
516 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
517 X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
518 VEX_R = 0x0;
519 CurOp++;
520
521 if (HasVEX_4V) {
522 VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
523 CurOp++;
524 }
525
526 // To only check operands before the memory address ones, start
527 // the search from the beginning
528 if (IsDestMem)
529 CurOp = 0;
530
531 // If the last register should be encoded in the immediate field
532 // do not use any bit from VEX prefix to this register, ignore it
533 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
534 NumOps--;
535
536 for (; CurOp != NumOps; ++CurOp) {
537 const MCOperand &MO = MI.getOperand(CurOp);
538 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
539 VEX_B = 0x0;
540 if (!VEX_B && MO.isReg() &&
541 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
542 X86II::isX86_64ExtendedReg(MO.getReg()))
543 VEX_X = 0x0;
544 }
545 break;
546 default: // MRMDestReg, MRM0r-MRM7r, RawFrm
547 if (!MI.getNumOperands())
548 break;
549
550 if (MI.getOperand(CurOp).isReg() &&
551 X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
552 VEX_B = 0;
553
554 if (HasVEX_4V)
555 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
556
557 CurOp++;
558 for (; CurOp != NumOps; ++CurOp) {
559 const MCOperand &MO = MI.getOperand(CurOp);
560 if (MO.isReg() && !HasVEX_4V &&
561 X86II::isX86_64ExtendedReg(MO.getReg()))
562 VEX_R = 0x0;
563 }
564 break;
565 }
566
567 // Emit segment override opcode prefix as needed.
568 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
569
570 // VEX opcode prefix can have 2 or 3 bytes
571 //
572 // 3 bytes:
573 // +-----+ +--------------+ +-------------------+
574 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
575 // +-----+ +--------------+ +-------------------+
576 // 2 bytes:
577 // +-----+ +-------------------+
578 // | C5h | | R | vvvv | L | pp |
579 // +-----+ +-------------------+
580 //
581 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
582
583 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
584 EmitByte(0xC5, CurByte, OS);
585 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
586 return;
587 }
588
589 // 3 byte VEX prefix
590 EmitByte(0xC4, CurByte, OS);
591 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
592 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
593 }
594
595 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
596 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
597 /// size, and 3) use of X86-64 extended registers.
598 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
599 const MCInstrDesc &Desc) {
600 unsigned REX = 0;
601 if (TSFlags & X86II::REX_W)
602 REX |= 1 << 3; // set REX.W
603
604 if (MI.getNumOperands() == 0) return REX;
605
606 unsigned NumOps = MI.getNumOperands();
607 // FIXME: MCInst should explicitize the two-addrness.
608 bool isTwoAddr = NumOps > 1 &&
609 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
610
611 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
612 unsigned i = isTwoAddr ? 1 : 0;
613 for (; i != NumOps; ++i) {
614 const MCOperand &MO = MI.getOperand(i);
615 if (!MO.isReg()) continue;
616 unsigned Reg = MO.getReg();
617 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
618 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
619 // that returns non-zero.
620 REX |= 0x40; // REX fixed encoding prefix
621 break;
622 }
623
624 switch (TSFlags & X86II::FormMask) {
625 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
626 case X86II::MRMSrcReg:
627 if (MI.getOperand(0).isReg() &&
628 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
629 REX |= 1 << 2; // set REX.R
630 i = isTwoAddr ? 2 : 1;
631 for (; i != NumOps; ++i) {
632 const MCOperand &MO = MI.getOperand(i);
633 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
634 REX |= 1 << 0; // set REX.B
635 }
636 break;
637 case X86II::MRMSrcMem: {
638 if (MI.getOperand(0).isReg() &&
639 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
640 REX |= 1 << 2; // set REX.R
641 unsigned Bit = 0;
642 i = isTwoAddr ? 2 : 1;
643 for (; i != NumOps; ++i) {
644 const MCOperand &MO = MI.getOperand(i);
645 if (MO.isReg()) {
646 if (X86II::isX86_64ExtendedReg(MO.getReg()))
647 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
648 Bit++;
649 }
650 }
651 break;
652 }
653 case X86II::MRM0m: case X86II::MRM1m:
654 case X86II::MRM2m: case X86II::MRM3m:
655 case X86II::MRM4m: case X86II::MRM5m:
656 case X86II::MRM6m: case X86II::MRM7m:
657 case X86II::MRMDestMem: {
658 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
659 i = isTwoAddr ? 1 : 0;
660 if (NumOps > e && MI.getOperand(e).isReg() &&
661 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
662 REX |= 1 << 2; // set REX.R
663 unsigned Bit = 0;
664 for (; i != e; ++i) {
665 const MCOperand &MO = MI.getOperand(i);
666 if (MO.isReg()) {
667 if (X86II::isX86_64ExtendedReg(MO.getReg()))
668 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
669 Bit++;
670 }
671 }
672 break;
673 }
674 default:
675 if (MI.getOperand(0).isReg() &&
676 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
677 REX |= 1 << 0; // set REX.B
678 i = isTwoAddr ? 2 : 1;
679 for (unsigned e = NumOps; i != e; ++i) {
680 const MCOperand &MO = MI.getOperand(i);
681 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
682 REX |= 1 << 2; // set REX.R
683 }
684 break;
685 }
686 return REX;
687 }
688
689 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
690 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
691 unsigned &CurByte, int MemOperand,
692 const MCInst &MI,
693 raw_ostream &OS) const {
694 switch (TSFlags & X86II::SegOvrMask) {
695 default: assert(0 && "Invalid segment!");
696 case 0:
697 // No segment override, check for explicit one on memory operand.
698 if (MemOperand != -1) { // If the instruction has a memory operand.
699 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
700 default: assert(0 && "Unknown segment register!");
701 case 0: break;
702 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
703 case X86::SS: EmitByte(0x36, CurByte, OS); break;
704 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
705 case X86::ES: EmitByte(0x26, CurByte, OS); break;
706 case X86::FS: EmitByte(0x64, CurByte, OS); break;
707 case X86::GS: EmitByte(0x65, CurByte, OS); break;
708 }
709 }
710 break;
711 case X86II::FS:
712 EmitByte(0x64, CurByte, OS);
713 break;
714 case X86II::GS:
715 EmitByte(0x65, CurByte, OS);
716 break;
717 }
718 }
719
720 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
721 ///
722 /// MemOperand is the operand # of the start of a memory operand if present. If
723 /// Not present, it is -1.
724 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
725 int MemOperand, const MCInst &MI,
726 const MCInstrDesc &Desc,
727 raw_ostream &OS) const {
728
729 // Emit the lock opcode prefix as needed.
730 if (TSFlags & X86II::LOCK)
731 EmitByte(0xF0, CurByte, OS);
732
733 // Emit segment override opcode prefix as needed.
734 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
735
736 // Emit the repeat opcode prefix as needed.
737 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
738 EmitByte(0xF3, CurByte, OS);
739
740 // Emit the address size opcode prefix as needed.
741 if ((TSFlags & X86II::AdSize) ||
742 (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand)))
743 EmitByte(0x67, CurByte, OS);
744
745 // Emit the operand size opcode prefix as needed.
746 if (TSFlags & X86II::OpSize)
747 EmitByte(0x66, CurByte, OS);
748
749 bool Need0FPrefix = false;
750 switch (TSFlags & X86II::Op0Mask) {
751 default: assert(0 && "Invalid prefix!");
752 case 0: break; // No prefix!
753 case X86II::REP: break; // already handled.
754 case X86II::TB: // Two-byte opcode prefix
755 case X86II::T8: // 0F 38
756 case X86II::TA: // 0F 3A
757 case X86II::A6: // 0F A6
758 case X86II::A7: // 0F A7
759 Need0FPrefix = true;
760 break;
761 case X86II::TF: // F2 0F 38
762 EmitByte(0xF2, CurByte, OS);
763 Need0FPrefix = true;
764 break;
765 case X86II::XS: // F3 0F
766 EmitByte(0xF3, CurByte, OS);
767 Need0FPrefix = true;
768 break;
769 case X86II::XD: // F2 0F
770 EmitByte(0xF2, CurByte, OS);
771 Need0FPrefix = true;
772 break;
773 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
774 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
775 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
776 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
777 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
778 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
779 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
780 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
781 }
782
783 // Handle REX prefix.
784 // FIXME: Can this come before F2 etc to simplify emission?
785 if (is64BitMode()) {
786 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
787 EmitByte(0x40 | REX, CurByte, OS);
788 }
789
790 // 0x0F escape code must be emitted just before the opcode.
791 if (Need0FPrefix)
792 EmitByte(0x0F, CurByte, OS);
793
794 // FIXME: Pull this up into previous switch if REX can be moved earlier.
795 switch (TSFlags & X86II::Op0Mask) {
796 case X86II::TF: // F2 0F 38
797 case X86II::T8: // 0F 38
798 EmitByte(0x38, CurByte, OS);
799 break;
800 case X86II::TA: // 0F 3A
801 EmitByte(0x3A, CurByte, OS);
802 break;
803 case X86II::A6: // 0F A6
804 EmitByte(0xA6, CurByte, OS);
805 break;
806 case X86II::A7: // 0F A7
807 EmitByte(0xA7, CurByte, OS);
808 break;
809 }
810 }
811
812 void X86MCCodeEmitter::
813 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
814 SmallVectorImpl &Fixups) const {
815 unsigned Opcode = MI.getOpcode();
816 const MCInstrDesc &Desc = MCII.get(Opcode);
817 uint64_t TSFlags = Desc.TSFlags;
818
819 // Pseudo instructions don't get encoded.
820 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
821 return;
822
823 // If this is a two-address instruction, skip one of the register operands.
824 // FIXME: This should be handled during MCInst lowering.
825 unsigned NumOps = Desc.getNumOperands();
826 unsigned CurOp = 0;
827 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
828 ++CurOp;
829 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0)
830 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
831 --NumOps;
832
833 // Keep track of the current byte being emitted.
834 unsigned CurByte = 0;
835
836 // Is this instruction encoded using the AVX VEX prefix?
837 bool HasVEXPrefix = false;
838
839 // It uses the VEX.VVVV field?
840 bool HasVEX_4V = false;
841
842 if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
843 HasVEXPrefix = true;
844 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
845 HasVEX_4V = true;
846
847
848 // Determine where the memory operand starts, if present.
849 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
850 if (MemoryOperand != -1) MemoryOperand += CurOp;
851
852 if (!HasVEXPrefix)
853 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
854 else
855 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
856
857
858 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
859
860 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
861 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
862
863 unsigned SrcRegNum = 0;
864 switch (TSFlags & X86II::FormMask) {
865 case X86II::MRMInitReg:
866 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
867 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
868 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
869 case X86II::Pseudo:
870 assert(0 && "Pseudo instruction shouldn't be emitted");
871 case X86II::RawFrm:
872 EmitByte(BaseOpcode, CurByte, OS);
873 break;
874
875 case X86II::RawFrmImm8:
876 EmitByte(BaseOpcode, CurByte, OS);
877 EmitImmediate(MI.getOperand(CurOp++),
878 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
879 CurByte, OS, Fixups);
880 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
881 break;
882 case X86II::RawFrmImm16:
883 EmitByte(BaseOpcode, CurByte, OS);
884 EmitImmediate(MI.getOperand(CurOp++),
885 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
886 CurByte, OS, Fixups);
887 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
888 break;
889
890 case X86II::AddRegFrm:
891 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
892 break;
893
894 case X86II::MRMDestReg:
895 EmitByte(BaseOpcode, CurByte, OS);
896 EmitRegModRMByte(MI.getOperand(CurOp),
897 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
898 CurOp += 2;
899 break;
900
901 case X86II::MRMDestMem:
902 EmitByte(BaseOpcode, CurByte, OS);
903 SrcRegNum = CurOp + X86::AddrNumOperands;
904
905 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
906 SrcRegNum++;
907
908 EmitMemModRMByte(MI, CurOp,
909 GetX86RegNum(MI.getOperand(SrcRegNum)),
910 TSFlags, CurByte, OS, Fixups);
911 CurOp = SrcRegNum + 1;
912 break;
913
914 case X86II::MRMSrcReg:
915 EmitByte(BaseOpcode, CurByte, OS);
916 SrcRegNum = CurOp + 1;
917
918 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
919 SrcRegNum++;
920
921 EmitRegModRMByte(MI.getOperand(SrcRegNum),
922 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
923 CurOp = SrcRegNum + 1;
924 break;
925
926 case X86II::MRMSrcMem: {
927 int AddrOperands = X86::AddrNumOperands;
928 unsigned FirstMemOp = CurOp+1;
929 if (HasVEX_4V) {
930 ++AddrOperands;
931 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
932 }
933
934 EmitByte(BaseOpcode, CurByte, OS);