llvm.org GIT mirror llvm / a84e7b8
RegisterPressure: Factor out liveness dead-def detection logic; NFCI Detecting additional dead-defs without a dead flag that are only visible through liveness information should be part of the register operand collection not intertwined with the register pressure update logic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255192 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 4 years ago
2 changed file(s) with 43 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
440440 /// after the current position.
441441 SlotIndex getCurrSlot() const;
442442
443 const LiveRange *getLiveRange(unsigned Reg) const;
444
445443 void increaseRegPressure(ArrayRef Regs);
446444 void decreaseRegPressure(ArrayRef Regs);
447445
170170 Regs.clear();
171171 }
172172
173 const LiveRange *RegPressureTracker::getLiveRange(unsigned Reg) const {
173 static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) {
174174 if (TargetRegisterInfo::isVirtualRegister(Reg))
175 return &LIS->getInterval(Reg);
176 return LIS->getCachedRegUnit(Reg);
175 return &LIS.getInterval(Reg);
176 return LIS.getCachedRegUnit(Reg);
177177 }
178178
179179 void RegPressureTracker::reset() {
322322
323323 void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
324324 const MachineRegisterInfo &MRI, bool IgnoreDead = false);
325
326 /// Use liveness information to find dead defs not marked with a dead flag
327 /// and move them to the DeadDefs vector.
328 void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
325329 };
326330
327331 /// Collect this instruction's unique uses and defs into SmallVectors for
392396 Collector.collectInstr(MI);
393397 }
394398
399 void RegisterOperands::detectDeadDefs(const MachineInstr &MI,
400 const LiveIntervals &LIS) {
401 SlotIndex SlotIdx = LIS.getInstructionIndex(&MI);
402 for (SmallVectorImpl::iterator RI = Defs.begin();
403 RI != Defs.end(); /*empty*/) {
404 unsigned Reg = *RI;
405 const LiveRange *LR = getLiveRange(LIS, Reg);
406 if (LR != nullptr) {
407 LiveQueryResult LRQ = LR->Query(SlotIdx);
408 if (LRQ.isDeadDef()) {
409 // LiveIntervals knows this is a dead even though it's MachineOperand is
410 // not flagged as such.
411 DeadDefs.push_back(Reg);
412 RI = Defs.erase(RI);
413 continue;
414 }
415 }
416 ++RI;
417 }
418 }
419
395420 } // namespace
396421
397422 /// Initialize an array of N PressureDiffs.
513538 if (RequireIntervals && isTopClosed())
514539 static_cast(P).openTop(SlotIdx);
515540
541 const MachineInstr &MI = *CurrPos;
516542 RegisterOperands RegOpers;
517 RegOpers.collect(*CurrPos, *TRI, *MRI);
543 RegOpers.collect(MI, *TRI, *MRI);
544 if (RequireIntervals)
545 RegOpers.detectDeadDefs(MI, *LIS);
518546
519547 if (PDiff)
520548 collectPDiff(*PDiff, RegOpers, MRI);
526554 // Kill liveness at live defs.
527555 // TODO: consider earlyclobbers?
528556 for (unsigned Reg : RegOpers.Defs) {
529 bool DeadDef = false;
530 if (RequireIntervals) {
531 const LiveRange *LR = getLiveRange(Reg);
532 if (LR) {
533 LiveQueryResult LRQ = LR->Query(SlotIdx);
534 DeadDef = LRQ.isDeadDef();
535 }
536 }
537 if (DeadDef) {
538 // LiveIntervals knows this is a dead even though it's MachineOperand is
539 // not flagged as such. Since this register will not be recorded as
540 // live-out, increase its PDiff value to avoid underflowing pressure.
541 if (PDiff)
542 PDiff->addPressureChange(Reg, false, MRI);
543 } else {
544 if (LiveRegs.erase(Reg))
545 decreaseRegPressure(Reg);
546 else
547 discoverLiveOut(Reg);
548 }
557 if (LiveRegs.erase(Reg))
558 decreaseRegPressure(Reg);
559 else
560 discoverLiveOut(Reg);
549561 }
550562
551563 // Generate liveness for uses.
553565 if (!LiveRegs.contains(Reg)) {
554566 // Adjust liveouts if LiveIntervals are available.
555567 if (RequireIntervals) {
556 const LiveRange *LR = getLiveRange(Reg);
568 const LiveRange *LR = getLiveRange(*LIS, Reg);
557569 if (LR) {
558570 LiveQueryResult LRQ = LR->Query(SlotIdx);
559571 if (!LRQ.isKill() && !LRQ.valueDefined())
605617 // Kill liveness at last uses.
606618 bool lastUse = false;
607619 if (RequireIntervals) {
608 const LiveRange *LR = getLiveRange(Reg);
620 const LiveRange *LR = getLiveRange(*LIS, Reg);
609621 lastUse = LR && LR->Query(SlotIdx).isKill();
610622 } else {
611623 // Allocatable physregs are always single-use before register rewriting.
725737 RegisterOperands RegOpers;
726738 RegOpers.collect(*MI, *TRI, *MRI, /*IgnoreDead=*/true);
727739 assert(RegOpers.DeadDefs.size() == 0);
740 if (RequireIntervals)
741 RegOpers.detectDeadDefs(*MI, *LIS);
728742
729743 // Kill liveness at live defs.
730744 for (unsigned Reg : RegOpers.Defs) {
731 bool DeadDef = false;
732 if (RequireIntervals) {
733 const LiveRange *LR = getLiveRange(Reg);
734 if (LR) {
735 SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
736 LiveQueryResult LRQ = LR->Query(SlotIdx);
737 DeadDef = LRQ.isDeadDef();
738 }
739 }
740 if (!DeadDef) {
741 if (!containsReg(RegOpers.Uses, Reg))
742 decreaseRegPressure(Reg);
743 }
745 if (!containsReg(RegOpers.Uses, Reg))
746 decreaseRegPressure(Reg);
744747 }
745748 // Generate liveness for uses.
746749 for (unsigned Reg : RegOpers.Uses) {
925928 // FIXME: allow the caller to pass in the list of vreg uses that remain
926929 // to be bottom-scheduled to avoid searching uses at each query.
927930 SlotIndex CurrIdx = getCurrSlot();
928 const LiveRange *LR = getLiveRange(Reg);
931 const LiveRange *LR = getLiveRange(*LIS, Reg);
929932 if (LR) {
930933 LiveQueryResult LRQ = LR->Query(SlotIdx);
931934 if (LRQ.isKill() && !findUseBetween(Reg, CurrIdx, SlotIdx, *MRI, LIS))