llvm.org GIT mirror llvm / a82e676
[PowerPC] Split the blr definition into BLR and BLR8 We really need a separate 64-bit version of this instruction so that it can be marked as clobbering LR8 (instead of just LR). No change in functionality (although the verifier might be slightly happier), however, it is required for stackmap/patchpoint support. Thus, this will be covered by stackmap test cases once those are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225804 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
5 changed file(s) with 13 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
16571657 }
16581658
16591659 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1660 TII.get(PPC::BLR));
1660 TII.get(PPC::BLR8));
16611661
16621662 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
16631663 MIB.addReg(RetRegs[i], RegState::Implicit);
870870 DebugLoc dl;
871871
872872 assert((RetOpcode == PPC::BLR ||
873 RetOpcode == PPC::BLR8 ||
873874 RetOpcode == PPC::TCRETURNri ||
874875 RetOpcode == PPC::TCRETURNdi ||
875876 RetOpcode == PPC::TCRETURNai ||
10561057
10571058 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
10581059 // call optimization
1059 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
1060 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1061 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
10601062 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
10611063 PPCFunctionInfo *FI = MF.getInfo();
10621064 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
8080
8181 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
8282 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
83 let isReturn = 1, Uses = [LR8, RM] in
84 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
85 [(retflag)]>, Requires<[In64BitMode]>;
8386 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
8487 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
8588 []>,
11121112 MachineInstr *MI,
11131113 const SmallVectorImpl &Pred) const {
11141114 unsigned OpC = MI->getOpcode();
1115 if (OpC == PPC::BLR) {
1115 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
11161116 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
11171117 bool isPPC64 = Subtarget.isPPC64();
11181118 MI->setDesc(get(Pred[0].getImm() ?
12761276 return false;
12771277 case PPC::B:
12781278 case PPC::BLR:
1279 case PPC::BLR8:
12791280 case PPC::BCTR:
12801281 case PPC::BCTR8:
12811282 case PPC::BCTRL:
21372138 I = ReturnMBB.SkipPHIsAndLabels(I);
21382139
21392140 // The block must be essentially empty except for the blr.
2140 if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
2141 if (I == ReturnMBB.end() ||
2142 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
21412143 I != ReturnMBB.getLastNonDebugInstr())
21422144 return Changed;
21432145
21502152 if (J->getOperand(0).getMBB() == &ReturnMBB) {
21512153 // This is an unconditional branch to the return. Replace the
21522154 // branch with a blr.
2153 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
2155 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()));
21542156 MachineBasicBlock::iterator K = J--;
21552157 K->eraseFromParent();
21562158 BlockChanged = true;
10151015 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
10161016 let isReturn = 1, Uses = [LR, RM] in
10171017 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1018 [(retflag)]>;
1018 [(retflag)]>, Requires<[In32BitMode]>;
10191019 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
10201020 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
10211021 []>;