llvm.org GIT mirror llvm / a80ff26
Add override to overriden virtual methods, remove virtual keywords. No functionality change. Changes made by clang-tidy + some manual cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217028 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 6 years ago
31 changed file(s) with 73 addition(s) and 101 deletion(s). Raw diff Collapse all Expand all
125125 void EmitZeros(uint64_t NumBytes) override;
126126 void FinishImpl() override;
127127
128 virtual bool mayHaveInstructions() const {
128 bool mayHaveInstructions() const override {
129129 return getCurrentSectionData()->hasInstructions();
130130 }
131131 };
165165 : CrashRecoveryContextCleanupBase<
166166 CrashRecoveryContextDeleteCleanup, T>(context, resource) {}
167167
168 virtual void recoverResources() {
169 delete this->resource;
170 }
168 void recoverResources() override { delete this->resource; }
171169 };
172170
173171 template
180178 : CrashRecoveryContextCleanupBase,
181179 T>(context, resource) {}
182180
183 virtual void recoverResources() {
184 this->resource->Release();
185 }
181 void recoverResources() override { this->resource->Release(); }
186182 };
187183
188184 template >
687687 }
688688
689689 /// useMachineCombiner - return true when a target supports MachineCombiner
690 virtual bool useMachineCombiner(void) const { return false; }
690 virtual bool useMachineCombiner() const { return false; }
691691
692692 protected:
693693 /// foldMemoryOperandImpl - Target-dependent implementation for
7979 initializeScopedNoAliasAAPass(*PassRegistry::getPassRegistry());
8080 }
8181
82 virtual void initializePass() {
83 InitializeAliasAnalysis(this);
84 }
82 void initializePass() override { InitializeAliasAnalysis(this); }
8583
8684 /// getAdjustedAnalysisPointer - This method is used when a pass implements
8785 /// an analysis interface through multiple inheritance. If needed, it
8886 /// should override this to adjust the this pointer as needed for the
8987 /// specified pass info.
90 virtual void *getAdjustedAnalysisPointer(const void *PI) {
88 void *getAdjustedAnalysisPointer(const void *PI) override {
9189 if (PI == &AliasAnalysis::ID)
9290 return (AliasAnalysis*)this;
9391 return this;
9997 SmallPtrSetImpl &Nodes) const;
10098
10199 private:
102 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
103 virtual AliasResult alias(const Location &LocA, const Location &LocB);
104 virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal);
105 virtual ModRefBehavior getModRefBehavior(ImmutableCallSite CS);
106 virtual ModRefBehavior getModRefBehavior(const Function *F);
107 virtual ModRefResult getModRefInfo(ImmutableCallSite CS,
108 const Location &Loc);
109 virtual ModRefResult getModRefInfo(ImmutableCallSite CS1,
110 ImmutableCallSite CS2);
100 void getAnalysisUsage(AnalysisUsage &AU) const override;
101 AliasResult alias(const Location &LocA, const Location &LocB) override;
102 bool pointsToConstantMemory(const Location &Loc, bool OrLocal) override;
103 ModRefBehavior getModRefBehavior(ImmutableCallSite CS) override;
104 ModRefBehavior getModRefBehavior(const Function *F) override;
105 ModRefResult getModRefInfo(ImmutableCallSite CS,
106 const Location &Loc) override;
107 ModRefResult getModRefInfo(ImmutableCallSite CS1,
108 ImmutableCallSite CS2) override;
111109 };
112110 } // End of anonymous namespace
113111
139139 public:
140140 RuntimeDyldMachOCRTPBase(RTDyldMemoryManager *mm) : RuntimeDyldMachO(mm) {}
141141
142 void finalizeLoad(ObjectImage &ObjImg, ObjSectionToIDMap &SectionMap) {
142 void finalizeLoad(ObjectImage &ObjImg,
143 ObjSectionToIDMap &SectionMap) override {
143144 unsigned EHFrameSID = RTDYLD_INVALID_SECTION_ID;
144145 unsigned TextSID = RTDYLD_INVALID_SECTION_ID;
145146 unsigned ExceptTabSID = RTDYLD_INVALID_SECTION_ID;
295295 return ++RelI;
296296 }
297297
298 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
298 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
299299 DEBUG(dumpRelocationToResolve(RE, Value));
300300
301301 const SectionEntry &Section = Sections[RE.SectionID];
7777 return ++RelI;
7878 }
7979
80 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
80 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
8181 DEBUG(dumpRelocationToResolve(RE, Value));
8282 const SectionEntry &Section = Sections[RE.SectionID];
8383 uint8_t *LocalAddress = Section.Address + RE.Offset;
7474 return ++RelI;
7575 }
7676
77 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
77 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
7878 DEBUG(dumpRelocationToResolve(RE, Value));
7979
8080 const SectionEntry &Section = Sections[RE.SectionID];
6060 return ++RelI;
6161 }
6262
63 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
63 void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
6464 DEBUG(dumpRelocationToResolve(RE, Value));
6565 const SectionEntry &Section = Sections[RE.SectionID];
6666 uint8_t *LocalAddress = Section.Address + RE.Offset;
8989 unsigned ByteAlignment) override;
9090 void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = nullptr,
9191 uint64_t Size = 0, unsigned ByteAlignment = 0) override;
92 virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
93 uint64_t Size, unsigned ByteAlignment = 0) override;
92 void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, uint64_t Size,
93 unsigned ByteAlignment = 0) override;
9494
9595 void EmitFileDirective(StringRef Filename) override {
9696 // FIXME: Just ignore the .file; it isn't important enough to fail the
425425 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
426426
427427 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
428 std::vector *Created) const;
428 std::vector *Created) const override;
429429
430430 ConstraintType
431431 getConstraintType(const std::string &Constraint) const override;
22052205 NopInst.addOperand(MCOperand::CreateImm(0));
22062206 }
22072207 /// useMachineCombiner - return true when a target supports MachineCombiner
2208 bool AArch64InstrInfo::useMachineCombiner(void) const {
2208 bool AArch64InstrInfo::useMachineCombiner() const {
22092209 // AArch64 supports the combiner
22102210 return true;
22112211 }
160160 /// for an instruction chain ending in . All potential patterns are
161161 /// listed
162162 /// in the array.
163 virtual bool hasPattern(
164 MachineInstr &Root,
165 SmallVectorImpl &Pattern) const;
163 bool hasPattern(MachineInstr &Root,
164 SmallVectorImpl &Pattern)
165 const override;
166166
167167 /// genAlternativeCodeSequence - when hasPattern() finds a pattern
168168 /// this function generates the instructions that could replace the
169169 /// original code sequence
170 virtual void genAlternativeCodeSequence(
170 void genAlternativeCodeSequence(
171171 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
172172 SmallVectorImpl &InsInstrs,
173173 SmallVectorImpl &DelInstrs,
174 DenseMap &InstrIdxForVirtReg) const;
174 DenseMap &InstrIdxForVirtReg) const override;
175175 /// useMachineCombiner - AArch64 supports MachineCombiner
176 virtual bool useMachineCombiner(void) const;
176 bool useMachineCombiner() const override;
177177
178178 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
179179 private:
126126
127127 void printInstruction(const MCInst *MI, raw_ostream &O) override;
128128 bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
129 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
130 unsigned PrintMethodIdx, raw_ostream &O);
129 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
130 unsigned PrintMethodIdx,
131 raw_ostream &O) override;
131132 StringRef getRegName(unsigned RegNo) const override {
132133 return getRegisterName(RegNo);
133134 }
436436
437437 /// getInstrItins - Return the instruction itineraries based on subtarget
438438 /// selection.
439 const InstrItineraryData *getInstrItineraryData() const {
439 const InstrItineraryData *getInstrItineraryData() const override {
440440 return &InstrItins;
441441 }
442442
5757
5858 /// getInstrItins - Return the instruction itineraries based on subtarget
5959 /// selection.
60 const InstrItineraryData *getInstrItineraryData() const {
60 const InstrItineraryData *getInstrItineraryData() const override {
6161 return &InstrItins;
6262 }
6363 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
64 const HexagonRegisterInfo *getRegisterInfo() const {
64 const HexagonRegisterInfo *getRegisterInfo() const override {
6565 return &InstrInfo.getRegisterInfo();
6666 }
67 const HexagonTargetLowering *getTargetLowering() const { return &TLInfo; }
68 const HexagonFrameLowering *getFrameLowering() const {
67 const HexagonTargetLowering *getTargetLowering() const override {
68 return &TLInfo;
69 }
70 const HexagonFrameLowering *getFrameLowering() const override {
6971 return &FrameLowering;
7072 }
71 const HexagonSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
72 const DataLayout *getDataLayout() const { return &DL; }
73 const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
74 return &TSInfo;
75 }
76 const DataLayout *getDataLayout() const override { return &DL; }
7377
7478 HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
7579 StringRef FS);
162162 void emitDirectiveSetDsp() override;
163163
164164 // PIC support
165 virtual void emitDirectiveCpload(unsigned RegNo);
165 void emitDirectiveCpload(unsigned RegNo) override;
166166 void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
167167 const MCSymbol &Sym, bool IsReg) override;
168168
208208 void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
209209
210210 // PIC support
211 virtual void emitDirectiveCpload(unsigned RegNo);
211 void emitDirectiveCpload(unsigned RegNo) override;
212212 void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
213213 const MCSymbol &Sym, bool IsReg) override;
214214
504504
505505 bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
506506
507 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
508 return true;
509 }
507 bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
510508
511509 private:
512510 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
3232 public:
3333 NVPTXReplaceImageHandles();
3434
35 bool runOnMachineFunction(MachineFunction &MF);
35 bool runOnMachineFunction(MachineFunction &MF) override;
3636
3737 const char *getPassName() const override {
3838 return "NVPTX Replace Image Handles";
2828 virtual ~PPCDisassembler() {}
2929
3030 // Override MCDisassembler.
31 virtual DecodeStatus getInstruction(MCInst &instr,
32 uint64_t &size,
33 const MemoryObject ®ion,
34 uint64_t address,
35 raw_ostream &vStream,
36 raw_ostream &cStream) const override;
31 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
32 const MemoryObject ®ion, uint64_t address,
33 raw_ostream &vStream,
34 raw_ostream &cStream) const override;
3735 };
3836 } // end anonymous namespace
3937
2323 public:
2424 PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI);
2525
26 virtual ~PPCELFObjectWriter();
2726 protected:
28 virtual unsigned getRelocTypeInner(const MCValue &Target,
29 const MCFixup &Fixup,
30 bool IsPCRel) const;
3127 unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
3228 bool IsPCRel) const override;
3329
4036 : MCELFObjectTargetWriter(Is64Bit, OSABI,
4137 Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC,
4238 /*HasRelocationAddend*/ true) {}
43
44 PPCELFObjectWriter::~PPCELFObjectWriter() {
45 }
4639
4740 static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target,
4841 const MCFixup &Fixup) {
7265 llvm_unreachable("unknown PPCMCExpr kind");
7366 }
7467
75 unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
76 const MCFixup &Fixup,
77 bool IsPCRel) const
78 {
68 unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
69 const MCFixup &Fixup,
70 bool IsPCRel) const {
7971 MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup);
8072
8173 // determine the type of the relocation
397389 }
398390 }
399391 return Type;
400 }
401
402 unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
403 const MCFixup &Fixup,
404 bool IsPCRel) const {
405 return getRelocTypeInner(Target, Fixup, IsPCRel);
406392 }
407393
408394 bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCSymbolData &SD,
7979 }
8080
8181 /// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
82 /// Outline based on PPCELFObjectWriter::getRelocTypeInner().
82 /// Outline based on PPCELFObjectWriter::GetRelocType().
8383 static unsigned getRelocType(const MCValue &Target,
8484 const MCFixupKind FixupKind, // from
8585 // Fixup.getKind()
152152 const SelectionDAG &DAG,
153153 unsigned Depth = 0) const override;
154154
155 virtual unsigned ComputeNumSignBitsForTargetNode(
156 SDValue Op,
157 const SelectionDAG &DAG,
158 unsigned Depth = 0) const override;
155 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
156 unsigned Depth = 0) const override;
159157
160158 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
161159 /// MachineFunction.
7171 MachineBasicBlock::iterator &MBBI,
7272 LiveVariables *LV) const override;
7373
74
75 virtual void copyPhysReg(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator MI, DebugLoc DL,
77 unsigned DestReg, unsigned SrcReg,
78 bool KillSrc) const = 0;
7974
8075 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
8176
3535 public:
3636 AMDGPUPromoteAlloca(const AMDGPUSubtarget &st) : FunctionPass(ID), ST(st),
3737 LocalMemAvailable(0) { }
38 virtual bool doInitialization(Module &M);
39 virtual bool runOnFunction(Function &F);
40 virtual const char *getPassName() const {
41 return "AMDGPU Promote Alloca";
42 }
38 bool doInitialization(Module &M) override;
39 bool runOnFunction(Function &F) override;
40 const char *getPassName() const override { return "AMDGPU Promote Alloca"; }
4341 void visitAlloca(AllocaInst &I);
4442 };
4543
5050 unsigned getSubRegFromChannel(unsigned Channel) const;
5151
5252 const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
53 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
53 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
5454 unsigned FIOperandNum,
5555 RegScavenger *RS) const override;
5656 unsigned getFrameRegister(const MachineFunction &MF) const override;
7979 return nullptr;
8080 }
8181
82 virtual void addCodeGenPrepare();
82 void addCodeGenPrepare() override;
8383 bool addPreISel() override;
8484 bool addInstSelector() override;
8585 bool addPreRegAlloc() override;
3535 const AMDGPUSubtarget *getSubtargetImpl() const override {
3636 return &Subtarget;
3737 }
38 const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { return &IntrinsicInfo; }
38 const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
39 return &IntrinsicInfo;
40 }
3941 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
4042
4143 /// \brief Register R600 analysis passes with a pass manager.
205205 int getInstrLatency(const InstrItineraryData *ItinData,
206206 SDNode *Node) const override { return 1;}
207207
208 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
208 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
209209
210210 /// \brief Reserve the registers that may be accesed using indirect addressing.
211211 void reserveIndirectRegisters(BitVector &Reserved,
8686 const TargetRegisterClass *RC,
8787 const TargetRegisterInfo *TRI) const override;
8888
89 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
89 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
9090
9191 unsigned commuteOpcode(unsigned Opcode) const;
9292
3636 MCDisassembler(STI, Ctx) {}
3737
3838 /// \brief See MCDisassembler.
39 virtual DecodeStatus getInstruction(MCInst &instr,
40 uint64_t &size,
41 const MemoryObject ®ion,
42 uint64_t address,
43 raw_ostream &vStream,
44 raw_ostream &cStream) const override;
45
39 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
40 const MemoryObject ®ion, uint64_t address,
41 raw_ostream &vStream,
42 raw_ostream &cStream) const override;
4643 };
4744 }
4845