llvm.org GIT mirror llvm / a7f892b
Convert SelectionDAG::getMergeValues to use ArrayRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207374 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
19 changed file(s) with 71 addition(s) and 74 deletion(s). Raw diff Collapse all Expand all
746746 EVT MemVT, MachineMemOperand *MMO);
747747
748748 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
749 SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, SDLoc dl);
749 SDValue getMergeValues(ArrayRef Ops, SDLoc dl);
750750
751751 /// getLoad - Loads are not normal binary operators: their result type is not
752752 /// determined by their operands, and they produce a value AND a token chain.
43984398 }
43994399
44004400 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
4401 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
4402 SDLoc dl) {
4403 if (NumOps == 1)
4401 SDValue SelectionDAG::getMergeValues(ArrayRef Ops, SDLoc dl) {
4402 if (Ops.size() == 1)
44044403 return Ops[0];
44054404
44064405 SmallVector VTs;
4407 VTs.reserve(NumOps);
4408 for (unsigned i = 0; i < NumOps; ++i)
4406 VTs.reserve(Ops.size());
4407 for (unsigned i = 0; i < Ops.size(); ++i)
44094408 VTs.push_back(Ops[i].getValueType());
4410 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs),
4411 ArrayRef(Ops, NumOps));
4409 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops.data(), Ops.size());
44124410 }
44134411
44144412 SDValue
10911091 Constants.push_back(SDValue(Val, i));
10921092 }
10931093
1094 return DAG.getMergeValues(&Constants[0], Constants.size(),
1095 getCurSDLoc());
1094 return DAG.getMergeValues(Constants, getCurSDLoc());
10961095 }
10971096
10981097 if (const ConstantDataSequential *CDS =
11071106 }
11081107
11091108 if (isa(CDS->getType()))
1110 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1109 return DAG.getMergeValues(Ops, getCurSDLoc());
11111110 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
11121111 VT, Ops);
11131112 }
11321131 Constants[i] = DAG.getConstant(0, EltVT);
11331132 }
11341133
1135 return DAG.getMergeValues(&Constants[0], NumElts,
1136 getCurSDLoc());
1134 return DAG.getMergeValues(Constants, getCurSDLoc());
11371135 }
11381136
11391137 if (const BlockAddress *BA = dyn_cast(C))
74977495 dyn_cast(ArgValues[0].getNode()))
74987496 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
74997497
7500 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7498 SDValue Res = DAG.getMergeValues(ArrayRef(ArgValues.data(),
7499 NumValues),
75017500 SDB->getCurSDLoc());
75027501
75037502 SDB->setValue(I, Res);
45854585 TrueVal, FalseVal, A64cc);
45864586
45874587 SDValue Ops[2] = { Lo, Hi };
4588 return DAG.getMergeValues(Ops, 2, dl);
4588 return DAG.getMergeValues(Ops, dl);
45894589 }
45904590
45914591 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
46244624 Tmp3, FalseVal, A64cc);
46254625
46264626 SDValue Ops[2] = { Lo, Hi };
4627 return DAG.getMergeValues(Ops, 2, dl);
4627 return DAG.getMergeValues(Ops, dl);
46284628 }
46294629
46304630 // If this is a case we can't handle, return null and let the default
38693869 CCR, Cmp);
38703870
38713871 SDValue Ops[2] = { Lo, Hi };
3872 return DAG.getMergeValues(Ops, 2, dl);
3872 return DAG.getMergeValues(Ops, dl);
38733873 }
38743874
38753875 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
39033903 CCR, Cmp);
39043904
39053905 SDValue Ops[2] = { Lo, Hi };
3906 return DAG.getMergeValues(Ops, 2, dl);
3906 return DAG.getMergeValues(Ops, dl);
39073907 }
39083908
39093909 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
33463346 DAG.getIntPtrConstant(1));
33473347 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
33483348 // Merge the rounded value with the chain output of the load.
3349 return DAG.getMergeValues(Ops, 2, DL);
3349 return DAG.getMergeValues(Ops, DL);
33503350 }
33513351
33523352 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
34333433 DAG.getNode(ARM64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
34343434
34353435 SDValue Ops[2] = { Lo, Hi };
3436 return DAG.getMergeValues(Ops, 2, dl);
3436 return DAG.getMergeValues(Ops, dl);
34373437 }
34383438
34393439 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
34733473 DAG.getNode(ARM64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
34743474
34753475 SDValue Ops[2] = { Lo, Hi };
3476 return DAG.getMergeValues(Ops, 2, dl);
3476 return DAG.getMergeValues(Ops, dl);
34773477 }
34783478
34793479 bool
816816 Sub);
817817
818818 SDValue Ops[2] = { ArgAdjust, CopyChain };
819 return DAG.getMergeValues(Ops, 2, dl);
819 return DAG.getMergeValues(Ops, dl);
820820 }
821821
822822 SDValue
18751875 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
18761876
18771877 SDValue Ops[2] = {Lo, Hi};
1878 return DAG.getMergeValues(Ops, 2, DL);
1878 return DAG.getMergeValues(Ops, DL);
18791879 }
18801880
18811881 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
19161916 ShiftRightHi);
19171917
19181918 SDValue Ops[2] = {Lo, Hi};
1919 return DAG.getMergeValues(Ops, 2, DL);
1919 return DAG.getMergeValues(Ops, DL);
19201920 }
19211921
19221922 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
19951995 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
19961996 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
19971997 SDValue Ops[] = { SRL, LWR.getValue(1) };
1998 return DAG.getMergeValues(Ops, 2, DL);
1998 return DAG.getMergeValues(Ops, DL);
19991999 }
20002000
20012001 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
11171117
11181118 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
11191119 SDValue Ops[2] = {BP, Hi.getValue(1)};
1120 return DAG.getMergeValues(Ops, 2, DL);
1120 return DAG.getMergeValues(Ops, DL);
11211121 }
11221122
11231123 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
11681168 return HasLo ? Lo : Hi;
11691169
11701170 SDValue Vals[] = { Lo, Hi };
1171 return DAG.getMergeValues(Vals, 2, DL);
1171 return DAG.getMergeValues(Vals, DL);
11721172 }
11731173
11741174
12431243
12441244 assert(Val->getValueType(1) == MVT::Other);
12451245 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1246 return DAG.getMergeValues(Vals, 2, DL);
1246 return DAG.getMergeValues(Vals, DL);
12471247 }
12481248
12491249 // Lower an MSA copy intrinsic into the specified SelectionDAG node
13131313 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
13141314 // in LegalizeDAG.cpp which also uses MergeValues.
13151315 SDValue Ops[] = { result, LD->getChain() };
1316 return DAG.getMergeValues(Ops, 2, dl);
1316 return DAG.getMergeValues(Ops, dl);
13171317 }
13181318
13191319 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
49224922 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
49234923
49244924 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4925 return DAG.getMergeValues(Ops, 2, dl);
4925 return DAG.getMergeValues(Ops, dl);
49264926 }
49274927
49284928 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
53405340 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
53415341 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
53425342 SDValue OutOps[] = { OutLo, OutHi };
5343 return DAG.getMergeValues(OutOps, 2, dl);
5343 return DAG.getMergeValues(OutOps, dl);
53445344 }
53455345
53465346 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
53695369 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
53705370 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
53715371 SDValue OutOps[] = { OutLo, OutHi };
5372 return DAG.getMergeValues(OutOps, 2, dl);
5372 return DAG.getMergeValues(OutOps, dl);
53735373 }
53745374
53755375 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
53985398 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
53995399 Tmp4, Tmp6, ISD::SETLE);
54005400 SDValue OutOps[] = { OutLo, OutHi };
5401 return DAG.getMergeValues(OutOps, 2, dl);
5401 return DAG.getMergeValues(OutOps, dl);
54025402 }
54035403
54045404 //===----------------------------------------------------------------------===//
10461046 Div,
10471047 Rem
10481048 };
1049 return DAG.getMergeValues(Ops, 2, DL);
1049 return DAG.getMergeValues(Ops, DL);
10501050 }
10511051
10521052 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
12381238 Ret,
12391239 Chain
12401240 };
1241 return DAG.getMergeValues(Ops, 2, DL);
1241 return DAG.getMergeValues(Ops, DL);
12421242 }
12431243
12441244
12471247 SplitVectorLoad(Op, DAG),
12481248 Chain
12491249 };
1250 return DAG.getMergeValues(MergedValues, 2, DL);
1250 return DAG.getMergeValues(MergedValues, DL);
12511251 }
12521252
12531253 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
12951295 Result,
12961296 Chain
12971297 };
1298 return DAG.getMergeValues(MergedValues, 2, DL);
1298 return DAG.getMergeValues(MergedValues, DL);
12991299 }
13001300
13011301 // For most operations returning SDValue() will result in the node being
13191319 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
13201320
13211321 SDValue MergedValues[2] = { Sra, Chain };
1322 return DAG.getMergeValues(MergedValues, 2, DL);
1322 return DAG.getMergeValues(MergedValues, DL);
13231323 }
13241324
13251325 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
13691369 Chain
13701370 };
13711371
1372 return DAG.getMergeValues(Ops, 2, DL);
1372 return DAG.getMergeValues(Ops, DL);
13731373 }
13741374
13751375 /// XXX Only kernel functions are supported, so we can assume for now that
558558 SplitVectorLoad(Op, DAG),
559559 Load->getChain()
560560 };
561 return DAG.getMergeValues(MergedValues, 2, SDLoc(Op));
561 return DAG.getMergeValues(MergedValues, SDLoc(Op));
562562 } else {
563563 return LowerLOAD(Op, DAG);
564564 }
786786 MergedValues[1] = Load->getChain();
787787 if (Ret.getNode()) {
788788 MergedValues[0] = Ret;
789 return DAG.getMergeValues(MergedValues, 2, DL);
789 return DAG.getMergeValues(MergedValues, DL);
790790 }
791791
792792 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
817817 }
818818
819819 MergedValues[0] = Ret;
820 return DAG.getMergeValues(MergedValues, 2, DL);
820 return DAG.getMergeValues(MergedValues, DL);
821821
822822 }
823823
24212421 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
24222422 DAG.getConstant(regSpillArea, VT));
24232423 SDValue Ops[2] = { NewVal, Chain };
2424 return DAG.getMergeValues(Ops, 2, dl);
2424 return DAG.getMergeValues(Ops, dl);
24252425 }
24262426
24272427
25922592 SDValue(Lo64.getNode(), 1) };
25932593 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
25942594 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2595 return DAG.getMergeValues(Ops, 2, dl);
2595 return DAG.getMergeValues(Ops, dl);
25962596 }
25972597
25982598 // Lower a f128 store into two f64 stores.
27172717
27182718 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
27192719 SDValue Ops[2] = { Dst, Carry };
2720 return DAG.getMergeValues(Ops, 2, dl);
2720 return DAG.getMergeValues(Ops, dl);
27212721 }
27222722
27232723 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
27642764 DAG.DeleteNode(MulResult.getNode());
27652765
27662766 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2767 return DAG.getMergeValues(Ops, 2, dl);
2767 return DAG.getMergeValues(Ops, dl);
27682768 }
27692769
27702770 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
20092009 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
20102010
20112011 SDValue Ops[2] = { Result, Chain };
2012 return DAG.getMergeValues(Ops, 2, DL);
2012 return DAG.getMergeValues(Ops, DL);
20132013 }
20142014
20152015 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
20512051 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
20522052 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
20532053 }
2054 return DAG.getMergeValues(Ops, 2, DL);
2054 return DAG.getMergeValues(Ops, DL);
20552055 }
20562056
20572057 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
20702070 // low half first, so the results are in reverse order.
20712071 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
20722072 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2073 return DAG.getMergeValues(Ops, 2, DL);
2073 return DAG.getMergeValues(Ops, DL);
20742074 }
20752075
20762076 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
20972097 SDValue Ops[2];
20982098 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
20992099 Op0, Op1, Ops[1], Ops[0]);
2100 return DAG.getMergeValues(Ops, 2, DL);
2100 return DAG.getMergeValues(Ops, DL);
21012101 }
21022102
21032103 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
21152115 else
21162116 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
21172117 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2118 return DAG.getMergeValues(Ops, 2, DL);
2118 return DAG.getMergeValues(Ops, DL);
21192119 }
21202120
21212121 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
22652265 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
22662266
22672267 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2268 return DAG.getMergeValues(RetOps, 2, DL);
2268 return DAG.getMergeValues(RetOps, DL);
22692269 }
22702270
22712271 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
18471847 }
18481848 cast(Ret)->setMemRefs(MemOp, MemOp + 1);
18491849 SDValue RetVals[] = { Undef, Ret };
1850 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1850 return CurDAG->getMergeValues(RetVals, dl).getNode();
18511851 }
18521852
18531853 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
88008800 }
88018801
88028802 SDValue Ops[2] = { Lo, Hi };
8803 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8803 return DAG.getMergeValues(Ops, dl);
88048804 }
88058805
88068806 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
92019201 SDValue Ops[] = { eax, edx };
92029202 SDValue pair = IsReplace
92039203 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
9204 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
9204 : DAG.getMergeValues(Ops, DL);
92059205 return std::make_pair(pair, SDValue());
92069206 }
92079207 }
1128011280 SDLoc(Node));
1128111281
1128211282 SDValue Ops[2] = { Tmp1, Tmp2 };
11283 return DAG.getMergeValues(Ops, 2, dl);
11283 return DAG.getMergeValues(Ops, dl);
1128411284 }
1128511285
1128611286 // Get the inputs.
1131411314 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
1131511315 DAG.getRegister(Vreg, SPTy));
1131611316 SDValue Ops1[2] = { Value, Chain };
11317 return DAG.getMergeValues(Ops1, 2, dl);
11317 return DAG.getMergeValues(Ops1, dl);
1131811318 } else {
1131911319 SDValue Flag;
1132011320 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
1133811338 }
1133911339
1134011340 SDValue Ops1[2] = { SP, Chain };
11341 return DAG.getMergeValues(Ops1, 2, dl);
11341 return DAG.getMergeValues(Ops1, dl);
1134211342 }
1134311343 }
1134411344
1230512305 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
1230612306 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
1230712307 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12308 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12308 return DAG.getMergeValues(RetOps, dl);
1230912309 }
1231012310
1231112311 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
1232712327 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
1232812328 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
1232912329 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12330 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12330 return DAG.getMergeValues(RetOps, dl);
1233112331 }
1233212332
1233312333 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
1242612426 SDLoc DL(Op);
1242712427 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
1242812428 Results);
12429 return DAG.getMergeValues(&Results[0], Results.size(), DL);
12429 return DAG.getMergeValues(Results, DL);
1243012430 }
1243112431
1243212432 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
1261712617 }
1261812618 SmallVector Results;
1261912619 getReadTimeStampCounter(Op.getNode(), dl, Opc, DAG, Subtarget, Results);
12620 return DAG.getMergeValues(&Results[0], Results.size(), dl);
12620 return DAG.getMergeValues(Results, dl);
1262112621 }
1262212622 // XTEST intrinsics.
1262312623 case Intrinsic::x86_xtest: {
427427 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
428428 High.getValue(1));
429429 SDValue Ops[] = { Result, Chain };
430 return DAG.getMergeValues(Ops, 2, DL);
430 return DAG.getMergeValues(Ops, DL);
431431 }
432432
433433 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
493493 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
494494 High.getValue(1));
495495 SDValue Ops[] = { Result, Chain };
496 return DAG.getMergeValues(Ops, 2, DL);
496 return DAG.getMergeValues(Ops, DL);
497497 }
498498
499499 // Lower to a call to __misaligned_load(BasePtr).
515515 SDValue Ops[] =
516516 { CallResult.first, CallResult.second };
517517
518 return DAG.getMergeValues(Ops, 2, DL);
518 return DAG.getMergeValues(Ops, DL);
519519 }
520520
521521 SDValue XCoreTargetLowering::
592592 LHS, RHS);
593593 SDValue Lo(Hi.getNode(), 1);
594594 SDValue Ops[] = { Lo, Hi };
595 return DAG.getMergeValues(Ops, 2, dl);
595 return DAG.getMergeValues(Ops, dl);
596596 }
597597
598598 SDValue XCoreTargetLowering::
609609 Zero, Zero);
610610 SDValue Lo(Hi.getNode(), 1);
611611 SDValue Ops[] = { Lo, Hi };
612 return DAG.getMergeValues(Ops, 2, dl);
612 return DAG.getMergeValues(Ops, dl);
613613 }
614614
615615 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
966966 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
967967 SDValue Crc(Data.getNode(), 1);
968968 SDValue Results[] = { Crc, Data };
969 return DAG.getMergeValues(Results, 2, DL);
969 return DAG.getMergeValues(Results, DL);
970970 }
971971 return SDValue();
972972 }
16891689 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
16901690 DAG.getConstant(1, VT));
16911691 SDValue Ops[] = { Result, Carry };
1692 return DAG.getMergeValues(Ops, 2, dl);
1692 return DAG.getMergeValues(Ops, dl);
16931693 }
16941694
16951695 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
17031703 SDValue Carry = DAG.getConstant(0, VT);
17041704 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
17051705 SDValue Ops[] = { Result, Carry };
1706 return DAG.getMergeValues(Ops, 2, dl);
1706 return DAG.getMergeValues(Ops, dl);
17071707 }
17081708 }
17091709 }
17271727 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
17281728 DAG.getConstant(0, VT), N2);
17291729 SDValue Ops[] = { Result, Borrow };
1730 return DAG.getMergeValues(Ops, 2, dl);
1730 return DAG.getMergeValues(Ops, dl);
17311731 }
17321732 }
17331733
17421742 SDValue Borrow = DAG.getConstant(0, VT);
17431743 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
17441744 SDValue Ops[] = { Result, Borrow };
1745 return DAG.getMergeValues(Ops, 2, dl);
1745 return DAG.getMergeValues(Ops, dl);
17461746 }
17471747 }
17481748 }
17681768 if (N->hasNUsesOfValue(0, 0)) {
17691769 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
17701770 SDValue Ops[] = { Lo, Lo };
1771 return DAG.getMergeValues(Ops, 2, dl);
1771 return DAG.getMergeValues(Ops, dl);
17721772 }
17731773 // Otherwise fold to ladd(a, b, 0)
17741774 SDValue Result =
17751775 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
17761776 SDValue Carry(Result.getNode(), 1);
17771777 SDValue Ops[] = { Carry, Result };
1778 return DAG.getMergeValues(Ops, 2, dl);
1778 return DAG.getMergeValues(Ops, dl);
17791779 }
17801780 }
17811781 break;