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[AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h Reviewers: artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D25084 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283560 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Kolton 3 years ago
11 changed file(s) with 188 addition(s) and 64 deletion(s). Raw diff Collapse all Expand all
2222 using namespace llvm;
2323
2424 #define GET_INSTRINFO_CTOR_DTOR
25 #define GET_INSTRINFO_NAMED_OPS
2625 #define GET_INSTRMAP_INFO
2726 #include "AMDGPUGenInstrInfo.inc"
2827
1616 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
1717
1818 #include "llvm/Target/TargetInstrInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
1920
2021 #define GET_INSTRINFO_HEADER
2122 #define GET_INSTRINFO_ENUM
22 #define GET_INSTRINFO_OPERAND_ENUM
2323 #include "AMDGPUGenInstrInfo.inc"
2424
2525 namespace llvm {
5353 /// equivalent opcode that writes \p Channels Channels.
5454 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
5555 };
56
57 namespace AMDGPU {
58 LLVM_READONLY
59 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
60 } // End namespace AMDGPU
61
6256 } // End llvm namespace
6357
6458 #endif
13631363 (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
13641364 getForcedEncodingSize() != 64)
13651365 return Match_PreferE32;
1366
1367 if (Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa ||
1368 Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa) {
1369 // v_mac_f32/16 allow only dst_sel == DWORD;
1370 auto OpNum = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);
1371 const auto &Op = Inst.getOperand(OpNum);
1372 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {
1373 return Match_InvalidOperand;
1374 }
1375 }
13661376
13671377 return Match_Success;
13681378 }
26742684 }
26752685 }
26762686
2687 static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
2688 // 1. This operand is input modifiers
2689 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
2690 // 2. This is not last operand
2691 && Desc.NumOperands > (OpNum + 1)
2692 // 3. Next operand is register class
2693 && Desc.OpInfo[OpNum + 1].RegClass != -1
2694 // 4. Next register is not tied to any other operand
2695 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
2696 }
2697
26772698 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
26782699 OptionalImmIndexMap OptionalIdx;
26792700 unsigned I = 1;
26842705
26852706 for (unsigned E = Operands.size(); I != E; ++I) {
26862707 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2687 if (Desc.OpInfo[Inst.getNumOperands()].OperandType == AMDGPU::OPERAND_INPUT_MODS) {
2708 if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
26882709 Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
26892710 } else if (Op.isImm()) {
26902711 OptionalIdx[Op.getImmTy()] = I;
26952716
26962717 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
26972718 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
2719
2720 // special case v_mac_f32:
2721 // it has src2 register operand that is tied to dst operand
2722 // we don't allow modifiers for this operand in assembler so src2_modifiers
2723 // should be 0
2724 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
2725 Inst.getOpcode() == AMDGPU::V_MAC_F32_e64_vi) {
2726 auto it = Inst.begin();
2727 std::advance(it, AMDGPU::getNamedOperandIdx(AMDGPU::V_MAC_F32_e64, AMDGPU::OpName::src2_modifiers));
2728 it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2
2729 ++it;
2730 Inst.insert(it, Inst.getOperand(0)); // src2 = dst
2731 }
26982732 }
26992733
27002734 //===----------------------------------------------------------------------===//
28452879 for (unsigned E = Operands.size(); I != E; ++I) {
28462880 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
28472881 // Add the register arguments
2848 if (Desc.OpInfo[Inst.getNumOperands()].OperandType == AMDGPU::OPERAND_INPUT_MODS) {
2882 if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
28492883 Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
28502884 } else if (Op.isDPPCtrl()) {
28512885 Op.addImmOperands(Inst, 1);
28602894 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
28612895 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
28622896 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
2897
2898 // special case v_mac_f32:
2899 // it has src2 register operand that is tied to dst operand
2900 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_dpp) {
2901 auto it = Inst.begin();
2902 std::advance(it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
2903 Inst.insert(it, Inst.getOperand(0)); // src2 = dst
2904 }
28632905 }
28642906
28652907 //===----------------------------------------------------------------------===//
28692911 AMDGPUAsmParser::OperandMatchResultTy
28702912 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,
28712913 AMDGPUOperand::ImmTy Type) {
2914 using namespace llvm::AMDGPU::SDWA;
2915
28722916 SMLoc S = Parser.getTok().getLoc();
28732917 StringRef Value;
28742918 AMDGPUAsmParser::OperandMatchResultTy res;
28802924
28812925 int64_t Int;
28822926 Int = StringSwitch(Value)
2883 .Case("BYTE_0", 0)
2884 .Case("BYTE_1", 1)
2885 .Case("BYTE_2", 2)
2886 .Case("BYTE_3", 3)
2887 .Case("WORD_0", 4)
2888 .Case("WORD_1", 5)
2889 .Case("DWORD", 6)
2927 .Case("BYTE_0", SdwaSel::BYTE_0)
2928 .Case("BYTE_1", SdwaSel::BYTE_1)
2929 .Case("BYTE_2", SdwaSel::BYTE_2)
2930 .Case("BYTE_3", SdwaSel::BYTE_3)
2931 .Case("WORD_0", SdwaSel::WORD_0)
2932 .Case("WORD_1", SdwaSel::WORD_1)
2933 .Case("DWORD", SdwaSel::DWORD)
28902934 .Default(0xffffffff);
28912935 Parser.Lex(); // eat last token
28922936
29002944
29012945 AMDGPUAsmParser::OperandMatchResultTy
29022946 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
2947 using namespace llvm::AMDGPU::SDWA;
2948
29032949 SMLoc S = Parser.getTok().getLoc();
29042950 StringRef Value;
29052951 AMDGPUAsmParser::OperandMatchResultTy res;
29112957
29122958 int64_t Int;
29132959 Int = StringSwitch(Value)
2914 .Case("UNUSED_PAD", 0)
2915 .Case("UNUSED_SEXT", 1)
2916 .Case("UNUSED_PRESERVE", 2)
2960 .Case("UNUSED_PAD", DstUnused::UNUSED_PAD)
2961 .Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)
2962 .Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)
29172963 .Default(0xffffffff);
29182964 Parser.Lex(); // eat last token
29192965
29553001 Op.Reg.RegNo == AMDGPU::VCC) {
29563002 // VOPC sdwa use "vcc" token as dst. Skip it.
29573003 continue;
2958 } else if (Desc.OpInfo[Inst.getNumOperands()].OperandType == AMDGPU::OPERAND_INPUT_MODS) {
3004 } else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
29593005 Op.addRegOrImmWithInputModsOperands(Inst, 2);
29603006 } else if (Op.isImm()) {
29613007 // Handle optional arguments
29673013
29683014 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
29693015
2970 if (Inst.getOpcode() == AMDGPU::V_NOP_sdwa) {
3016 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa) {
29713017 // V_NOP_sdwa has no optional sdwa arguments
2972 return;
2973 }
2974 switch (BasicInstType) {
2975 case SIInstrFlags::VOP1: {
2976 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
2977 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
2978 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2979 break;
2980 }
2981 case SIInstrFlags::VOP2: {
2982 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
2983 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
2984 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2985 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
2986 break;
2987 }
2988 case SIInstrFlags::VOPC: {
2989 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2990 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
2991 break;
2992 }
2993 default:
2994 llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
2995 }
3018 switch (BasicInstType) {
3019 case SIInstrFlags::VOP1: {
3020 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
3021 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
3022 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
3023 break;
3024 }
3025 case SIInstrFlags::VOP2: {
3026 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
3027 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
3028 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
3029 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
3030 break;
3031 }
3032 case SIInstrFlags::VOPC: {
3033 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
3034 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
3035 break;
3036 }
3037 default:
3038 llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
3039 }
3040 }
3041
3042 // special case v_mac_f32:
3043 // it has src2 register operand that is tied to dst operand
3044 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa) {
3045 auto it = Inst.begin();
3046 std::advance(it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
3047 Inst.insert(it, Inst.getOperand(0)); // src2 = dst
3048 }
3049
29963050 }
29973051
29983052 /// Force static initialization.
530530
531531 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
532532 raw_ostream &O) {
533 using namespace llvm::AMDGPU::SDWA;
534
533535 unsigned Imm = MI->getOperand(OpNo).getImm();
534536 switch (Imm) {
535 case 0: O << "BYTE_0"; break;
536 case 1: O << "BYTE_1"; break;
537 case 2: O << "BYTE_2"; break;
538 case 3: O << "BYTE_3"; break;
539 case 4: O << "WORD_0"; break;
540 case 5: O << "WORD_1"; break;
541 case 6: O << "DWORD"; break;
537 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
538 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
539 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
540 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
541 case SdwaSel::WORD_0: O << "WORD_0"; break;
542 case SdwaSel::WORD_1: O << "WORD_1"; break;
543 case SdwaSel::DWORD: O << "DWORD"; break;
542544 default: llvm_unreachable("Invalid SDWA data select operand");
543545 }
544546 }
567569 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
568570 const MCSubtargetInfo &STI,
569571 raw_ostream &O) {
572 using namespace llvm::AMDGPU::SDWA;
573
570574 O << "dst_unused:";
571575 unsigned Imm = MI->getOperand(OpNo).getImm();
572576 switch (Imm) {
573 case 0: O << "UNUSED_PAD"; break;
574 case 1: O << "UNUSED_SEXT"; break;
575 case 2: O << "UNUSED_PRESERVE"; break;
577 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
578 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
579 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
576580 default: llvm_unreachable("Invalid SDWA dest_unused operand");
577581 }
578582 }
218218 };
219219
220220 } // namespace Hwreg
221
222 namespace SDWA {
223
224 enum SdwaSel {
225 BYTE_0 = 0,
226 BYTE_1 = 1,
227 BYTE_2 = 2,
228 BYTE_3 = 3,
229 WORD_0 = 4,
230 WORD_1 = 5,
231 DWORD = 6,
232 };
233
234 enum DstUnused {
235 UNUSED_PAD = 0,
236 UNUSED_SEXT = 1,
237 UNUSED_PRESERVE = 2,
238 };
239
240 } // namespace SDWA
221241 } // namespace AMDGPU
222242 } // namespace llvm
223243
2626 #include "AMDGPUGenRegisterInfo.inc"
2727 #undef GET_REGINFO_ENUM
2828
29 #define GET_INSTRINFO_NAMED_OPS
30 #define GET_INSTRINFO_ENUM
31 #include "AMDGPUGenInstrInfo.inc"
32 #undef GET_INSTRINFO_NAMED_OPS
33 #undef GET_INSTRINFO_ENUM
34
2935 namespace llvm {
3036 namespace AMDGPU {
3137
1212 #include "AMDKernelCodeT.h"
1313 #include "llvm/IR/CallingConv.h"
1414
15 #define GET_INSTRINFO_OPERAND_ENUM
16 #include "AMDGPUGenInstrInfo.inc"
17 #undef GET_INSTRINFO_OPERAND_ENUM
18
1519 namespace llvm {
1620
1721 class FeatureBitset;
2428 class MCSubtargetInfo;
2529
2630 namespace AMDGPU {
31
32 LLVM_READONLY
33 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
2734
2835 struct IsaVersion {
2936 unsigned Major;
164164 let AsmSDWA = getAsmSDWA<1, 2, HasModifiers, f32>.ret;
165165 let HasSrc2 = 0;
166166 let HasSrc2Mods = 0;
167 let HasExt = 1;
167168 }
168169
169170 // Write out to vcc or arbitrary SGPR.
None // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
2
31 // RUN: llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck %s --check-prefix=CI
42 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
3
4 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
55 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
66
77
240240 v_mul_i32_i24 v1, v3, s5
241241 // SICI: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x12,0xd2,0x03,0x0b,0x00,0x00]
242242 // VI: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x06,0xd1,0x03,0x0b,0x00,0x00]
243
244 v_mac_f32_e64 v0, v1, v2
245 // SICI: v_mac_f32_e64 v0, v1, v2 ; encoding: [0x00,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00]
246 // VI: v_mac_f32_e64 v0, v1, v2 ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
247
248 v_mac_f32_e64 v0, v1, v2 clamp
249 // SICI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x08,0x3e,0xd2,0x01,0x05,0x02,0x00]
250 // VI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
251
252 v_mac_f32_e64 v0, v1, v2 mul:2
253 // SICI: v_mac_f32_e64 v0, v1, v2 mul:2 ; encoding: [0x00,0x00,0x3e,0xd2,0x01,0x05,0x02,0x08]
254 // VI: v_mac_f32_e64 v0, v1, v2 mul:2 ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]
255
256 v_mac_f32_e64 v0, -v1, |v2|
257 // SICI: v_mac_f32_e64 v0, -v1, |v2| ; encoding: [0x00,0x02,0x3e,0xd2,0x01,0x05,0x02,0x20]
258 // VI: v_mac_f32_e64 v0, -v1, |v2| ; encoding: [0x00,0x02,0x16,0xd1,0x01,0x05,0x02,0x20]
243259
244260 ///===---------------------------------------------------------------------===//
245261 // VOP3 Instructions
334334 // Check VOP2 opcodes
335335 //===----------------------------------------------------------------------===//
336336 // ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp)
337 // ToDo: v_mac_f32 (VOP_MAC)
337
338 // NOSICI: error:
339 // VI: v_mac_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff]
340 v_mac_f32 v0, v0, v0 row_shl:1
341
342 // NOSICI: error:
343 // VI: v_mac_f32_dpp v0, v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x1f,0x01,0xff]
344 v_mac_f32 v0, v0, v0 row_shr:0xf
345
346 // NOSICI: error:
347 // VI: v_mac_f32_dpp v0, v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x4d,0x08,0xaf]
348 v_mac_f32 v0, v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bound_ctrl:0
338349
339350 // NOSICI: error:
340351 // VI: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
None // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
1
12 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
23 // RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
34 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
4
5 // ToDo: VOPC
5 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOVI
6
67 // ToDo: VOP2b (see vop_dpp.s)
7 // ToDo: V_MAC_F32 (see vop_dpp.s)
8 // ToDo: sext()
98 // ToDo: intrinsics
109
1110 //---------------------------------------------------------------------------//
3938 // NOSICI: error:
4039 // VI: v_min_u32_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x1c,0x01,0x06,0x00,0x06]
4140 v_min_u32 v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
41
4242 //---------------------------------------------------------------------------//
4343 // Check optional operands
4444 //---------------------------------------------------------------------------//
344344 //===----------------------------------------------------------------------===//
345345
346346 // NOSICI: error:
347 // VI: v_mac_f32_sdwa v3, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x0a,0x06,0x2c,0x04,0x16,0x05,0x06]
348 v_mac_f32 v3, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
349
350 // NOSICI: error:
351 // VI: v_mac_f32_sdwa v15, v99, v194 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:WORD_0 src1_sel:DWORD ; encoding: [0xf9,0x84,0x1f,0x2c,0x63,0x0e,0x04,0x06]
352 v_mac_f32 v15, v99, v194 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:WORD_0
353
354 // NOSICI: error:
355 // NOVI: error: invalid operand for instruction
356 v_mac_f32 v194, v13, v1 dst_sel:BYTE_0 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2
357
358 // NOSICI: error:
347359 // VI: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x02]
348360 v_add_f32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
349361