llvm.org GIT mirror llvm / a7ba3a8
Added bits of the ARM target assembler to llvm-mc to parse some load instruction operands. Some parsing of arm memory operands for preindexing and postindexing forms including with register controled shifts. This is a work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 11 years ago
1 changed file(s) with 404 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
2222 namespace {
2323 struct ARMOperand;
2424
25 // The shift types for register controlled shifts in arm memory addressing
26 enum ShiftType {
27 Lsl,
28 Lsr,
29 Asr,
30 Ror,
31 Rrx
32 };
33
2534 class ARMAsmParser : public TargetAsmParser {
2635 MCAsmParser &Parser;
2736
3443
3544 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
3645
46 bool ParseRegister(ARMOperand &Op);
47
48 bool ParseMemory(ARMOperand &Op);
49
50 bool ParseShift(enum ShiftType *St, const MCExpr *ShiftAmount);
51
52 bool ParseOperand(ARMOperand &Op);
53
3754 bool ParseDirectiveWord(unsigned Size, SMLoc L);
55
56 // TODO - For now hacked versions of the next two are in here in this file to
57 // allow some parser testing until the table gen versions are implemented.
58
59 /// @name Auto-generated Match Functions
60 /// {
61 bool MatchInstruction(SmallVectorImpl &Operands,
62 MCInst &Inst);
63
64 /// MatchRegisterName - Match the given string to a register name, or 0 if
65 /// there is no match.
66 unsigned MatchRegisterName(const StringRef &Name);
67
68 /// }
69
3870
3971 public:
4072 ARMAsmParser(const Target &T, MCAsmParser &_Parser)
4779
4880 } // end anonymous namespace
4981
82 namespace {
83
84 /// ARMOperand - Instances of this class represent a parsed ARM machine
85 /// instruction.
86 struct ARMOperand {
87 enum {
88 Token,
89 Register,
90 Memory
91 } Kind;
92
93
94 union {
95 struct {
96 const char *Data;
97 unsigned Length;
98 } Tok;
99
100 struct {
101 unsigned RegNum;
102 } Reg;
103
104 // This is for all forms of ARM address expressions
105 struct {
106 unsigned BaseRegNum;
107 bool OffsetIsReg;
108 const MCExpr *Offset; // used when OffsetIsReg is false
109 unsigned OffsetRegNum; // used when OffsetIsReg is true
110 bool OffsetRegShifted; // only used when OffsetIsReg is true
111 enum ShiftType ShiftType; // used when OffsetRegShifted is true
112 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
113 bool Preindexed;
114 bool Postindexed;
115 bool Negative; // only used when OffsetIsReg is true
116 bool Writeback;
117 } Mem;
118
119 };
120
121 StringRef getToken() const {
122 assert(Kind == Token && "Invalid access!");
123 return StringRef(Tok.Data, Tok.Length);
124 }
125
126 unsigned getReg() const {
127 assert(Kind == Register && "Invalid access!");
128 return Reg.RegNum;
129 }
130
131 bool isToken() const {return Kind == Token; }
132
133 bool isReg() const { return Kind == Register; }
134
135 void addRegOperands(MCInst &Inst, unsigned N) const {
136 assert(N == 1 && "Invalid number of operands!");
137 Inst.addOperand(MCOperand::CreateReg(getReg()));
138 }
139
140 static ARMOperand CreateToken(StringRef Str) {
141 ARMOperand Res;
142 Res.Kind = Token;
143 Res.Tok.Data = Str.data();
144 Res.Tok.Length = Str.size();
145 return Res;
146 }
147
148 static ARMOperand CreateReg(unsigned RegNum) {
149 ARMOperand Res;
150 Res.Kind = Register;
151 Res.Reg.RegNum = RegNum;
152 return Res;
153 }
154
155 static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
156 const MCExpr *Offset, unsigned OffsetRegNum,
157 bool OffsetRegShifted, enum ShiftType ShiftType,
158 const MCExpr *ShiftAmount, bool Preindexed,
159 bool Postindexed, bool Negative, bool Writeback) {
160 ARMOperand Res;
161 Res.Kind = Memory;
162 Res.Mem.BaseRegNum = BaseRegNum;
163 Res.Mem.OffsetIsReg = OffsetIsReg;
164 Res.Mem.Offset = Offset;
165 Res.Mem.OffsetRegNum = OffsetRegNum;
166 Res.Mem.OffsetRegShifted = OffsetRegShifted;
167 Res.Mem.ShiftType = ShiftType;
168 Res.Mem.ShiftAmount = ShiftAmount;
169 Res.Mem.Preindexed = Preindexed;
170 Res.Mem.Postindexed = Postindexed;
171 Res.Mem.Negative = Negative;
172 Res.Mem.Writeback = Writeback;
173 return Res;
174 }
175 };
176
177 } // end anonymous namespace.
178
179 // Try to parse a register name. The token must be an Identifier when called,
180 // and if it is a register name a Reg operand is created, the token is eaten
181 // and false is returned. Else true is returned and no token is eaten.
182 // TODO this is likely to change to allow different register types and or to
183 // parse for a specific register type.
184 bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
185 const AsmToken &Tok = getLexer().getTok();
186 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
187
188 // FIXME: Validate register for the current architecture; we have to do
189 // validation later, so maybe there is no need for this here.
190 unsigned RegNum;
191
192 RegNum = MatchRegisterName(Tok.getString());
193 if (RegNum == 0)
194 return true;
195
196 Op = ARMOperand::CreateReg(RegNum);
197 getLexer().Lex(); // Eat identifier token.
198
199 return false;
200 }
201
202 // Try to parse an arm memory expression. It must start with a '[' token.
203 // TODO Only preindexing and postindexing addressing are started, unindexed
204 // with option, etc are still to do.
205 bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
206 const AsmToken &LBracTok = getLexer().getTok();
207 assert(LBracTok.is(AsmToken::LBrac) && "Token is not an Left Bracket");
208 getLexer().Lex(); // Eat left bracket token.
209
210 const AsmToken &BaseRegTok = getLexer().getTok();
211 if (BaseRegTok.isNot(AsmToken::Identifier))
212 return Error(BaseRegTok.getLoc(), "register expected");
213 unsigned BaseRegNum = MatchRegisterName(BaseRegTok.getString());
214 if (BaseRegNum == 0)
215 return Error(BaseRegTok.getLoc(), "register expected");
216 getLexer().Lex(); // Eat identifier token.
217
218 bool Preindexed = false;
219 bool Postindexed = false;
220 bool OffsetIsReg = false;
221 bool Negative = false;
222 bool Writeback = false;
223
224 // First look for preindexed address forms:
225 // [Rn, +/-Rm]
226 // [Rn, #offset]
227 // [Rn, +/-Rm, shift]
228 // that is after the "[Rn" we now have see if the next token is a comma.
229 const AsmToken &Tok = getLexer().getTok();
230 if (Tok.is(AsmToken::Comma)) {
231 Preindexed = true;
232 getLexer().Lex(); // Eat comma token.
233
234 const AsmToken &NextTok = getLexer().getTok();
235 if (NextTok.is(AsmToken::Plus))
236 getLexer().Lex(); // Eat plus token.
237 else if (NextTok.is(AsmToken::Minus)) {
238 Negative = true;
239 getLexer().Lex(); // Eat minus token
240 }
241
242 // See if there is a register following the "[Rn," we have so far.
243 const AsmToken &OffsetRegTok = getLexer().getTok();
244 unsigned OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
245 bool OffsetRegShifted = false;
246 enum ShiftType ShiftType;
247 const MCExpr *ShiftAmount;
248 const MCExpr *Offset;
249 if (OffsetRegNum != 0) {
250 OffsetIsReg = true;
251 getLexer().Lex(); // Eat identifier token for the offset register.
252 // Look for a comma then a shift
253 const AsmToken &Tok = getLexer().getTok();
254 if (Tok.is(AsmToken::Comma)) {
255 getLexer().Lex(); // Eat comma token.
256
257 const AsmToken &Tok = getLexer().getTok();
258 if (ParseShift(&ShiftType, ShiftAmount))
259 return Error(Tok.getLoc(), "shift expected");
260 OffsetRegShifted = true;
261 }
262 }
263 else { // "[Rn," we have so far was not followed by "Rm"
264 // Look for #offset following the "[Rn,"
265 const AsmToken &HashTok = getLexer().getTok();
266 if (HashTok.isNot(AsmToken::Hash))
267 return Error(HashTok.getLoc(), "'#' expected");
268 getLexer().Lex(); // Eat hash token.
269
270 if (getParser().ParseExpression(Offset))
271 return true;
272 }
273 const AsmToken &RBracTok = getLexer().getTok();
274 if (RBracTok.isNot(AsmToken::RBrac))
275 return Error(RBracTok.getLoc(), "']' expected");
276 getLexer().Lex(); // Eat right bracket token.
277
278 const AsmToken &ExclaimTok = getLexer().getTok();
279 if (ExclaimTok.is(AsmToken::Exclaim)) {
280 Writeback = true;
281 getLexer().Lex(); // Eat exclaim token
282 }
283 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
284 OffsetRegShifted, ShiftType, ShiftAmount,
285 Preindexed, Postindexed, Negative, Writeback);
286 return false;
287 }
288 // The "[Rn" we have so far was not followed by a comma.
289 else if (Tok.is(AsmToken::RBrac)) {
290 // This is a post indexing addressing forms:
291 // [Rn], #offset
292 // [Rn], +/-Rm
293 // [Rn], +/-Rm, shift
294 // that is a ']' follows after the "[Rn".
295 Postindexed = true;
296 Writeback = true;
297 getLexer().Lex(); // Eat right bracket token.
298
299 const AsmToken &CommaTok = getLexer().getTok();
300 if (CommaTok.isNot(AsmToken::Comma))
301 return Error(CommaTok.getLoc(), "',' expected");
302 getLexer().Lex(); // Eat comma token.
303
304 const AsmToken &NextTok = getLexer().getTok();
305 if (NextTok.is(AsmToken::Plus))
306 getLexer().Lex(); // Eat plus token.
307 else if (NextTok.is(AsmToken::Minus)) {
308 Negative = true;
309 getLexer().Lex(); // Eat minus token
310 }
311
312 // See if there is a register following the "[Rn]," we have so far.
313 const AsmToken &OffsetRegTok = getLexer().getTok();
314 unsigned OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
315 bool OffsetRegShifted = false;
316 enum ShiftType ShiftType;
317 const MCExpr *ShiftAmount;
318 const MCExpr *Offset;
319 if (OffsetRegNum != 0) {
320 OffsetIsReg = true;
321 getLexer().Lex(); // Eat identifier token for the offset register.
322 // Look for a comma then a shift
323 const AsmToken &Tok = getLexer().getTok();
324 if (Tok.is(AsmToken::Comma)) {
325 getLexer().Lex(); // Eat comma token.
326
327 const AsmToken &Tok = getLexer().getTok();
328 if (ParseShift(&ShiftType, ShiftAmount))
329 return Error(Tok.getLoc(), "shift expected");
330 OffsetRegShifted = true;
331 }
332 }
333 else { // "[Rn]," we have so far was not followed by "Rm"
334 // Look for #offset following the "[Rn],"
335 const AsmToken &HashTok = getLexer().getTok();
336 if (HashTok.isNot(AsmToken::Hash))
337 return Error(HashTok.getLoc(), "'#' expected");
338 getLexer().Lex(); // Eat hash token.
339
340 if (getParser().ParseExpression(Offset))
341 return true;
342 }
343 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
344 OffsetRegShifted, ShiftType, ShiftAmount,
345 Preindexed, Postindexed, Negative, Writeback);
346 return false;
347 }
348
349 return true;
350 }
351
352 /// ParseShift as one of these two:
353 /// ( lsl | lsr | asr | ror ) , # shift_amount
354 /// rrx
355 /// and returns true if it parses a shift otherwise it returns false.
356 bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *ShiftAmount) {
357 const AsmToken &Tok = getLexer().getTok();
358 if (Tok.isNot(AsmToken::Identifier))
359 return true;
360 const StringRef &ShiftName = Tok.getString();
361 if (ShiftName == "lsl" || ShiftName == "LSL")
362 *St = Lsl;
363 else if (ShiftName == "lsr" || ShiftName == "LSR")
364 *St = Lsr;
365 else if (ShiftName == "asr" || ShiftName == "ASR")
366 *St = Asr;
367 else if (ShiftName == "ror" || ShiftName == "ROR")
368 *St = Ror;
369 else if (ShiftName == "rrx" || ShiftName == "RRX")
370 *St = Rrx;
371 else
372 return true;
373 getLexer().Lex(); // Eat shift type token.
374
375 // For all but a Rotate right there must be a '#' and a shift amount
376 if (*St != Rrx) {
377 // Look for # following the shift type
378 const AsmToken &HashTok = getLexer().getTok();
379 if (HashTok.isNot(AsmToken::Hash))
380 return Error(HashTok.getLoc(), "'#' expected");
381 getLexer().Lex(); // Eat hash token.
382
383 if (getParser().ParseExpression(ShiftAmount))
384 return true;
385 }
386
387 return false;
388 }
389
390 // A hack to allow some testing
391 unsigned ARMAsmParser::MatchRegisterName(const StringRef &Name) {
392 if (Name == "r1")
393 return 1;
394 else if (Name == "r2")
395 return 2;
396 else if (Name == "r3")
397 return 3;
398 return 0;
399 }
400
401 // A hack to allow some testing
402 bool ARMAsmParser::MatchInstruction(SmallVectorImpl &Operands,
403 MCInst &Inst) {
404 struct ARMOperand Op0 = Operands[0];
405 assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
406 const StringRef &Mnemonic = Op0.getToken();
407 if (Mnemonic == "add" ||
408 Mnemonic == "ldr")
409 return false;
410
411 return true;
412 }
413
414 // TODO - this is a work in progress
415 bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
416 switch (getLexer().getKind()) {
417 case AsmToken::Identifier:
418 if (!ParseRegister(Op))
419 return false;
420 // TODO parse other operands that start with an identifier
421 return true;
422 case AsmToken::LBrac:
423 if (!ParseMemory(Op))
424 return false;
425 default:
426 return true;
427 }
428 }
429
50430 bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
431 SmallVector Operands;
432
433 Operands.push_back(ARMOperand::CreateToken(Name));
434
51435 SMLoc Loc = getLexer().getTok().getLoc();
52 Error(Loc, "ARMAsmParser::ParseInstruction currently unimplemented");
436 if (getLexer().isNot(AsmToken::EndOfStatement)) {
437
438 // Read the first operand.
439 Operands.push_back(ARMOperand());
440 if (ParseOperand(Operands.back()))
441 return true;
442
443 while (getLexer().is(AsmToken::Comma)) {
444 getLexer().Lex(); // Eat the comma.
445
446 // Parse and remember the operand.
447 Operands.push_back(ARMOperand());
448 if (ParseOperand(Operands.back()))
449 return true;
450 }
451 }
452 if (!MatchInstruction(Operands, Inst))
453 return false;
454
455 Error(Loc, "ARMAsmParser::ParseInstruction only partly implemented");
53456 return true;
54457 }
55458