llvm.org GIT mirror llvm / a703f67
[Mips64] Add support for MCJIT for MIPS64r2 and MIPS64r6 Add support for resolving MIPS64r2 and MIPS64r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D9667 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238424 91177308-0d34-0410-b5e6-96231b3b80d8 Petar Jovanovic 5 years ago
32 changed file(s) with 469 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
148148 // Save information about our target
149149 Arch = (Triple::ArchType)Obj.getArch();
150150 IsTargetLittleEndian = Obj.isLittleEndian();
151 setMipsABI(Obj);
151152
152153 // Compute the memory size required to load all sections to be loaded
153154 // and pass this information to the memory manager
688689 // and stubs for branches Thumb - ARM and ARM - Thumb.
689690 writeBytesUnaligned(0xe51ff004, Addr, 4); // ldr pc,
690691 return Addr + 4;
691 } else if (Arch == Triple::mipsel || Arch == Triple::mips) {
692 } else if (IsMipsO32ABI) {
692693 // 0: 3c190000 lui t9,%hi(addr).
693694 // 4: 27390000 addiu t9,t9,%lo(addr).
694695 // 8: 03200008 jr t9.
504504 *TargetPtr = ((*TargetPtr) & 0xffff0000) | (Value & 0xffff);
505505 break;
506506 }
507 }
508
509 void RuntimeDyldELF::setMipsABI(const ObjectFile &Obj) {
510 if (!StringRef(Triple::getArchTypePrefix(Arch)).equals("mips")) {
511 IsMipsO32ABI = false;
512 IsMipsN64ABI = false;
513 return;
514 }
515 unsigned AbiVariant;
516 Obj.getPlatformFlags(AbiVariant);
517 IsMipsO32ABI = AbiVariant & ELF::EF_MIPS_ABI_O32;
518 IsMipsN64ABI = Obj.getFileFormatName().equals("ELF64-mips");
519 if (AbiVariant & ELF::EF_MIPS_ABI2)
520 llvm_unreachable("Mips N32 ABI is not supported yet");
521 }
522
523 void RuntimeDyldELF::resolveMIPS64Relocation(const SectionEntry &Section,
524 uint64_t Offset, uint64_t Value,
525 uint32_t Type, int64_t Addend,
526 uint64_t SymOffset,
527 SID SectionID) {
528 uint32_t r_type = Type & 0xff;
529 uint32_t r_type2 = (Type >> 8) & 0xff;
530 uint32_t r_type3 = (Type >> 16) & 0xff;
531
532 // RelType is used to keep information for which relocation type we are
533 // applying relocation.
534 uint32_t RelType = r_type;
535 int64_t CalculatedValue = evaluateMIPS64Relocation(Section, Offset, Value,
536 RelType, Addend,
537 SymOffset, SectionID);
538 if (r_type2 != ELF::R_MIPS_NONE) {
539 RelType = r_type2;
540 CalculatedValue = evaluateMIPS64Relocation(Section, Offset, 0, RelType,
541 CalculatedValue, SymOffset,
542 SectionID);
543 }
544 if (r_type3 != ELF::R_MIPS_NONE) {
545 RelType = r_type3;
546 CalculatedValue = evaluateMIPS64Relocation(Section, Offset, 0, RelType,
547 CalculatedValue, SymOffset,
548 SectionID);
549 }
550 applyMIPS64Relocation(Section.Address + Offset, CalculatedValue, RelType);
551 }
552
553 int64_t
554 RuntimeDyldELF::evaluateMIPS64Relocation(const SectionEntry &Section,
555 uint64_t Offset, uint64_t Value,
556 uint32_t Type, int64_t Addend,
557 uint64_t SymOffset, SID SectionID) {
558
559 DEBUG(dbgs() << "evaluateMIPS64Relocation, LocalAddress: 0x"
560 << format("%llx", Section.Address + Offset)
561 << " FinalAddress: 0x"
562 << format("%llx", Section.LoadAddress + Offset)
563 << " Value: 0x" << format("%llx", Value) << " Type: 0x"
564 << format("%x", Type) << " Addend: 0x" << format("%llx", Addend)
565 << " SymOffset: " << format("%x", SymOffset)
566 << "\n");
567
568 switch (Type) {
569 default:
570 llvm_unreachable("Not implemented relocation type!");
571 break;
572 case ELF::R_MIPS_JALR:
573 case ELF::R_MIPS_NONE:
574 break;
575 case ELF::R_MIPS_32:
576 case ELF::R_MIPS_64:
577 return Value + Addend;
578 case ELF::R_MIPS_26:
579 return ((Value + Addend) >> 2) & 0x3ffffff;
580 case ELF::R_MIPS_GPREL16: {
581 uint64_t GOTAddr = getSectionLoadAddress(SectionToGOTMap[SectionID]);
582 return Value + Addend - (GOTAddr + 0x7ff0);
583 }
584 case ELF::R_MIPS_SUB:
585 return Value - Addend;
586 case ELF::R_MIPS_HI16:
587 // Get the higher 16-bits. Also add 1 if bit 15 is 1.
588 return ((Value + Addend + 0x8000) >> 16) & 0xffff;
589 case ELF::R_MIPS_LO16:
590 return (Value + Addend) & 0xffff;
591 case ELF::R_MIPS_CALL16:
592 case ELF::R_MIPS_GOT_DISP:
593 case ELF::R_MIPS_GOT_PAGE: {
594 uint8_t *LocalGOTAddr =
595 getSectionAddress(SectionToGOTMap[SectionID]) + SymOffset;
596 uint64_t GOTEntry = readBytesUnaligned(LocalGOTAddr, 8);
597
598 Value += Addend;
599 if (Type == ELF::R_MIPS_GOT_PAGE)
600 Value = (Value + 0x8000) & ~0xffff;
601
602 if (GOTEntry)
603 assert(GOTEntry == Value &&
604 "GOT entry has two different addresses.");
605 else
606 writeBytesUnaligned(Value, LocalGOTAddr, 8);
607
608 return (SymOffset - 0x7ff0) & 0xffff;
609 }
610 case ELF::R_MIPS_GOT_OFST: {
611 int64_t page = (Value + Addend + 0x8000) & ~0xffff;
612 return (Value + Addend - page) & 0xffff;
613 }
614 case ELF::R_MIPS_GPREL32: {
615 uint64_t GOTAddr = getSectionLoadAddress(SectionToGOTMap[SectionID]);
616 return Value + Addend - (GOTAddr + 0x7ff0);
617 }
618 case ELF::R_MIPS_PC16: {
619 uint64_t FinalAddress = (Section.LoadAddress + Offset);
620 return ((Value + Addend - FinalAddress - 4) >> 2) & 0xffff;
621 }
622 case ELF::R_MIPS_PC18_S3: {
623 uint64_t FinalAddress = (Section.LoadAddress + Offset);
624 return ((Value + Addend - ((FinalAddress | 7) ^ 7)) >> 3) & 0x3ffff;
625 }
626 case ELF::R_MIPS_PC19_S2: {
627 uint64_t FinalAddress = (Section.LoadAddress + Offset);
628 return ((Value + Addend - FinalAddress) >> 2) & 0x7ffff;
629 }
630 case ELF::R_MIPS_PC21_S2: {
631 uint64_t FinalAddress = (Section.LoadAddress + Offset);
632 return ((Value + Addend - FinalAddress) >> 2) & 0x1fffff;
633 }
634 case ELF::R_MIPS_PC26_S2: {
635 uint64_t FinalAddress = (Section.LoadAddress + Offset);
636 return ((Value + Addend - FinalAddress) >> 2) & 0x3ffffff;
637 }
638 case ELF::R_MIPS_PCHI16: {
639 uint64_t FinalAddress = (Section.LoadAddress + Offset);
640 return ((Value + Addend - FinalAddress + 0x8000) >> 16) & 0xffff;
641 }
642 case ELF::R_MIPS_PCLO16: {
643 uint64_t FinalAddress = (Section.LoadAddress + Offset);
644 return (Value + Addend - FinalAddress) & 0xffff;
645 }
646 }
647 return 0;
648 }
649
650 void RuntimeDyldELF::applyMIPS64Relocation(uint8_t *TargetPtr,
651 int64_t CalculatedValue,
652 uint32_t Type) {
653 uint32_t Insn = readBytesUnaligned(TargetPtr, 4);
654
655 switch (Type) {
656 default:
657 break;
658 case ELF::R_MIPS_32:
659 case ELF::R_MIPS_GPREL32:
660 writeBytesUnaligned(CalculatedValue & 0xffffffff, TargetPtr, 4);
661 break;
662 case ELF::R_MIPS_64:
663 case ELF::R_MIPS_SUB:
664 writeBytesUnaligned(CalculatedValue, TargetPtr, 8);
665 break;
666 case ELF::R_MIPS_26:
667 case ELF::R_MIPS_PC26_S2:
668 Insn = (Insn & 0xfc000000) | CalculatedValue;
669 writeBytesUnaligned(Insn, TargetPtr, 4);
670 break;
671 case ELF::R_MIPS_GPREL16:
672 Insn = (Insn & 0xffff0000) | (CalculatedValue & 0xffff);
673 writeBytesUnaligned(Insn, TargetPtr, 4);
674 break;
675 case ELF::R_MIPS_HI16:
676 case ELF::R_MIPS_LO16:
677 case ELF::R_MIPS_PCHI16:
678 case ELF::R_MIPS_PCLO16:
679 case ELF::R_MIPS_PC16:
680 case ELF::R_MIPS_CALL16:
681 case ELF::R_MIPS_GOT_DISP:
682 case ELF::R_MIPS_GOT_PAGE:
683 case ELF::R_MIPS_GOT_OFST:
684 Insn = (Insn & 0xffff0000) | CalculatedValue;
685 writeBytesUnaligned(Insn, TargetPtr, 4);
686 break;
687 case ELF::R_MIPS_PC18_S3:
688 Insn = (Insn & 0xfffc0000) | CalculatedValue;
689 writeBytesUnaligned(Insn, TargetPtr, 4);
690 break;
691 case ELF::R_MIPS_PC19_S2:
692 Insn = (Insn & 0xfff80000) | CalculatedValue;
693 writeBytesUnaligned(Insn, TargetPtr, 4);
694 break;
695 case ELF::R_MIPS_PC21_S2:
696 Insn = (Insn & 0xffe00000) | CalculatedValue;
697 writeBytesUnaligned(Insn, TargetPtr, 4);
698 break;
699 }
507700 }
508701
509702 // Return the .TOC. section and offset.
783976 uint64_t Value) {
784977 const SectionEntry &Section = Sections[RE.SectionID];
785978 return resolveRelocation(Section, RE.Offset, Value, RE.RelType, RE.Addend,
786 RE.SymOffset);
979 RE.SymOffset, RE.SectionID);
787980 }
788981
789982 void RuntimeDyldELF::resolveRelocation(const SectionEntry &Section,
790983 uint64_t Offset, uint64_t Value,
791984 uint32_t Type, int64_t Addend,
792 uint64_t SymOffset) {
985 uint64_t SymOffset, SID SectionID) {
793986 switch (Arch) {
794987 case Triple::x86_64:
795988 resolveX86_64Relocation(Section, Offset, Value, Type, Addend, SymOffset);
8111004 break;
8121005 case Triple::mips: // Fall through.
8131006 case Triple::mipsel:
814 resolveMIPSRelocation(Section, Offset, (uint32_t)(Value & 0xffffffffL),
815 Type, (uint32_t)(Addend & 0xffffffffL));
1007 case Triple::mips64:
1008 case Triple::mips64el:
1009 if (IsMipsO32ABI)
1010 resolveMIPSRelocation(Section, Offset, (uint32_t)(Value & 0xffffffffL),
1011 Type, (uint32_t)(Addend & 0xffffffffL));
1012 else if (IsMipsN64ABI)
1013 resolveMIPS64Relocation(Section, Offset, Value, Type, Addend, SymOffset,
1014 SectionID);
1015 else
1016 llvm_unreachable("Mips ABI not handled");
8161017 break;
8171018 case Triple::ppc64: // Fall through.
8181019 case Triple::ppc64le:
9981199 }
9991200 processSimpleRelocation(SectionID, Offset, RelType, Value);
10001201 }
1001 } else if ((Arch == Triple::mipsel || Arch == Triple::mips)) {
1202 } else if (IsMipsO32ABI) {
10021203 uint32_t *Placeholder = reinterpret_cast(computePlaceholderAddress(SectionID, Offset));
10031204 if (RelType == ELF::R_MIPS_26) {
10041205 // This is an Mips branch relocation, need to use a stub function.
10531254 Value.Addend += *Placeholder;
10541255 processSimpleRelocation(SectionID, Offset, RelType, Value);
10551256 }
1257 } else if (IsMipsN64ABI) {
1258 uint32_t r_type = RelType & 0xff;
1259 RelocationEntry RE(SectionID, Offset, RelType, Value.Addend);
1260 if (r_type == ELF::R_MIPS_CALL16 || r_type == ELF::R_MIPS_GOT_PAGE
1261 || r_type == ELF::R_MIPS_GOT_DISP) {
1262 StringMap::iterator i = GOTSymbolOffsets.find(TargetName);
1263 if (i != GOTSymbolOffsets.end())
1264 RE.SymOffset = i->second;
1265 else {
1266 RE.SymOffset = allocateGOTEntries(SectionID, 1);
1267 GOTSymbolOffsets[TargetName] = RE.SymOffset;
1268 }
1269 }
1270 if (Value.SymbolName)
1271 addRelocationForSymbol(RE, Value.SymbolName);
1272 else
1273 addRelocationForSection(RE, Value.SectionID);
10561274 } else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le) {
10571275 if (RelType == ELF::R_PPC64_REL24) {
10581276 // Determine ABI variant in use for this object.
13551573 case Triple::x86:
13561574 case Triple::arm:
13571575 case Triple::thumb:
1576 Result = sizeof(uint32_t);
1577 break;
13581578 case Triple::mips:
13591579 case Triple::mipsel:
1360 Result = sizeof(uint32_t);
1580 case Triple::mips64:
1581 case Triple::mips64el:
1582 if (IsMipsO32ABI)
1583 Result = sizeof(uint32_t);
1584 else if (IsMipsN64ABI)
1585 Result = sizeof(uint64_t);
1586 else
1587 llvm_unreachable("Mips ABI not handled");
13611588 break;
13621589 default:
13631590 llvm_unreachable("Unsupported CPU type!");
14121639 // For now, initialize all GOT entries to zero. We'll fill them in as
14131640 // needed when GOT-based relocations are applied.
14141641 memset(Addr, 0, TotalSize);
1642 if (IsMipsN64ABI) {
1643 // To correctly resolve Mips GOT relocations, we need a mapping from
1644 // object's sections to GOTs.
1645 for (section_iterator SI = Obj.section_begin(), SE = Obj.section_end();
1646 SI != SE; ++SI) {
1647 if (SI->relocation_begin() != SI->relocation_end()) {
1648 section_iterator RelocatedSection = SI->getRelocatedSection();
1649 ObjSectionToIDMap::iterator i = SectionMap.find(*RelocatedSection);
1650 assert (i != SectionMap.end());
1651 SectionToGOTMap[i->second] = GOTSectionID;
1652 }
1653 }
1654 GOTSymbolOffsets.clear();
1655 }
14151656 }
14161657
14171658 // Look for and record the EH frame section.
2424
2525 void resolveRelocation(const SectionEntry &Section, uint64_t Offset,
2626 uint64_t Value, uint32_t Type, int64_t Addend,
27 uint64_t SymOffset = 0);
27 uint64_t SymOffset = 0, SID SectionID = 0);
2828
2929 void resolveX86_64Relocation(const SectionEntry &Section, uint64_t Offset,
3030 uint64_t Value, uint32_t Type, int64_t Addend,
4848 void resolveSystemZRelocation(const SectionEntry &Section, uint64_t Offset,
4949 uint64_t Value, uint32_t Type, int64_t Addend);
5050
51 void resolveMIPS64Relocation(const SectionEntry &Section, uint64_t Offset,
52 uint64_t Value, uint32_t Type, int64_t Addend,
53 uint64_t SymOffset, SID SectionID);
54
55 int64_t evaluateMIPS64Relocation(const SectionEntry &Section,
56 uint64_t Offset, uint64_t Value,
57 uint32_t Type, int64_t Addend,
58 uint64_t SymOffset, SID SectionID);
59
60 void applyMIPS64Relocation(uint8_t *TargetPtr, int64_t CalculatedValue,
61 uint32_t Type);
62
5163 unsigned getMaxStubSize() override {
5264 if (Arch == Triple::aarch64 || Arch == Triple::aarch64_be)
5365 return 20; // movz; movk; movk; movk; br
5466 if (Arch == Triple::arm || Arch == Triple::thumb)
5567 return 8; // 32-bit instruction and 32-bit address
56 else if (Arch == Triple::mipsel || Arch == Triple::mips)
68 else if (IsMipsO32ABI)
5769 return 16;
5870 else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le)
5971 return 44;
7183 else
7284 return 1;
7385 }
86
87 void setMipsABI(const ObjectFile &Obj) override;
7488
7589 void findPPC64TOCSection(const ObjectFile &Obj,
7690 ObjSectionToIDMap &LocalSections,
113127 // that consume more than one slot)
114128 unsigned CurrentGOTIndex;
115129
130 // A map from section to a GOT section that has entries for section's GOT
131 // relocations. (Mips64 specific)
132 DenseMap SectionToGOTMap;
133
134 // A map to avoid duplicate got entries (Mips64 specific)
135 StringMap GOTSymbolOffsets;
136
116137 // When a module is loaded we save the SectionID of the EH frame section
117138 // in a table until we receive a request to register all unregistered
118139 // EH frame sections with the memory manager.
235235
236236 Triple::ArchType Arch;
237237 bool IsTargetLittleEndian;
238 bool IsMipsO32ABI;
239 bool IsMipsN64ABI;
238240
239241 // True if all sections should be passed to the memory manager, false if only
240242 // sections containing relocations should be. Defaults to 'false'.
302304 *(Addr + 7) = Value & 0xFF;
303305 }
304306
307 virtual void setMipsABI(const ObjectFile &Obj) {
308 IsMipsO32ABI = false;
309 IsMipsN64ABI = false;
310 }
311
305312 /// Endian-aware read Read the least significant Size bytes from Src.
306313 uint64_t readBytesUnaligned(uint8_t *Src, unsigned Size) const;
307314
2222 /*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel");
2323
2424 RegisterTarget
25 /*HasJIT=*/false> A(TheMips64Target, "mips64", "Mips64 [experimental]");
25 /*HasJIT=*/true> A(TheMips64Target, "mips64", "Mips64 [experimental]");
2626
2727 RegisterTarget
28 /*HasJIT=*/false> B(TheMips64elTarget,
28 /*HasJIT=*/true> B(TheMips64elTarget,
2929 "mips64el", "Mips64el [experimental]");
3030 }
0 ; RUN: %lli -extra-module=%p/Inputs/cross-module-b.ll -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386
1 ; XFAIL: mips-, mipsel-, i686, i386
22
33 declare i32 @FB()
44
0 ; RUN: %lli -relocation-model=pic -code-model=large %s
1 ; XFAIL: cygwin, win32, mingw, mips, i686, i386, aarch64, arm, asan, msan
1 ; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, aarch64, arm, asan, msan
22 declare i8* @__cxa_allocate_exception(i64)
33 declare void @__cxa_throw(i8*, i8*, i8*)
44 declare i32 @__gxx_personality_v0(...)
0 ; RUN: %lli -relocation-model=pic -code-model=small %s
1 ; XFAIL: cygwin, win32, mingw, mips, i686, i386, darwin, aarch64, arm, asan, msan
1 ; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, darwin, aarch64, arm, asan, msan
22 declare i8* @__cxa_allocate_exception(i64)
33 declare void @__cxa_throw(i8*, i8*, i8*)
44 declare i32 @__gxx_personality_v0(...)
0 ; RUN: %lli -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386
1 ; XFAIL: mips-, mipsel-, i686, i386
22
33 declare i32 @FB()
44
0 ; RUN: %lli -extra-module=%p/Inputs/cross-module-b.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386, arm
1 ; XFAIL: mips-, mipsel-, i686, i386, arm
22
33 declare i32 @FB()
44
0 ; RUN: %lli -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386, arm
1 ; XFAIL: mips-, mipsel-, i686, i386, arm
22
33 declare i32 @FB()
44
0 ; RUN: %lli -remote-mcjit -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @count = global i32 1, align 4
44
0 ; RUN: %lli -remote-mcjit -O0 -relocation-model=pic -code-model=small %s
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
44 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
0 ; RUN: %lli -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
1 ; XFAIL: mips, i686, i386, aarch64, arm
1 ; XFAIL: mips-, mipsel-, i686, i386, aarch64, arm
22
33 define i32 @main() nounwind {
44 entry:
0 ; RUN: %lli -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @count = global i32 1, align 4
44
0 ; RUN: %lli -O0 -relocation-model=pic -code-model=small %s
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
44 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
0 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386
1 ; XFAIL: mips-, mipsel-, i686, i386
22
33 declare i32 @FB()
44
0 ; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=large %s
1 ; XFAIL: cygwin, win32, mingw, mips, i686, i386, aarch64, arm, asan, msan
1 ; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, aarch64, arm, asan, msan
22 declare i8* @__cxa_allocate_exception(i64)
33 declare void @__cxa_throw(i8*, i8*, i8*)
44 declare i32 @__gxx_personality_v0(...)
0 ; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=small %s
1 ; XFAIL: cygwin, win32, mingw, mips, i686, i386, darwin, aarch64, arm, asan, msan
1 ; XFAIL: cygwin, win32, mingw, mips-, mipsel-, i686, i386, darwin, aarch64, arm, asan, msan
22 declare i8* @__cxa_allocate_exception(i64)
33 declare void @__cxa_throw(i8*, i8*, i8*)
44 declare i32 @__gxx_personality_v0(...)
0 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386
1 ; XFAIL: mips-, mipsel-, i686, i386
22
33 declare i32 @FB()
44
0 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/cross-module-b.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386, arm
1 ; XFAIL: mips-, mipsel-, i686, i386, arm
22
33 declare i32 @FB()
44
0 ; RUN: %lli -jit-kind=orc-mcjit -extra-module=%p/Inputs/multi-module-b.ll -extra-module=%p/Inputs/multi-module-c.ll -disable-lazy-compilation=true -remote-mcjit -mcjit-remote-process=lli-child-target%exeext -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, i686, i386, arm
1 ; XFAIL: mips-, mipsel-, i686, i386, arm
22
33 declare i32 @FB()
44
0 ; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @count = global i32 1, align 4
44
0 ; RUN: %lli -jit-kind=orc-mcjit -remote-mcjit -O0 -relocation-model=pic -code-model=small %s
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
44 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
0 ; RUN: %lli -jit-kind=orc-mcjit -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
1 ; XFAIL: mips, i686, i386, aarch64, arm
1 ; XFAIL: mips-, mipsel-, i686, i386, aarch64, arm
22
33 define i32 @main() nounwind {
44 entry:
0 ; RUN: %lli -jit-kind=orc-mcjit -relocation-model=pic -code-model=small %s > /dev/null
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @count = global i32 1, align 4
44
0 ; RUN: %lli -jit-kind=orc-mcjit -O0 -relocation-model=pic -code-model=small %s
1 ; XFAIL: mips, aarch64, arm, i686, i386
1 ; XFAIL: mips-, mipsel-, aarch64, arm, i686, i386
22
33 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
44 @ptr = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), align 4
0 # RUN: llvm-mc -triple=mips64el-unknown-linux -relocation-model=pic -code-model=small -filetype=obj -o %T/test_ELF_Mips64N64.o %s
1 # RUN: llc -mtriple=mips64el-unknown-linux -relocation-model=pic -filetype=obj -o %T/test_ELF_ExternalFunction_Mips64N64.o %S/Inputs/ExternalFunction.ll
2 # RUN: llvm-rtdyld -triple=mips64el-unknown-linux -verify -map-section test_ELF_Mips64N64.o,.text=0x1000 -map-section test_ELF_ExternalFunction_Mips64N64.o,.text=0x10000 -check=%s %/T/test_ELF_Mips64N64.o %T/test_ELF_ExternalFunction_Mips64N64.o
3
4 .text
5 .abicalls
6 .section .mdebug.abi64,"",@progbits
7 .nan legacy
8 .file "ELF_Mips64N64_PIC_relocations.ll"
9 .text
10 .globl bar
11 .align 3
12 .type bar,@function
13 .set nomicromips
14 .set nomips16
15 .ent bar
16 bar:
17 .frame $fp,40,$ra
18 .mask 0x00000000,0
19 .fmask 0x00000000,0
20 .set noreorder
21 .set nomacro
22 .set noat
23 daddiu $sp, $sp, -40
24 sd $ra, 32($sp)
25 sd $fp, 24($sp)
26 move $fp, $sp
27 sd $4, 16($fp)
28 lb $2, 0($4)
29 sd $4, 8($fp)
30
31 # Test R_MIPS_26 relocation.
32 # rtdyld-check: decode_operand(insn1, 0)[25:0] = foo
33 insn1:
34 jal foo
35 nop
36
37 # Test R_MIPS_PC16 relocation.
38 # rtdyld-check: decode_operand(insn2, 1)[15:0] = foo - insn2
39 insn2:
40 bal foo
41 nop
42
43 move $sp, $fp
44 ld $ra, 32($sp)
45 ld $fp, 24($sp)
46 daddiu $sp, $sp, 32
47 jr $ra
48 nop
49 .set at
50 .set macro
51 .set reorder
52 .end bar
53 $func_end0:
54 .size bar, ($func_end0)-bar
55
56 .globl main
57 .align 3
58 .type main,@function
59 .set nomicromips
60 .set nomips16
61 .ent main
62 main:
63 .frame $fp,32,$ra
64 .mask 0x00000000,0
65 .fmask 0x00000000,0
66 .set noreorder
67 .set nomacro
68 .set noat
69 daddiu $sp, $sp, -32
70 sd $ra, 24($sp)
71 sd $fp, 16($sp)
72 sd $gp, 8($sp)
73 move $fp, $sp
74
75 # Check upper 16-bits of offset between the address of main function
76 # and the global offset table.
77 # rtdyld-check: decode_operand(insn3, 1)[15:0] = ((section_addr(test_ELF_Mips64N64.o, .got) + 0x7ff0) - main + 0x8000)[31:16]
78 insn3:
79 lui $1, %hi(%neg(%gp_rel(main)))
80 daddu $1, $1, $25
81
82 # Check lower 16-bits of offset between the address of main function
83 # and the global offset table.
84 # rtdyld-check: decode_operand(insn4, 2)[15:0] = ((section_addr(test_ELF_Mips64N64.o, .got) + 0x7ff0) - main)[15:0]
85 insn4:
86 daddiu $1, $1, %lo(%neg(%gp_rel(main)))
87 sw $zero, 4($fp)
88
89 # $gp register contains address of the .got section + 0x7FF0. 0x7FF0 is
90 # the offset of $gp from the beginning of the .got section. Check that we are
91 # loading address of the page pointer from correct offset. In this case
92 # the page pointer is the first entry in the .got section, so offset will be
93 # 0 - 0x7FF0.
94 # rtdyld-check: decode_operand(insn5, 2)[15:0] = 0x8010
95 #
96 # Check that the global offset table contains the page pointer.
97 # rtdyld-check: *{8}(section_addr(test_ELF_Mips64N64.o, .got)) = (_str + 0x8000) & 0xffffffffffff0000
98 insn5:
99 ld $25, %got_page(_str)($1)
100
101 # Check the offset of _str from the page pointer.
102 # rtdyld-check: decode_operand(insn6, 2)[15:0] = _str[15:0]
103 insn6:
104 daddiu $25, $25, %got_ofst(_str)
105
106 # Check that we are loading address of var from correct offset. In this case
107 # var is the second entry in the .got section, so offset will be 8 - 0x7FF0.
108 # rtdyld-check: decode_operand(insn7, 2)[15:0] = 0x8018
109 #
110 # Check that the global offset table contains the address of the var.
111 # rtdyld-check: *{8}(section_addr(test_ELF_Mips64N64.o, .got) + 8) = var
112 insn7:
113 ld $2, %got_disp(var)($1)
114 sd $25, 0($2)
115
116 # Check that we are loading address of bar from correct offset. In this case
117 # bar is the third entry in the .got section, so offset will be 16 - 0x7FF0.
118 # rtdyld-check: decode_operand(insn8, 2)[15:0] = 0x8020
119 #
120 # Check that the global offset table contains the address of the bar.
121 # rtdyld-check: *{8}(section_addr(test_ELF_Mips64N64.o, .got) + 16) = bar
122 insn8:
123 ld $2, %call16(bar)($1)
124
125 move $4, $25
126 move $gp, $1
127 move $25, $2
128 jalr $25
129 nop
130 move $sp, $fp
131 ld $gp, 8($sp)
132 ld $fp, 16($sp)
133 ld $ra, 24($sp)
134 daddiu $sp, $sp, 32
135 jr $ra
136 nop
137 .set at
138 .set macro
139 .set reorder
140 .end main
141 $func_end1:
142 .size main, ($func_end1)-main
143
144 .type _str,@object
145 .section .rodata.str1.1,"aMS",@progbits,1
146 _str:
147 .asciz "test"
148 .size _str, 5
149
150 .type var,@object
151 .comm var,8,8
152
153 .section ".note.GNU-stack","",@progbits
154 .text
0 if not 'Mips' in config.root.targets:
1 config.unsupported = True
2
126126 SupportedArchs.push_back(Triple::aarch64);
127127 SupportedArchs.push_back(Triple::arm);
128128 SupportedArchs.push_back(Triple::mips);
129 SupportedArchs.push_back(Triple::mips64);
130 SupportedArchs.push_back(Triple::mips64el);
129131 SupportedArchs.push_back(Triple::x86);
130132 SupportedArchs.push_back(Triple::x86_64);
131133
297297 SupportedArchs.push_back(Triple::arm);
298298 SupportedArchs.push_back(Triple::mips);
299299 SupportedArchs.push_back(Triple::mipsel);
300 SupportedArchs.push_back(Triple::mips64);
301 SupportedArchs.push_back(Triple::mips64el);
300302 SupportedArchs.push_back(Triple::x86);
301303 SupportedArchs.push_back(Triple::x86_64);
302304