llvm.org GIT mirror llvm / a6d6586
Lower CONCAT_VECTOR during legalization instead of matching it during isel. Add a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
3 changed file(s) with 55 addition(s) and 26 deletion(s). Raw diff Collapse all Expand all
12661266 MVT::Other, Ops, 3);
12671267 }
12681268
1269 case ISD::CONCAT_VECTORS: {
1270 MVT VT = Op.getValueType();
1271 assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
1272 "unexpected CONCAT_VECTORS");
1273 SDValue N0 = Op.getOperand(0);
1274 SDValue N1 = Op.getOperand(1);
1275 SDNode *Result =
1276 CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
1277 if (N0.getOpcode() != ISD::UNDEF)
1278 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1279 SDValue(Result, 0), N0,
1280 CurDAG->getTargetConstant(arm_dsubreg_0,
1281 MVT::i32));
1282 if (N1.getOpcode() != ISD::UNDEF)
1283 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1284 SDValue(Result, 0), N1,
1285 CurDAG->getTargetConstant(arm_dsubreg_1,
1286 MVT::i32));
1287 return Result;
1288 }
1289
12901269 case ISD::VECTOR_SHUFFLE: {
12911270 MVT VT = Op.getValueType();
12921271
23112311 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
23122312 }
23132313
2314 static SDValue LowerCONCAT_VECTORS(SDValue Op) {
2315 if (Op.getValueType().is128BitVector() && Op.getNumOperands() == 2)
2316 return Op;
2317 return SDValue();
2314 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2315 // The only time a CONCAT_VECTORS operation can have legal types is when
2316 // two 64-bit vectors are concatenated to a 128-bit vector.
2317 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2318 "unexpected CONCAT_VECTORS");
2319 DebugLoc dl = Op.getDebugLoc();
2320 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2321 SDValue Op0 = Op.getOperand(0);
2322 SDValue Op1 = Op.getOperand(1);
2323 if (Op0.getOpcode() != ISD::UNDEF)
2324 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2325 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2326 DAG.getIntPtrConstant(0));
2327 if (Op1.getOpcode() != ISD::UNDEF)
2328 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2329 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2330 DAG.getIntPtrConstant(1));
2331 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
23182332 }
23192333
23202334 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
23502364 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
23512365 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
23522366 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2353 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op);
2367 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
23542368 }
23552369 return SDValue();
23562370 }
0 ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon
1
2 define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 %tmp1 = load <8 x i8>* %A
4 %tmp2 = load <8 x i8>* %B
5 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32>
6 ret <16 x i8> %tmp3
7 }
8
9 define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
10 %tmp1 = load <4 x i16>* %A
11 %tmp2 = load <4 x i16>* %B
12 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32>
13 ret <8 x i16> %tmp3
14 }
15
16 define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
17 %tmp1 = load <2 x i32>* %A
18 %tmp2 = load <2 x i32>* %B
19 %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32>
20 ret <4 x i32> %tmp3
21 }
22
23 define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
24 %tmp1 = load <2 x float>* %A
25 %tmp2 = load <2 x float>* %B
26 %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32>
27 ret <4 x float> %tmp3
28 }
29
30 define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
31 %tmp1 = load <1 x i64>* %A
32 %tmp2 = load <1 x i64>* %B
33 %tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32>
34 ret <2 x i64> %tmp3
35 }