llvm.org GIT mirror llvm / a6aeb61
Merging r369095: ------------------------------------------------------------------------ r369095 | lewis-revill | 2019-08-16 12:28:34 +0200 (Fri, 16 Aug 2019) | 11 lines [RISCV] Lower inline asm constraint A for RISC-V This allows arguments with the constraint A to be lowered to input nodes for RISC-V, which implies a memory address stored in a register. This patch adds the minimal amount of code required to get operands with the right constraints to compile. https://reviews.llvm.org/D54296 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@369651 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg a month ago
5 changed file(s) with 49 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
243243 Constraint_m,
244244 Constraint_o,
245245 Constraint_v,
246 Constraint_A,
246247 Constraint_Q,
247248 Constraint_R,
248249 Constraint_S,
176176 case InlineAsm::Constraint_m:
177177 // We just support simple memory operands that have a single address
178178 // operand and need no special handling.
179 OutOps.push_back(Op);
180 return false;
181 case InlineAsm::Constraint_A:
179182 OutOps.push_back(Op);
180183 return false;
181184 default:
24122412 case 'J':
24132413 case 'K':
24142414 return C_Immediate;
2415 case 'A':
2416 return C_Memory;
24152417 }
24162418 }
24172419 return TargetLowering::getConstraintType(Constraint);
24392441 }
24402442
24412443 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2444 }
2445
2446 unsigned
2447 RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2448 // Currently only support length 1 constraints.
2449 if (ConstraintCode.size() == 1) {
2450 switch (ConstraintCode[0]) {
2451 case 'A':
2452 return InlineAsm::Constraint_A;
2453 default:
2454 break;
2455 }
2456 }
2457
2458 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
24422459 }
24432460
24442461 void RISCVTargetLowering::LowerAsmOperandForConstraint(
9292 const char *getTargetNodeName(unsigned Opcode) const override;
9393
9494 ConstraintType getConstraintType(StringRef Constraint) const override;
95
96 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
97
9598 std::pair
9699 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
97100 StringRef Constraint, MVT VT) const override;
149149 ret void
150150 }
151151
152 define void @constraint_A(i8* %a) nounwind {
153 ; RV32I-LABEL: constraint_A:
154 ; RV32I: # %bb.0:
155 ; RV32I-NEXT: #APP
156 ; RV32I-NEXT: sb s0, 0(a0)
157 ; RV32I-NEXT: #NO_APP
158 ; RV32I-NEXT: #APP
159 ; RV32I-NEXT: lb s1, 0(a0)
160 ; RV32I-NEXT: #NO_APP
161 ; RV32I-NEXT: ret
162 ;
163 ; RV64I-LABEL: constraint_A:
164 ; RV64I: # %bb.0:
165 ; RV64I-NEXT: #APP
166 ; RV64I-NEXT: sb s0, 0(a0)
167 ; RV64I-NEXT: #NO_APP
168 ; RV64I-NEXT: #APP
169 ; RV64I-NEXT: lb s1, 0(a0)
170 ; RV64I-NEXT: #NO_APP
171 ; RV64I-NEXT: ret
172 tail call void asm sideeffect "sb s0, $0", "*A"(i8* %a)
173 tail call void asm sideeffect "lb s1, $0", "*A"(i8* %a)
174 ret void
175 }
176
152177 define i32 @modifier_z_zero(i32 %a) nounwind {
153178 ; RV32I-LABEL: modifier_z_zero:
154179 ; RV32I: # %bb.0: