llvm.org GIT mirror llvm / a67f32a
Avoid spilling EBP / RBP twice in the prologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56675 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
3 changed file(s) with 21 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
18311831 }
18321832
18331833 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1834 MachineBasicBlock::iterator MI,
1834 MachineBasicBlock::iterator MI,
18351835 const std::vector &CSI) const {
18361836 if (CSI.empty())
18371837 return false;
18381838
1839 MachineFunction &MF = *MBB.getParent();
18391840 bool is64Bit = TM.getSubtarget().is64Bit();
1840 unsigned SlotSize = is64Bit ? 8 : 4;
1841
1842 MachineFunction &MF = *MBB.getParent();
1843 X86MachineFunctionInfo *X86FI = MF.getInfo();
1844 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1845
1841 unsigned FrameReg = is64Bit ? X86::RBP : X86::EBP;
18461842 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1843 unsigned CSSize = 0;
18471844 for (unsigned i = CSI.size(); i != 0; --i) {
18481845 unsigned Reg = CSI[i-1].getReg();
1846 if (Reg == FrameReg && RI.hasFP(MF))
1847 // It will be saved as part of the prologue.
1848 continue;
18491849 // Add the callee-saved register as live-in. It's killed at the spill.
18501850 MBB.addLiveIn(Reg);
18511851 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1852 }
1852 ++CSSize;
1853 }
1854
1855 X86MachineFunctionInfo *X86FI = MF.getInfo();
1856 unsigned SlotSize = is64Bit ? 8 : 4;
1857 X86FI->setCalleeSavedFrameSize(CSSize * SlotSize);
18531858 return true;
18541859 }
18551860
18561861 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1857 MachineBasicBlock::iterator MI,
1862 MachineBasicBlock::iterator MI,
18581863 const std::vector &CSI) const {
18591864 if (CSI.empty())
18601865 return false;
18611866
1867 MachineFunction &MF = *MBB.getParent();
18621868 bool is64Bit = TM.getSubtarget().is64Bit();
1869 unsigned FrameReg = is64Bit ? X86::RBP : X86::EBP;
18631870
18641871 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
18651872 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
18661873 unsigned Reg = CSI[i].getReg();
1874 if (Reg == FrameReg && RI.hasFP(MF))
1875 // It will be restored as part of the epilogue.
1876 continue;
18671877 BuildMI(MBB, MI, get(Opc), Reg);
18681878 }
18691879 return true;
0 ; Check that eh_return & unwind_init were properly lowered
1 ; RUN: llvm-as < %s | llc | grep %ebp | count 9
1 ; RUN: llvm-as < %s | llc | grep %ebp | count 7
22 ; RUN: llvm-as < %s | llc | grep %ecx | count 5
33
44 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
0 ; Check that eh_return & unwind_init were properly lowered
1 ; RUN: llvm-as < %s | llc | grep %rbp | count 7
1 ; RUN: llvm-as < %s | llc | grep %rbp | count 5
22 ; RUN: llvm-as < %s | llc | grep %rcx | count 3
33
44 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"