llvm.org GIT mirror llvm / a63bbbc
[NFC][PhaseOrdering] Add tests showcasing the problems of unsigned multiply overflow check While we can form the @llvm.mul.with.overflow easily, we are still left with that check that was guarding against div-by-0. And in the second case we won't even flatten the CFG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366747 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Lebedev a month ago
1 changed file(s) with 85 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt -simplifycfg -S < %s | FileCheck %s --check-prefixes=ALL,SIMPLIFYCFG
2 ; RUN: opt -instcombine -S < %s | FileCheck %s --check-prefixes=ALL,INSTCOMBINE,INSTCOMBINEONLY
3 ; RUN: opt -instcombine -simplifycfg -S < %s | FileCheck %s --check-prefixes=ALL,INSTCOMBINE,BOTH
4
5 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
6 target triple = "x86_64-pc-linux-gnu"
7
8 ; #include
9 ; #include
10 ;
11 ; using size_type = std::size_t;
12 ; bool will_not_overflow(size_type size, size_type nmemb) {
13 ; return (size != 0 && (nmemb > std::numeric_limits::max() / size));
14 ; }
15
16 define i1 @will_not_overflow(i64 %arg, i64 %arg1) {
17 ; ALL-LABEL: @will_not_overflow(
18 ; ALL-NEXT: bb:
19 ; ALL-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
20 ; ALL-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
21 ; ALL: bb2:
22 ; ALL-NEXT: [[T3:%.*]] = udiv i64 -1, [[ARG]]
23 ; ALL-NEXT: [[T4:%.*]] = icmp ult i64 [[T3]], [[ARG1:%.*]]
24 ; ALL-NEXT: br label [[BB5]]
25 ; ALL: bb5:
26 ; ALL-NEXT: [[T6:%.*]] = phi i1 [ false, [[BB:%.*]] ], [ [[T4]], [[BB2]] ]
27 ; ALL-NEXT: ret i1 [[T6]]
28 ;
29 bb:
30 %t0 = icmp eq i64 %arg, 0
31 br i1 %t0, label %bb5, label %bb2
32
33 bb2: ; preds = %bb
34 %t3 = udiv i64 -1, %arg
35 %t4 = icmp ult i64 %t3, %arg1
36 br label %bb5
37
38 bb5: ; preds = %bb2, %bb
39 %t6 = phi i1 [ false, %bb ], [ %t4, %bb2 ]
40 ret i1 %t6
41 }
42
43 ; Same as @will_not_overflow, but inverting return value.
44
45 define i1 @will_overflow(i64 %arg, i64 %arg1) {
46 ; SIMPLIFYCFG-LABEL: @will_overflow(
47 ; SIMPLIFYCFG-NEXT: bb:
48 ; SIMPLIFYCFG-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
49 ; SIMPLIFYCFG-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
50 ; SIMPLIFYCFG: bb2:
51 ; SIMPLIFYCFG-NEXT: [[T3:%.*]] = udiv i64 -1, [[ARG]]
52 ; SIMPLIFYCFG-NEXT: [[T4:%.*]] = icmp ult i64 [[T3]], [[ARG1:%.*]]
53 ; SIMPLIFYCFG-NEXT: br label [[BB5]]
54 ; SIMPLIFYCFG: bb5:
55 ; SIMPLIFYCFG-NEXT: [[T6:%.*]] = phi i1 [ false, [[BB:%.*]] ], [ [[T4]], [[BB2]] ]
56 ; SIMPLIFYCFG-NEXT: [[T7:%.*]] = xor i1 [[T6]], true
57 ; SIMPLIFYCFG-NEXT: ret i1 [[T7]]
58 ;
59 ; INSTCOMBINE-LABEL: @will_overflow(
60 ; INSTCOMBINE-NEXT: bb:
61 ; INSTCOMBINE-NEXT: [[T0:%.*]] = icmp eq i64 [[ARG:%.*]], 0
62 ; INSTCOMBINE-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
63 ; INSTCOMBINE: bb2:
64 ; INSTCOMBINE-NEXT: [[T3:%.*]] = udiv i64 -1, [[ARG]]
65 ; INSTCOMBINE-NEXT: [[T4:%.*]] = icmp uge i64 [[T3]], [[ARG1:%.*]]
66 ; INSTCOMBINE-NEXT: br label [[BB5]]
67 ; INSTCOMBINE: bb5:
68 ; INSTCOMBINE-NEXT: [[T6:%.*]] = phi i1 [ true, [[BB:%.*]] ], [ [[T4]], [[BB2]] ]
69 ; INSTCOMBINE-NEXT: ret i1 [[T6]]
70 ;
71 bb:
72 %t0 = icmp eq i64 %arg, 0
73 br i1 %t0, label %bb5, label %bb2
74
75 bb2: ; preds = %bb
76 %t3 = udiv i64 -1, %arg
77 %t4 = icmp ult i64 %t3, %arg1
78 br label %bb5
79
80 bb5: ; preds = %bb2, %bb
81 %t6 = phi i1 [ false, %bb ], [ %t4, %bb2 ]
82 %t7 = xor i1 %t6, true
83 ret i1 %t7
84 }