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Merging r312337: ------------------------------------------------------------------------ r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states Summary: This fixes a bug that was exposed on gfx9 in various GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests, e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D36193 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314324 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
2 changed file(s) with 40 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
217217
218218 int GCNHazardRecognizer::getWaitStatesSince(
219219 function_ref IsHazard) {
220 int WaitStates = -1;
220 int WaitStates = 0;
221221 for (MachineInstr *MI : EmittedInstrs) {
222 if (MI) {
223 if (IsHazard(MI))
224 return WaitStates;
225
226 unsigned Opcode = MI->getOpcode();
227 if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF)
228 continue;
229 }
222230 ++WaitStates;
223 if (!MI || !IsHazard(MI))
224 continue;
225 return WaitStates;
226231 }
227232 return std::numeric_limits::max();
228233 }
0 # RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
2
3 # GCN: bb.0.entry:
4 # GCN: %m0 = S_MOV_B32
5 # GFX9: S_NOP 0
6 # VI-NOT: S_NOP_0
7 # GCN: V_INTERP_P1_F32
8
9 ---
10 name: hazard_implicit_def
11 alignment: 0
12 exposesReturnsTwice: false
13 legalized: false
14 regBankSelected: false
15 selected: false
16 tracksRegLiveness: true
17 registers:
18 liveins:
19 - { reg: '%sgpr7', virtual-reg: '' }
20 - { reg: '%vgpr4', virtual-reg: '' }
21 body: |
22 bb.0.entry:
23 liveins: %sgpr7, %vgpr4
24
25 %m0 = S_MOV_B32 killed %sgpr7
26 %vgpr5 = IMPLICIT_DEF
27 %vgpr0 = V_INTERP_P1_F32 killed %vgpr4, 0, 0, implicit %m0, implicit %exec
28 SI_RETURN_TO_EPILOG killed %vgpr5, killed %vgpr0
29
30 ...