llvm.org GIT mirror llvm / a60ff0d
[mips][msa] Implement f16 support The MIPS MSA ASE provides instructions to convert to and from half precision floating point. This patch teaches the MIPS backend to treat f16 as a legal type and how to promote such values to f32 for the usual set of operations. As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during type legalization. Reviewers: zoran.jovanvoic, vkalintiris Differential Revision: https://reviews.llvm.org/D26398 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287349 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
4 changed file(s) with 418 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
37293729 MSA128D, NoItinerary>;
37303730 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE
37313731 MSA128B, NoItinerary>;
3732
3733 // Pseudoes used to implement transparent fp16 support.
3734
3735 let Predicates = [HasMSA] in {
3736 def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
3737 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> {
3738 let usesCustomInserter = 1;
3739 }
3740
3741 def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
3742 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> {
3743 let usesCustomInserter = 1;
3744 }
3745
3746 def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd),
3747 (ins MSA128F16:$ws),
3748 [(set FGR32Opnd:$fd,
3749 (f32 (fpextend MSA128F16:$ws)))]> {
3750 let usesCustomInserter = 1;
3751 }
3752
3753 def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
3754 (ins FGR32Opnd:$fs),
3755 [(set MSA128F16:$wd,
3756 (f16 (fpround FGR32Opnd:$fs)))]> {
3757 let usesCustomInserter = 1;
3758 }
3759
3760 def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd),
3761 (ins MSA128F16:$ws),
3762 [(set FGR64Opnd:$fd,
3763 (f64 (fpextend MSA128F16:$ws)))]> {
3764 let usesCustomInserter = 1;
3765 }
3766
3767 def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
3768 (ins FGR64Opnd:$fs),
3769 [(set MSA128F16:$wd,
3770 (f16 (fpround FGR64Opnd:$fs)))]> {
3771 let usesCustomInserter = 1;
3772 }
3773
3774 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
3775 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>;
3776
3777 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
3778 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
3779 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
3780 ISA_MIPS1_NOT_32R6_64R6;
3781 }
37323782
37333783 // Vector extraction with fixed index.
37343784 //
399399 // This class allows us to represent this in codegen patterns.
400400 def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
401401
402 def MSA128F16 : RegisterClass<"Mips", [f16], 128, (sequence "W%u", 0, 31)>;
403
402404 def MSA128B: RegisterClass<"Mips", [v16i8], 128,
403405 (sequence "W%u", 0, 31)>;
404406 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
645647 let ParserMatchClass = COP3AsmOperand;
646648 }
647649
650 def MSA128F16Opnd : RegisterOperand {
651 let ParserMatchClass = MSA128AsmOperand;
652 }
653
648654 def MSA128BOpnd : RegisterOperand {
649655 let ParserMatchClass = MSA128AsmOperand;
650656 }
9090 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
9191 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
9292 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93
94 // f16 is a storage-only type, always promote it to f32.
95 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
96 setOperationAction(ISD::SETCC, MVT::f16, Promote);
97 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
98 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
99 setOperationAction(ISD::SELECT, MVT::f16, Promote);
100 setOperationAction(ISD::FADD, MVT::f16, Promote);
101 setOperationAction(ISD::FSUB, MVT::f16, Promote);
102 setOperationAction(ISD::FMUL, MVT::f16, Promote);
103 setOperationAction(ISD::FDIV, MVT::f16, Promote);
104 setOperationAction(ISD::FREM, MVT::f16, Promote);
105 setOperationAction(ISD::FMA, MVT::f16, Promote);
106 setOperationAction(ISD::FNEG, MVT::f16, Promote);
107 setOperationAction(ISD::FABS, MVT::f16, Promote);
108 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
109 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
110 setOperationAction(ISD::FCOS, MVT::f16, Promote);
111 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
112 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
113 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
114 setOperationAction(ISD::FPOW, MVT::f16, Promote);
115 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
116 setOperationAction(ISD::FRINT, MVT::f16, Promote);
117 setOperationAction(ISD::FSIN, MVT::f16, Promote);
118 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
119 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
120 setOperationAction(ISD::FEXP, MVT::f16, Promote);
121 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
122 setOperationAction(ISD::FLOG, MVT::f16, Promote);
123 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
124 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
125 setOperationAction(ISD::FROUND, MVT::f16, Promote);
126 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
127 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
128 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
129 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
130 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
93131
94132 setTargetDAGCombine(ISD::AND);
95133 setTargetDAGCombine(ISD::OR);
11711209 return emitFEXP2_W_1(MI, BB);
11721210 case Mips::FEXP2_D_1_PSEUDO:
11731211 return emitFEXP2_D_1(MI, BB);
1212 case Mips::ST_F16:
1213 return emitST_F16_PSEUDO(MI, BB);
1214 case Mips::LD_F16:
1215 return emitLD_F16_PSEUDO(MI, BB);
1216 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1217 return emitFPEXTEND_PSEUDO(MI, BB, false);
1218 case Mips::MSA_FP_ROUND_W_PSEUDO:
1219 return emitFPROUND_PSEUDO(MI, BB, false);
1220 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1221 return emitFPEXTEND_PSEUDO(MI, BB, true);
1222 case Mips::MSA_FP_ROUND_D_PSEUDO:
1223 return emitFPROUND_PSEUDO(MI, BB, true);
11741224 }
11751225 }
11761226
33713421 return BB;
33723422 }
33733423
3424 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3425 // register.
3426 //
3427 // STF16 MSA128F16:$wd, mem_simm10:$addr
3428 // =>
3429 // copy_u.h $rtemp,$wd[0]
3430 // sh $rtemp, $addr
3431 //
3432 // Safety: We can't use st.h & co as they would over write the memory after
3433 // the destination. It would require half floats be allocated 16 bytes(!) of
3434 // space.
3435 MachineBasicBlock *
3436 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3437 MachineBasicBlock *BB) const {
3438
3439 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3440 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3441 DebugLoc DL = MI.getDebugLoc();
3442 unsigned Ws = MI.getOperand(0).getReg();
3443 unsigned Rt = MI.getOperand(1).getReg();
3444 const MachineMemOperand &MMO = **MI.memoperands_begin();
3445 unsigned Imm = MMO.getOffset();
3446
3447 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3448 // spill and reload can expand as a GPR64 operand. Examine the
3449 // operand in detail and default to ABI.
3450 const TargetRegisterClass *RC =
3451 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3452 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3453 : &Mips::GPR64RegClass);
3454 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3455 unsigned Rs = RegInfo.createVirtualRegister(RC);
3456
3457 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3458 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3459 .addReg(Rs)
3460 .addReg(Rt)
3461 .addImm(Imm)
3462 .addMemOperand(BB->getParent()->getMachineMemOperand(
3463 &MMO, MMO.getOffset(), MMO.getSize()));
3464
3465 MI.eraseFromParent();
3466 return BB;
3467 }
3468
3469 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3470 //
3471 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3472 // =>
3473 // lh $rtemp, $addr
3474 // fill.h $wd, $rtemp
3475 //
3476 // Safety: We can't use ld.h & co as they over-read from the source.
3477 // Additionally, if the address is not modulo 16, 2 cases can occur:
3478 // a) Segmentation fault as the load instruction reads from a memory page
3479 // memory it's not supposed to.
3480 // b) The load crosses an implementation specific boundary, requiring OS
3481 // intervention.
3482 //
3483 MachineBasicBlock *
3484 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3485 MachineBasicBlock *BB) const {
3486
3487 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3488 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3489 DebugLoc DL = MI.getDebugLoc();
3490 unsigned Wd = MI.getOperand(0).getReg();
3491
3492 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3493 // spill and reload can expand as a GPR64 operand. Examine the
3494 // operand in detail and default to ABI.
3495 const TargetRegisterClass *RC =
3496 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3497 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3498 : &Mips::GPR64RegClass);
3499
3500 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3501 unsigned Rt = RegInfo.createVirtualRegister(RC);
3502
3503 MachineInstrBuilder MIB =
3504 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3505 for (unsigned i = 1; i < MI.getNumOperands(); i++)
3506 MIB.addOperand(MI.getOperand(i));
3507
3508 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3509
3510 MI.eraseFromParent();
3511 return BB;
3512 }
3513
3514 // Emit the FPROUND_PSEUDO instruction.
3515 //
3516 // Round an FGR64Opnd, FGR32Opnd to an f16.
3517 //
3518 // Safety: Cycle the operand through the GPRs so the result always ends up
3519 // the correct MSA register.
3520 //
3521 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3522 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3523 // (which they can be, as the MSA registers are defined to alias the
3524 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3525 // the correct register class. That requires operands be tie-able across
3526 // register classes which have a sub/super register class relationship.
3527 //
3528 // For FPG32Opnd:
3529 //
3530 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3531 // =>
3532 // mfc1 $rtemp, $fs
3533 // fill.w $rtemp, $wtemp
3534 // fexdo.w $wd, $wtemp, $wtemp
3535 //
3536 // For FPG64Opnd on mips32r2+:
3537 //
3538 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3539 // =>
3540 // mfc1 $rtemp, $fs
3541 // fill.w $rtemp, $wtemp
3542 // mfhc1 $rtemp2, $fs
3543 // insert.w $wtemp[1], $rtemp2
3544 // insert.w $wtemp[3], $rtemp2
3545 // fexdo.w $wtemp2, $wtemp, $wtemp
3546 // fexdo.h $wd, $temp2, $temp2
3547 //
3548 // For FGR64Opnd on mips64r2+:
3549 //
3550 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3551 // =>
3552 // dmfc1 $rtemp, $fs
3553 // fill.d $rtemp, $wtemp
3554 // fexdo.w $wtemp2, $wtemp, $wtemp
3555 // fexdo.h $wd, $wtemp2, $wtemp2
3556 //
3557 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3558 // undef bits are "just right" and the exception enable bits are
3559 // set. By using fill.w to replicate $fs into all elements over
3560 // insert.w for one element, we avoid that potiential case. If
3561 // fexdo.[hw] causes an exception in, the exception is valid and it
3562 // occurs for all elements.
3563 //
3564 MachineBasicBlock *
3565 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3566 MachineBasicBlock *BB,
3567 bool IsFGR64) const {
3568
3569 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3570 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3571 // it.
3572 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3573
3574 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3575
3576 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3577 DebugLoc DL = MI.getDebugLoc();
3578 unsigned Wd = MI.getOperand(0).getReg();
3579 unsigned Fs = MI.getOperand(1).getReg();
3580
3581 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3582 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3583 const TargetRegisterClass *GPRRC =
3584 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3585 unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1;
3586 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3587
3588 // Perform the register class copy as mentioned above.
3589 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3590 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3591 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3592 unsigned WPHI = Wtemp;
3593
3594 if (!Subtarget.hasMips64() && IsFGR64) {
3595 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3596 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3597 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3598 unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3599 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3600 .addReg(Wtemp)
3601 .addReg(Rtemp2)
3602 .addImm(1);
3603 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3604 .addReg(Wtemp2)
3605 .addReg(Rtemp2)
3606 .addImm(3);
3607 WPHI = Wtemp3;
3608 }
3609
3610 if (IsFGR64) {
3611 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3612 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3613 .addReg(WPHI)
3614 .addReg(WPHI);
3615 WPHI = Wtemp2;
3616 }
3617
3618 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3619
3620 MI.eraseFromParent();
3621 return BB;
3622 }
3623
3624 // Emit the FPEXTEND_PSEUDO instruction.
3625 //
3626 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3627 //
3628 // Safety: Cycle the result through the GPRs so the result always ends up
3629 // the correct floating point register.
3630 //
3631 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3632 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3633 // (which they can be, as the MSA registers are defined to alias the
3634 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3635 // the correct register class. That requires operands be tie-able across
3636 // register classes which have a sub/super register class relationship. I
3637 // haven't checked.
3638 //
3639 // For FGR32Opnd:
3640 //
3641 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3642 // =>
3643 // fexupr.w $wtemp, $ws
3644 // copy_s.w $rtemp, $ws[0]
3645 // mtc1 $rtemp, $fd
3646 //
3647 // For FGR64Opnd on Mips64:
3648 //
3649 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3650 // =>
3651 // fexupr.w $wtemp, $ws
3652 // fexupr.d $wtemp2, $wtemp
3653 // copy_s.d $rtemp, $wtemp2s[0]
3654 // dmtc1 $rtemp, $fd
3655 //
3656 // For FGR64Opnd on Mips32:
3657 //
3658 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3659 // =>
3660 // fexupr.w $wtemp, $ws
3661 // fexupr.d $wtemp2, $wtemp
3662 // copy_s.w $rtemp, $wtemp2[0]
3663 // mtc1 $rtemp, $ftemp
3664 // copy_s.w $rtemp2, $wtemp2[1]
3665 // $fd = mthc1 $rtemp2, $ftemp
3666 //
3667 MachineBasicBlock *
3668 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3669 MachineBasicBlock *BB,
3670 bool IsFGR64) const {
3671
3672 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3673 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3674 // it.
3675 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3676
3677 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3678 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3679
3680 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3681 DebugLoc DL = MI.getDebugLoc();
3682 unsigned Fd = MI.getOperand(0).getReg();
3683 unsigned Ws = MI.getOperand(1).getReg();
3684
3685 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3686 const TargetRegisterClass *GPRRC =
3687 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3688 unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1;
3689 unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3690
3691 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3692 unsigned WPHI = Wtemp;
3693
3694 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3695 if (IsFGR64) {
3696 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3697 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3698 }
3699
3700 // Perform the safety regclass copy mentioned above.
3701 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3702 unsigned FPRPHI = IsFGR64onMips32
3703 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3704 : Fd;
3705 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3706 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3707
3708 if (IsFGR64onMips32) {
3709 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3710 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3711 .addReg(WPHI)
3712 .addImm(1);
3713 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3714 .addReg(FPRPHI)
3715 .addReg(Rtemp2);
3716 }
3717
3718 MI.eraseFromParent();
3719 return BB;
3720 }
3721
33743722 // Emit the FEXP2_W_1 pseudo instructions.
33753723 //
33763724 // fexp2_w_1_pseudo $wd, $wt
110110 /// \brief Emit the FEXP2_D_1 pseudo instructions.
111111 MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
112112 MachineBasicBlock *BB) const;
113 /// \brief Emit the FILL_FW pseudo instruction
114 MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
115 MachineBasicBlock *BB) const;
116 /// \brief Emit the FILL_FD pseudo instruction
117 MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
118 MachineBasicBlock *BB) const;
119 /// \brief Emit the FEXP2_W_1 pseudo instructions.
120 MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
121 MachineBasicBlock *BB,
122 bool IsFGR64) const;
123 /// \brief Emit the FEXP2_D_1 pseudo instructions.
124 MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
125 MachineBasicBlock *BBi,
126 bool IsFGR64) const;
113127 };
114128 }
115129