llvm.org GIT mirror llvm / a5e8c70
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751 Differential Revision: https://reviews.llvm.org/D44529 Reviewers: artem.tamazov, arsenm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327723 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 1 year, 11 months ago
7 changed file(s) with 107 addition(s) and 90 deletion(s). Raw diff Collapse all Expand all
373373 O << "_dpp ";
374374 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
375375 O << "_sdwa ";
376 else
377 O << "_e32 ";
378
379 printOperand(MI, OpNo, STI, O);
380 }
381
382 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
383 const MCSubtargetInfo &STI, raw_ostream &O) {
384 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
385 O << " ";
376386 else
377387 O << "_e32 ";
378388
9595 void printRegOperand(unsigned RegNo, raw_ostream &O);
9696 void printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
9797 raw_ostream &O);
98 void printVINTRPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
99 raw_ostream &O);
98100 void printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI,
99101 raw_ostream &O);
100102 void printImmediateV216(uint32_t Imm, const MCSubtargetInfo &STI,
19361936 // Interpolation opcodes
19371937 //===----------------------------------------------------------------------===//
19381938
1939 class VINTRPDstOperand : RegisterOperand ;
1940
19391941 class VINTRP_Pseudo pattern> :
19401942 VINTRPCommon ,
19411943 SIMCInstr {
3939 // VINTRP Instructions
4040 //===----------------------------------------------------------------------===//
4141
42 // Used to inject printing of "_e32" suffix for VI (there are "_e64" variants for VI)
43 def VINTRPDst : VINTRPDstOperand ;
44
4245 let Uses = [M0, EXEC] in {
4346
4447 // FIXME: Specify SchedRW for VINTRP insturctions.
4548
4649 multiclass V_INTERP_P1_F32_m : VINTRP_m <
4750 0x00000000,
48 (outs VGPR_32:$vdst),
51 (outs VINTRPDst:$vdst),
4952 (ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
50 "v_interp_p1_f32 $vdst, $vsrc, $attr$attrchan",
53 "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
5154 [(set f32:$vdst, (AMDGPUinterp_p1 f32:$vsrc, (i32 imm:$attrchan),
5255 (i32 imm:$attr)))]
5356 >;
6871
6972 defm V_INTERP_P2_F32 : VINTRP_m <
7073 0x00000001,
71 (outs VGPR_32:$vdst),
74 (outs VINTRPDst:$vdst),
7275 (ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
73 "v_interp_p2_f32 $vdst, $vsrc, $attr$attrchan",
76 "v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
7477 [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$vsrc, (i32 imm:$attrchan),
7578 (i32 imm:$attr)))]>;
7679
7881
7982 defm V_INTERP_MOV_F32 : VINTRP_m <
8083 0x00000002,
81 (outs VGPR_32:$vdst),
84 (outs VINTRPDst:$vdst),
8285 (ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan),
83 "v_interp_mov_f32 $vdst, $vsrc, $attr$attrchan",
86 "v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",
8487 [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 imm:$attrchan),
8588 (i32 imm:$attr)))]>;
8689
55 ; GCN-LABEL: {{^}}v_interp:
66 ; GCN-NOT: s_wqm
77 ; GCN: s_mov_b32 m0, s{{[0-9]+}}
8 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
9 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
10 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
11 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}}
8 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
9 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
10 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
11 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p0, attr0.x{{$}}
1212 define amdgpu_ps void @v_interp(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x float> %arg4) #0 {
1313 main_body:
1414 %i = extractelement <2 x float> %arg4, i32 0
2525
2626 ; GCN-LABEL: {{^}}v_interp_p1:
2727 ; GCN: s_movk_i32 m0, 0x100
28 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
29 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
30 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}}
31 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}}
32 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
33
34 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr1.x{{$}}
35 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr2.y{{$}}
36 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr3.z{{$}}
37 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr4.w{{$}}
38 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr63.w{{$}}
39 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.w{{$}}
40 ; GCN-DAG: v_interp_p1_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}}
28 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
29 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
30 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}}
31 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}}
32 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
33
34 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr1.x{{$}}
35 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr2.y{{$}}
36 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr3.z{{$}}
37 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr4.w{{$}}
38 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr63.w{{$}}
39 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.w{{$}}
40 ; GCN-DAG: v_interp_p1_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}}
4141 define amdgpu_ps void @v_interp_p1(float %i) #0 {
4242 bb:
4343 %p0_0 = call float @llvm.amdgcn.interp.p1(float %i, i32 0, i32 0, i32 256)
7070
7171 ; GCN-LABEL: {{^}}v_interp_p2:
7272 ; GCN: s_movk_i32 m0, 0x100
73 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
74 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
75 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}}
76 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}}
77 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
78 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
79 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr63.x{{$}}
80 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}}
81 ; GCN-DAG: v_interp_p2_f32 v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}}
73 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
74 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.y{{$}}
75 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.z{{$}}
76 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.w{{$}}
77 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
78 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr0.x{{$}}
79 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr63.x{{$}}
80 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}}
81 ; GCN-DAG: v_interp_p2_f32{{(_e32)*}} v{{[0-9]+}}, v{{[0-9]+}}, attr64.x{{$}}
8282 define amdgpu_ps void @v_interp_p2(float %x, float %j) #0 {
8383 bb:
8484 %p2_0 = call float @llvm.amdgcn.interp.p2(float %x, float %j, i32 0, i32 0, i32 256)
106106
107107 ; GCN-LABEL: {{^}}v_interp_mov:
108108 ; GCN: s_movk_i32 m0, 0x100
109 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.x{{$}}
110 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p20, attr0.x{{$}}
111 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}}
112 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_3, attr0.x{{$}}
113
114 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.x{{$}}
115 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.z{{$}}
116 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.w{{$}}
117 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr0.x{{$}}
118 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_8, attr0.x{{$}}
119
120 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr63.y{{$}}
121 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, p10, attr64.y{{$}}
122 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_3, attr64.y{{$}}
123 ; GCN-DAG: v_interp_mov_f32 v{{[0-9]+}}, invalid_param_10, attr64.x{{$}}
109 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.x{{$}}
110 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p20, attr0.x{{$}}
111 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p0, attr0.x{{$}}
112 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_3, attr0.x{{$}}
113
114 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.x{{$}}
115 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.z{{$}}
116 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.w{{$}}
117 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr0.x{{$}}
118 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_8, attr0.x{{$}}
119
120 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr63.y{{$}}
121 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, p10, attr64.y{{$}}
122 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_3, attr64.y{{$}}
123 ; GCN-DAG: v_interp_mov_f32{{(_e32)*}} v{{[0-9]+}}, invalid_param_10, attr64.x{{$}}
124124 define amdgpu_ps void @v_interp_mov(float %x, float %j) #0 {
125125 bb:
126126 %mov_0 = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 0, i32 256)
166166 ; TODO-VI-LABEL: v_interp_readnone:
167167 ; TODO-VI: s_mov_b32 m0, 0
168168 ; TODO-VI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
169 ; TODO-VI-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}}
169 ; TODO-VI-DAG: v_interp_mov_f32_e32 v{{[0-9]+}}, p0, attr0.x{{$}}
170170 ; TODO-VI: s_mov_b32 m0, -1{{$}}
171171 ; TODO-VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
172172 ;define amdgpu_ps void @v_interp_readnone(float addrspace(3)* %lds) #0 {
183183 ; on 16 bank LDS chips.
184184
185185 ; GCN-LABEL: {{^}}v_interp_p1_bank16_bug:
186 ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
186 ; 16BANK-NOT: v_interp_p1_f32{{(_e32)*}} [[DST:v[0-9]+]], [[DST]]
187187 define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg13, [17 x <4 x i32>] addrspace(2)* byval %arg14, [34 x <8 x i32>] addrspace(2)* byval %arg15, float inreg %arg16, i32 inreg %arg17, <2 x i32> %arg18, <2 x i32> %arg19, <2 x i32> %arg20, <3 x i32> %arg21, <2 x i32> %arg22, <2 x i32> %arg23, <2 x i32> %arg24, float %arg25, float %arg26, float %arg27, float %arg28, float %arg29, float %arg30, i32 %arg31, float %arg32, float %arg33) #0 {
188188 main_body:
189189 %i.i = extractelement <2 x i32> %arg19, i32 0
22
33 v_interp_p1_f32 v1, v0, attr0.x
44 // SI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xc8]
5 // VI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xd4]
5 // VI: v_interp_p1_f32_e32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xd4]
66
77 v_interp_p1_f32 v2, v0, attr0.y
88 // SI: v_interp_p1_f32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xc8]
9 // VI: v_interp_p1_f32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xd4]
9 // VI: v_interp_p1_f32_e32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xd4]
1010
1111 v_interp_p1_f32 v3, v0, attr0.z
1212 // SI: v_interp_p1_f32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xc8]
13 // VI: v_interp_p1_f32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xd4]
13 // VI: v_interp_p1_f32_e32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xd4]
1414
1515 v_interp_p1_f32 v4, v0, attr0.w
1616 // SI: v_interp_p1_f32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xc8]
17 // VI: v_interp_p1_f32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xd4]
17 // VI: v_interp_p1_f32_e32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xd4]
1818
1919 v_interp_p1_f32 v5, v0, attr0.x
2020 // SI: v_interp_p1_f32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xc8]
21 // VI: v_interp_p1_f32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xd4]
21 // VI: v_interp_p1_f32_e32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xd4]
2222
2323 v_interp_p1_f32 v6, v0, attr1.x
2424 // SI: v_interp_p1_f32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xc8]
25 // VI: v_interp_p1_f32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xd4]
25 // VI: v_interp_p1_f32_e32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xd4]
2626
2727 v_interp_p1_f32 v7, v0, attr2.y
2828 // SI: v_interp_p1_f32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xc8]
29 // VI: v_interp_p1_f32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xd4]
29 // VI: v_interp_p1_f32_e32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xd4]
3030
3131 v_interp_p1_f32 v8, v0, attr3.z
3232 // SI: v_interp_p1_f32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xc8]
33 // VI: v_interp_p1_f32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xd4]
33 // VI: v_interp_p1_f32_e32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xd4]
3434
3535 v_interp_p1_f32 v9, v0, attr4.w
3636 // SI: v_interp_p1_f32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xc8]
37 // VI: v_interp_p1_f32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xd4]
37 // VI: v_interp_p1_f32_e32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xd4]
3838
3939 v_interp_p1_f32 v10, v0, attr63.w
4040 // SI: v_interp_p1_f32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xc8]
41 // VI: v_interp_p1_f32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xd4]
41 // VI: v_interp_p1_f32_e32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xd4]
4242
4343
4444 v_interp_p2_f32 v2, v1, attr0.x
4545 // SI: v_interp_p2_f32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xc8]
46 // VI: v_interp_p2_f32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xd4]
46 // VI: v_interp_p2_f32_e32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xd4]
4747
4848 v_interp_p2_f32 v3, v1, attr0.y
4949 // SI: v_interp_p2_f32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xc8]
50 // VI: v_interp_p2_f32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xd4]
50 // VI: v_interp_p2_f32_e32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xd4]
5151
5252 v_interp_p2_f32 v4, v1, attr0.z
5353 // SI: v_interp_p2_f32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xc8]
54 // VI: v_interp_p2_f32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xd4]
54 // VI: v_interp_p2_f32_e32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xd4]
5555
5656 v_interp_p2_f32 v5, v1, attr0.w
5757 // SI: v_interp_p2_f32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xc8]
58 // VI: v_interp_p2_f32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xd4]
58 // VI: v_interp_p2_f32_e32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xd4]
5959
6060 v_interp_p2_f32 v6, v1, attr0.x
6161 // SI: v_interp_p2_f32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xc8]
62 // VI: v_interp_p2_f32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xd4]
62 // VI: v_interp_p2_f32_e32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xd4]
6363
6464 v_interp_p2_f32 v7, v1, attr1.x
6565 // SI: v_interp_p2_f32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xc8]
66 // VI: v_interp_p2_f32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xd4]
66 // VI: v_interp_p2_f32_e32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xd4]
6767
6868 v_interp_p2_f32 v8, v1, attr63.x
6969 // SI: v_interp_p2_f32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xc8]
70 // VI: v_interp_p2_f32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xd4]
70 // VI: v_interp_p2_f32_e32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xd4]
7171
7272
7373 v_interp_mov_f32 v0, p10, attr0.x
7474 // SI: v_interp_mov_f32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xc8]
75 // VI: v_interp_mov_f32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xd4]
75 // VI: v_interp_mov_f32_e32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xd4]
7676
7777 v_interp_mov_f32 v1, p20, attr0.x
7878 // SI: v_interp_mov_f32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xc8]
79 // VI: v_interp_mov_f32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xd4]
79 // VI: v_interp_mov_f32_e32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xd4]
8080
8181 v_interp_mov_f32 v2, p0, attr0.x
8282 // SI: v_interp_mov_f32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xc8]
83 // VI: v_interp_mov_f32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xd4]
83 // VI: v_interp_mov_f32_e32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xd4]
8484
8585 v_interp_mov_f32 v4, p10, attr0.y
8686 // SI: v_interp_mov_f32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xc8]
87 // VI: v_interp_mov_f32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xd4]
87 // VI: v_interp_mov_f32_e32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xd4]
8888
8989 v_interp_mov_f32 v5, p10, attr0.z
9090 // SI: v_interp_mov_f32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xc8]
91 // VI: v_interp_mov_f32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xd4]
91 // VI: v_interp_mov_f32_e32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xd4]
9292
9393 v_interp_mov_f32 v6, p10, attr0.w
9494 // SI: v_interp_mov_f32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xc8]
95 // VI: v_interp_mov_f32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xd4]
95 // VI: v_interp_mov_f32_e32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xd4]
9696
9797 v_interp_mov_f32 v7, p10, attr0.x
9898 // SI: v_interp_mov_f32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xc8]
99 // VI: v_interp_mov_f32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xd4]
99 // VI: v_interp_mov_f32_e32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xd4]
100100
101101 v_interp_mov_f32 v9, p10, attr63.y
102102 // SI: v_interp_mov_f32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xc8]
103 // VI: v_interp_mov_f32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xd4]
103 // VI: v_interp_mov_f32_e32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xd4]
104104
0 # RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI
11
2 #VI: v_interp_p1_f32 v7, v212, attr16.y
2 #VI: v_interp_p1_f32_e32 v7, v212, attr16.y
33 0xd4 0x41 0x1c 0xd4
44
5 #VI: v_interp_p2_f32 v7, v212, attr16.y
5 #VI: v_interp_p2_f32_e32 v7, v212, attr16.y
66 0xd4 0x41 0x1d 0xd4
77
8 #VI: v_interp_mov_f32 v7, invalid_param_212, attr16.y
8 #VI: v_interp_mov_f32_e32 v7, invalid_param_212, attr16.y
99 0xd4 0x41 0x1e 0xd4
1010
11 #VI: v_interp_mov_f32 v7, p10, attr16.y
11 #VI: v_interp_mov_f32_e32 v7, p10, attr16.y
1212 0x00 0x41 0x1e 0xd4
1313
14 #VI: v_interp_mov_f32 v7, p20, attr16.y
14 #VI: v_interp_mov_f32_e32 v7, p20, attr16.y
1515 0x01 0x41 0x1e 0xd4
1616
17 #VI: v_interp_mov_f32 v7, p0, attr16.y
17 #VI: v_interp_mov_f32_e32 v7, p0, attr16.y
1818 0x02 0x41 0x1e 0xd4
1919
20 #VI: v_interp_mov_f32 v7, invalid_param_3, attr16.y
20 #VI: v_interp_mov_f32_e32 v7, invalid_param_3, attr16.y
2121 0x03 0x41 0x1e 0xd4
2222
23 # VI: v_interp_p1_f32 v0, v0, attr0.x
23 # VI: v_interp_p1_f32_e32 v0, v0, attr0.x
2424 0x00 0x00 0x00 0xd4
2525
26 # VI: v_interp_p1_f32 v0, v0, attr0.x
26 # VI: v_interp_p1_f32_e32 v0, v0, attr0.x
2727 0x00 0x00 0x00 0xd4
2828
29 # VI: v_interp_p1_f32 v0, v1, attr0.x
29 # VI: v_interp_p1_f32_e32 v0, v1, attr0.x
3030 0x01 0x00 0x00 0xd4
3131
32 # VI: v_interp_p1_f32 v0, v1, attr0.w
32 # VI: v_interp_p1_f32_e32 v0, v1, attr0.w
3333 0x01 0x03 0x00 0xd4
3434
35 # VI: v_interp_p2_f32 v0, v1, attr0.x
35 # VI: v_interp_p2_f32_e32 v0, v1, attr0.x
3636 0x01 0x00 0x01 0xd4
3737
38 # VI: v_interp_mov_f32 v0, p20, attr0.x
38 # VI: v_interp_mov_f32_e32 v0, p20, attr0.x
3939 0x01 0x00 0x02 0xd4
4040
41 #VI: v_interp_p2_f32 v0, v1, attr63.x
41 #VI: v_interp_p2_f32_e32 v0, v1, attr63.x
4242 0x01 0xfc 0x01 0xd4
4343
44 #VI: v_interp_p2_f32 v0, v1, attr63.x
44 #VI: v_interp_p2_f32_e32 v0, v1, attr63.x
4545 0x01 0xfc 0x01 0xd4
4646
47 #VI: v_interp_p2_f32 v0, v1, attr63.w
47 #VI: v_interp_p2_f32_e32 v0, v1, attr63.w
4848 0x01 0xff 0x01 0xd4