llvm.org GIT mirror llvm / a59d469
Merge current work back to tree to minimize diffs and drift. Major highlights for CellSPU modifications: - SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend. - Other improvements based on refactoring effort in SPUISelLowering.cpp, esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and rotates are now eliminiated, other scalar-to-vector-to-scalar silliness is also eliminated. - 64-bit operations are being implemented, _muldi3.c gcc runtime now compiles and generates the right code. More work still needs to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Michel 12 years ago
11 changed file(s) with 1996 addition(s) and 1076 deletion(s). Raw diff Collapse all Expand all
1818 // 7-bit integer type, used as an immediate:
1919 def cell_i7_ty: LLVMType;
2020 def cell_i8_ty: LLVMType;
21
22 // Keep this here until it's actually supported:
23 def llvm_i128_ty : LLVMType;
2124
2225 class v16i8_u7imm :
2326 GCCBuiltin,
157160 [IntrNoMem]>;
158161
159162 def int_spu_si_shli: v4i32_u7imm<"shli">;
160 def int_spu_si_shlqbi: v16i8_rr<"shlqbi">;
163
164 def int_spu_si_shlqbi:
165 GCCBuiltin,
166 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty],
167 [IntrNoMem]>;
168
161169 def int_spu_si_shlqbii: v16i8_u7imm<"shlqbii">;
162 def int_spu_si_shlqby: v16i8_rr<"shlqby">;
170 def int_spu_si_shlqby:
171 GCCBuiltin,
172 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty],
173 [IntrNoMem]>;
163174 def int_spu_si_shlqbyi: v16i8_u7imm<"shlqbyi">;
164175
165176 def int_spu_si_ceq: v4i32_rr<"ceq">;
209209 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
210210
211211 def CellSDKshlqbi:
212 Pat<(int_spu_si_shlqbi VECREG:$rA, VECREG:$rB),
213 (SHLQBIvec VECREG:$rA, VECREG:$rB)>;
212 Pat<(int_spu_si_shlqbi VECREG:$rA, R32C:$rB),
213 (SHLQBIv16i8 VECREG:$rA, R32C:$rB)>;
214214
215215 def CellSDKshlqii:
216216 Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val),
217 (SHLQBIIvec VECREG:$rA, uimm7:$val)>;
217 (SHLQBIIv16i8 VECREG:$rA, uimm7:$val)>;
218218
219219 def CellSDKshlqby:
220 Pat<(int_spu_si_shlqby VECREG:$rA, VECREG:$rB),
221 (SHLQBYvec VECREG:$rA, VECREG:$rB)>;
220 Pat<(int_spu_si_shlqby VECREG:$rA, R32C:$rB),
221 (SHLQBYv16i8 VECREG:$rA, R32C:$rB)>;
222222
223223 def CellSDKshlqbyi:
224224 Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val),
225 (SHLQBYIvec VECREG:$rA, uimm7:$val)>;
225 (SHLQBYIv16i8 VECREG:$rA, uimm7:$val)>;
226226
227227 //===----------------------------------------------------------------------===//
228228 // Branch/compare intrinsics:
165165 struct valtype_map_s {
166166 MVT::ValueType VT;
167167 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
168 bool ldresult_imm; /// LDRESULT instruction requires immediate?
168169 int prefslot_byte; /// Byte offset of the "preferred" slot
169170 };
170171
171172 const valtype_map_s valtype_map[] = {
172 { MVT::i1, 0, 3 },
173 { MVT::i8, SPU::ORBIr8, 3 },
174 { MVT::i16, SPU::ORHIr16, 2 },
175 { MVT::i32, SPU::ORIr32, 0 },
176 { MVT::i64, SPU::ORIr64, 0 },
177 { MVT::f32, 0, 0 },
178 { MVT::f64, 0, 0 },
173 { MVT::i1, 0, false, 3 },
174 { MVT::i8, SPU::ORBIr8, true, 3 },
175 { MVT::i16, SPU::ORHIr16, true, 2 },
176 { MVT::i32, SPU::ORIr32, true, 0 },
177 { MVT::i64, SPU::ORr64, false, 0 },
178 { MVT::f32, SPU::ORf32, false, 0 },
179 { MVT::f64, SPU::ORf64, false, 0 },
179180 // vector types... (sigh!)
180 { MVT::v16i8, 0, 0 },
181 { MVT::v8i16, 0, 0 },
182 { MVT::v4i32, 0, 0 },
183 { MVT::v2i64, 0, 0 },
184 { MVT::v4f32, 0, 0 },
185 { MVT::v2f64, 0, 0 }
181 { MVT::v16i8, 0, false, 0 },
182 { MVT::v8i16, 0, false, 0 },
183 { MVT::v4i32, 0, false, 0 },
184 { MVT::v2i64, 0, false, 0 },
185 { MVT::v4f32, 0, false, 0 },
186 { MVT::v2f64, 0, false, 0 }
186187 };
187188
188189 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
602603 // to i8, then i8 to i16 in logical/branching operations.
603604 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
604605 ", ))\n");
605 NewOpc = SPU::ANDHI1To2;
606 NewOpc = SPU::ANDHIi8i16;
606607 Ops[0] = Op1.getOperand(0);
607608 Ops[1] = Op1.getOperand(1);
608609 n_ops = 2;
614615 SDOperand Arg = N->getOperand(0);
615616 SDOperand Chain = N->getOperand(1);
616617 SDNode *Result;
618 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
619
620 if (vtm->ldresult_ins == 0) {
621 cerr << "LDRESULT for unsupported type: "
622 << MVT::getValueTypeString(VT)
623 << "\n";
624 abort();
625 }
617626
618627 AddToISelQueue(Arg);
619 if (!MVT::isFloatingPoint(VT)) {
628 Opc = vtm->ldresult_ins;
629 if (vtm->ldresult_imm) {
620630 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
621 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
622
623 if (vtm->ldresult_ins == 0) {
624 cerr << "LDRESULT for unsupported type: "
625 << MVT::getValueTypeString(VT)
626 << "\n";
627 abort();
628 } else
629 Opc = vtm->ldresult_ins;
630631
631632 AddToISelQueue(Zero);
632633 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
633634 } else {
634 Opc = (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64);
635635 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
636636 }
637637
215215 setOperationAction(ISD::SHL, MVT::i8, Custom);
216216 setOperationAction(ISD::SRL, MVT::i8, Custom);
217217 setOperationAction(ISD::SRA, MVT::i8, Custom);
218 // And SPU needs custom lowering for shift left/right for i64
219 setOperationAction(ISD::SHL, MVT::i64, Custom);
220 setOperationAction(ISD::SRL, MVT::i64, Custom);
221 setOperationAction(ISD::SRA, MVT::i64, Custom);
218222
219223 // Custom lower i32 multiplications
220224 setOperationAction(ISD::MUL, MVT::i32, Custom);
247251 setOperationAction(ISD::SELECT, MVT::f32, Expand);
248252 setOperationAction(ISD::SELECT, MVT::f64, Expand);
249253
250 setOperationAction(ISD::SETCC, MVT::i1, Expand);
251 setOperationAction(ISD::SETCC, MVT::i8, Expand);
252 setOperationAction(ISD::SETCC, MVT::i16, Expand);
253 setOperationAction(ISD::SETCC, MVT::i32, Expand);
254 setOperationAction(ISD::SETCC, MVT::i64, Expand);
255 setOperationAction(ISD::SETCC, MVT::f32, Expand);
256 setOperationAction(ISD::SETCC, MVT::f64, Expand);
254 // Zero extension and sign extension for i64 have to be
255 // custom legalized
256 setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
257 setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
258 setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
257259
258260 // SPU has a legal FP -> signed INT instruction
259261 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
376378
377379 // We have target-specific dag combine patterns for the following nodes:
378380 setTargetDAGCombine(ISD::ADD);
381 setTargetDAGCombine(ISD::ZERO_EXTEND);
382 setTargetDAGCombine(ISD::SIGN_EXTEND);
383 setTargetDAGCombine(ISD::ANY_EXTEND);
379384
380385 computeRegisterProperties();
381386 }
406411 node_names[(unsigned) SPUISD::MPYU] = "SPUISD::MPYU";
407412 node_names[(unsigned) SPUISD::MPYH] = "SPUISD::MPYH";
408413 node_names[(unsigned) SPUISD::MPYHH] = "SPUISD::MPYHH";
414 node_names[(unsigned) SPUISD::SHLQUAD_L_BITS] = "SPUISD::SHLQUAD_L_BITS";
415 node_names[(unsigned) SPUISD::SHLQUAD_L_BYTES] = "SPUISD::SHLQUAD_L_BYTES";
409416 node_names[(unsigned) SPUISD::VEC_SHL] = "SPUISD::VEC_SHL";
410417 node_names[(unsigned) SPUISD::VEC_SRL] = "SPUISD::VEC_SRL";
411418 node_names[(unsigned) SPUISD::VEC_SRA] = "SPUISD::VEC_SRA";
412419 node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL";
413420 node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR";
414 node_names[(unsigned) SPUISD::ROTBYTES_RIGHT_Z] =
415 "SPUISD::ROTBYTES_RIGHT_Z";
421 node_names[(unsigned) SPUISD::ROTQUAD_RZ_BYTES] =
422 "SPUISD::ROTQUAD_RZ_BYTES";
423 node_names[(unsigned) SPUISD::ROTQUAD_RZ_BITS] =
424 "SPUISD::ROTQUAD_RZ_BITS";
416425 node_names[(unsigned) SPUISD::ROTBYTES_RIGHT_S] =
417426 "SPUISD::ROTBYTES_RIGHT_S";
418427 node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT";
707716 && basePtr.getOperand(0).getOpcode() == SPUISD::IndirectAddr)) {
708717 insertEltPtr = basePtr;
709718 } else {
710 #if 0
711 // $sp is always aligned, so use it when necessary to avoid loading
712 // an address
713 SDOperand ptrP =
714 basePtr.Val->hasOneUse() ? DAG.getRegister(SPU::R1, PtrVT) : basePtr;
715 insertEltPtr = DAG.getNode(ISD::ADD, PtrVT, ptrP, insertEltOffs);
716 #else
717719 insertEltPtr = DAG.getNode(ISD::ADD, PtrVT, basePtr, insertEltOffs);
718 #endif
719720 }
720721
721722 insertEltOp = DAG.getNode(SPUISD::INSERT_MASK, stVecVT, insertEltPtr);
761762 // Just return the SDOperand with the constant pool address in it.
762763 return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero);
763764 } else {
764 #if 1
765765 SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero);
766766 SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero);
767
768 return DAG.getNode(ISD::ADD, PtrVT, Lo, Hi);
769 #else
770 return DAG.getNode(SPUISD::IndirectAddr, PtrVT, CPI, Zero);
771 #endif
767 return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
772768 }
773769 }
774770
786782 const TargetMachine &TM = DAG.getTarget();
787783
788784 if (TM.getRelocationModel() == Reloc::Static) {
789 SDOperand JmpAForm = DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero);
790 return (!ST->usingLargeMem()
791 ? JmpAForm
792 : DAG.getNode(SPUISD::IndirectAddr, PtrVT, JmpAForm, Zero));
785 if (!ST->usingLargeMem()) {
786 return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero);
787 } else {
788 SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero);
789 SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero);
790 return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
791 }
793792 }
794793
795794 assert(0 &&
18061805 else
18071806 SrcElt = cast(PermMask.getOperand(i))->getValue();
18081807
1809 for (unsigned j = 0; j != BytesPerElement; ++j) {
1808 for (unsigned j = 0; j < BytesPerElement; ++j) {
18101809 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
18111810 MVT::i8));
18121811 }
19241923 // is to break it all apart, sign extend, and reassemble the various
19251924 // intermediate products.
19261925 case MVT::v16i8: {
1927 MachineFunction &MF = DAG.getMachineFunction();
1928 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1929 SDOperand Chain = Op.getOperand(0);
19301926 SDOperand rA = Op.getOperand(0);
19311927 SDOperand rB = Op.getOperand(1);
1932 SDOperand c8 = DAG.getConstant(8, MVT::i8);
1933 SDOperand c16 = DAG.getConstant(16, MVT::i8);
1934
1935 unsigned FSMBreg_2222 = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1936 unsigned LoProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1937 unsigned HiProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1928 SDOperand c8 = DAG.getConstant(8, MVT::i32);
1929 SDOperand c16 = DAG.getConstant(16, MVT::i32);
19381930
19391931 SDOperand LLProd =
19401932 DAG.getNode(SPUISD::MPY, MVT::v8i16,
19491941 DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16,
19501942 DAG.getNode(SPUISD::MPY, MVT::v8i16, rALH, rBLH), c8);
19511943
1952 SDOperand FSMBdef_2222 =
1953 DAG.getCopyToReg(Chain, FSMBreg_2222,
1954 DAG.getNode(SPUISD::FSMBI, MVT::v8i16,
1955 DAG.getConstant(0x2222, MVT::i32)));
1956
1957 SDOperand FSMBuse_2222 =
1958 DAG.getCopyFromReg(FSMBdef_2222, FSMBreg_2222, MVT::v4i32);
1959
1960 SDOperand LoProd_1 =
1961 DAG.getCopyToReg(Chain, LoProd_reg,
1962 DAG.getNode(SPUISD::SELB, MVT::v8i16, LLProd, LHProd,
1963 FSMBuse_2222));
1944 SDOperand FSMBmask = DAG.getNode(SPUISD::FSMBI, MVT::v8i16,
1945 DAG.getConstant(0x2222, MVT::i32));
1946
1947 SDOperand LoProdParts =
1948 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
1949 DAG.getNode(SPUISD::SELB, MVT::v8i16,
1950 LLProd, LHProd, FSMBmask));
19641951
19651952 SDOperand LoProdMask = DAG.getConstant(0xffff, MVT::i32);
19661953
19671954 SDOperand LoProd =
19681955 DAG.getNode(ISD::AND, MVT::v4i32,
1969 DAG.getCopyFromReg(LoProd_1, LoProd_reg, MVT::v4i32),
1956 LoProdParts,
19701957 DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
19711958 LoProdMask, LoProdMask,
19721959 LoProdMask, LoProdMask));
19921979 DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rBH, c8)));
19931980
19941981 SDOperand HHProd =
1995 DAG.getCopyToReg(Chain, HiProd_reg,
1996 DAG.getNode(SPUISD::SELB, MVT::v8i16,
1997 HLProd,
1998 DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, HHProd_1, c8),
1999 FSMBuse_2222));
1982 DAG.getNode(SPUISD::SELB, MVT::v8i16,
1983 HLProd,
1984 DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, HHProd_1, c8),
1985 FSMBmask);
20001986
20011987 SDOperand HiProd =
2002 DAG.getNode(SPUISD::VEC_SHL, MVT::v4i32,
2003 DAG.getCopyFromReg(HHProd, HiProd_reg, MVT::v4i32), c16);
1988 DAG.getNode(SPUISD::VEC_SHL, MVT::v4i32, HHProd, c16);
20041989
20051990 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8,
20061991 DAG.getNode(ISD::OR, MVT::v4i32,
21672152 return result;
21682153 }
21692154
2170 static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) {
2155 static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
2156 {
21712157 SDOperand N0 = Op.getOperand(0); // Everything has at least one operand
21722158
21732159 assert(Op.getValueType() == MVT::i8);
22532239 return SDOperand();
22542240 }
22552241
2242 static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
2243 {
2244 MVT::ValueType VT = Op.getValueType();
2245 unsigned VecVT =
2246 MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
2247
2248 SDOperand Op0 = Op.getOperand(0);
2249
2250 switch (Opc) {
2251 case ISD::ZERO_EXTEND:
2252 case ISD::SIGN_EXTEND:
2253 case ISD::ANY_EXTEND: {
2254 MVT::ValueType Op0VT = Op0.getValueType();
2255 unsigned Op0VecVT =
2256 MVT::getVectorType(Op0VT, (128 / MVT::getSizeInBits(Op0VT)));
2257
2258 assert(Op0VT == MVT::i32
2259 && "CellSPU: Zero/sign extending something other than i32");
2260
2261 unsigned NewOpc = (Opc == ISD::SIGN_EXTEND
2262 ? SPUISD::ROTBYTES_RIGHT_S
2263 : SPUISD::ROTQUAD_RZ_BYTES);
2264 SDOperand PromoteScalar =
2265 DAG.getNode(SPUISD::PROMOTE_SCALAR, Op0VecVT, Op0);
2266
2267 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
2268 DAG.getNode(ISD::BIT_CONVERT, VecVT,
2269 DAG.getNode(NewOpc, Op0VecVT,
2270 PromoteScalar,
2271 DAG.getConstant(4, MVT::i32))));
2272 }
2273
2274 case ISD::SHL: {
2275 SDOperand ShiftAmt = Op.getOperand(1);
2276 unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType());
2277 SDOperand Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0);
2278 SDOperand MaskLower =
2279 DAG.getNode(SPUISD::SELB, VecVT,
2280 Op0Vec,
2281 DAG.getConstant(0, VecVT),
2282 DAG.getNode(SPUISD::FSMBI, VecVT,
2283 DAG.getConstant(0xff00ULL, MVT::i16)));
2284 SDOperand ShiftAmtBytes =
2285 DAG.getNode(ISD::SRL, ShiftAmtVT,
2286 ShiftAmt,
2287 DAG.getConstant(3, ShiftAmtVT));
2288 SDOperand ShiftAmtBits =
2289 DAG.getNode(ISD::AND, ShiftAmtVT,
2290 ShiftAmt,
2291 DAG.getConstant(7, ShiftAmtVT));
2292
2293 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
2294 DAG.getNode(SPUISD::SHLQUAD_L_BITS, VecVT,
2295 DAG.getNode(SPUISD::SHLQUAD_L_BYTES, VecVT,
2296 MaskLower, ShiftAmtBytes),
2297 ShiftAmtBits));
2298 }
2299
2300 case ISD::SRL: {
2301 unsigned VT = unsigned(Op.getValueType());
2302 SDOperand ShiftAmt = Op.getOperand(1);
2303 unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType());
2304 SDOperand ShiftAmtBytes =
2305 DAG.getNode(ISD::SRL, ShiftAmtVT,
2306 ShiftAmt,
2307 DAG.getConstant(3, ShiftAmtVT));
2308 SDOperand ShiftAmtBits =
2309 DAG.getNode(ISD::AND, ShiftAmtVT,
2310 ShiftAmt,
2311 DAG.getConstant(7, ShiftAmtVT));
2312
2313 return DAG.getNode(SPUISD::ROTQUAD_RZ_BITS, VT,
2314 DAG.getNode(SPUISD::ROTQUAD_RZ_BYTES, VT,
2315 Op0, ShiftAmtBytes),
2316 ShiftAmtBits);
2317 }
2318 }
2319
2320 return SDOperand();
2321 }
2322
22562323 //! Lower byte immediate operations for v16i8 vectors:
22572324 static SDOperand
22582325 LowerByteImmed(SDOperand Op, SelectionDAG &DAG) {
24372504 SDOperand
24382505 SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
24392506 {
2440 switch (Op.getOpcode()) {
2507 unsigned Opc = (unsigned) Op.getOpcode();
2508 unsigned VT = (unsigned) Op.getValueType();
2509
2510 switch (Opc) {
24412511 default: {
24422512 cerr << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
2443 cerr << "Op.getOpcode() = " << Op.getOpcode() << "\n";
2513 cerr << "Op.getOpcode() = " << Opc << "\n";
24442514 cerr << "*Op.Val:\n";
24452515 Op.Val->dump();
24462516 abort();
24702540 case ISD::RET:
24712541 return LowerRET(Op, DAG, getTargetMachine());
24722542
2473 // i8 math ops:
2543
2544 // i8, i64 math ops:
2545 case ISD::ZERO_EXTEND:
2546 case ISD::SIGN_EXTEND:
2547 case ISD::ANY_EXTEND:
24742548 case ISD::SUB:
24752549 case ISD::ROTR:
24762550 case ISD::ROTL:
24772551 case ISD::SRL:
24782552 case ISD::SHL:
24792553 case ISD::SRA:
2480 return LowerI8Math(Op, DAG, Op.getOpcode());
2554 if (VT == MVT::i8)
2555 return LowerI8Math(Op, DAG, Opc);
2556 else if (VT == MVT::i64)
2557 return LowerI64Math(Op, DAG, Opc);
2558 break;
24812559
24822560 // Vector-related lowering.
24832561 case ISD::BUILD_VECTOR:
24992577
25002578 // Vector and i8 multiply:
25012579 case ISD::MUL:
2502 if (MVT::isVector(Op.getValueType()))
2580 if (MVT::isVector(VT))
25032581 return LowerVectorMUL(Op, DAG);
2504 else if (Op.getValueType() == MVT::i8)
2505 return LowerI8Math(Op, DAG, Op.getOpcode());
2582 else if (VT == MVT::i8)
2583 return LowerI8Math(Op, DAG, Opc);
25062584 else
2507 return LowerMUL(Op, DAG, Op.getValueType(), Op.getOpcode());
2585 return LowerMUL(Op, DAG, VT, Opc);
25082586
25092587 case ISD::FDIV:
2510 if (Op.getValueType() == MVT::f32 || Op.getValueType() == MVT::v4f32)
2588 if (VT == MVT::f32 || VT == MVT::v4f32)
25112589 return LowerFDIVf32(Op, DAG);
25122590 // else if (Op.getValueType() == MVT::f64)
25132591 // return LowerFDIVf64(Op, DAG);
25332611 #endif
25342612 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
25352613 SelectionDAG &DAG = DCI.DAG;
2536 SDOperand N0 = N->getOperand(0); // everything has at least one operand
2614 SDOperand Op0 = N->getOperand(0); // everything has at least one operand
2615 SDOperand Result; // Initially, NULL result
25372616
25382617 switch (N->getOpcode()) {
25392618 default: break;
2540 case SPUISD::IndirectAddr: {
2541 if (!ST->usingLargeMem() && N0.getOpcode() == SPUISD::AFormAddr) {
2542 ConstantSDNode *CN = cast(N->getOperand(1));
2543 if (CN->getValue() == 0) {
2544 // (SPUindirect (SPUaform , 0), 0) ->
2545 // (SPUaform , 0)
2546
2547 DEBUG(cerr << "Replace: ");
2548 DEBUG(N->dump(&DAG));
2549 DEBUG(cerr << "\nWith: ");
2550 DEBUG(N0.Val->dump(&DAG));
2551 DEBUG(cerr << "\n");
2552
2553 return N0;
2554 }
2555 }
2556 }
25572619 case ISD::ADD: {
2558 SDOperand Op0 = N->getOperand(0);
25592620 SDOperand Op1 = N->getOperand(1);
25602621
25612622 if ((Op1.getOpcode() == ISD::Constant
26022663 Op1.getOperand(0), combinedConst);
26032664 }
26042665 }
2666 break;
2667 }
2668 case ISD::SIGN_EXTEND:
2669 case ISD::ZERO_EXTEND:
2670 case ISD::ANY_EXTEND: {
2671 if (Op0.getOpcode() == SPUISD::EXTRACT_ELT0 &&
2672 N->getValueType(0) == Op0.getValueType()) {
2673 // (any_extend (SPUextract_elt0 )) ->
2674 // (SPUextract_elt0 )
2675 // Types must match, however...
2676 DEBUG(cerr << "Replace: ");
2677 DEBUG(N->dump(&DAG));
2678 DEBUG(cerr << "\nWith: ");
2679 DEBUG(Op0.Val->dump(&DAG));
2680 DEBUG(cerr << "\n");
2681
2682 return Op0;
2683 }
2684 break;
2685 }
2686 case SPUISD::IndirectAddr: {
2687 if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
2688 ConstantSDNode *CN = cast(N->getOperand(1));
2689 if (CN->getValue() == 0) {
2690 // (SPUindirect (SPUaform , 0), 0) ->
2691 // (SPUaform , 0)
2692
2693 DEBUG(cerr << "Replace: ");
2694 DEBUG(N->dump(&DAG));
2695 DEBUG(cerr << "\nWith: ");
2696 DEBUG(Op0.Val->dump(&DAG));
2697 DEBUG(cerr << "\n");
2698
2699 return Op0;
2700 }
2701 }
2702 break;
2703 }
2704 case SPUISD::SHLQUAD_L_BITS:
2705 case SPUISD::SHLQUAD_L_BYTES:
2706 case SPUISD::VEC_SHL:
2707 case SPUISD::VEC_SRL:
2708 case SPUISD::VEC_SRA:
2709 case SPUISD::ROTQUAD_RZ_BYTES:
2710 case SPUISD::ROTQUAD_RZ_BITS: {
2711 SDOperand Op1 = N->getOperand(1);
2712
2713 if (isa(Op1)) {
2714 // Kill degenerate vector shifts:
2715 ConstantSDNode *CN = cast(Op1);
2716
2717 if (CN->getValue() == 0) {
2718 Result = Op0;
2719 }
2720 }
2721 break;
2722 }
2723 case SPUISD::PROMOTE_SCALAR: {
2724 switch (Op0.getOpcode()) {
2725 default:
2726 break;
2727 case ISD::ANY_EXTEND:
2728 case ISD::ZERO_EXTEND:
2729 case ISD::SIGN_EXTEND: {
2730 // (SPUpromote_scalar (any|sign|zero_extend (SPUextract_elt0 ))) ->
2731 //
2732 // but only if the SPUpromote_scalar and types match.
2733 SDOperand Op00 = Op0.getOperand(0);
2734 if (Op00.getOpcode() == SPUISD::EXTRACT_ELT0) {
2735 SDOperand Op000 = Op00.getOperand(0);
2736 if (Op000.getValueType() == N->getValueType(0)) {
2737 Result = Op000;
2738 }
2739 }
2740 break;
2741 }
2742 case SPUISD::EXTRACT_ELT0: {
2743 // (SPUpromote_scalar (SPUextract_elt0 )) ->
2744 //
2745 Result = Op0.getOperand(0);
2746 break;
2747 }
2748 }
2749 break;
26052750 }
26062751 }
26072752 // Otherwise, return unchanged.
2608 return SDOperand();
2753 #if 0
2754 if (Result.Val) {
2755 DEBUG(cerr << "\nReplace.SPU: ");
2756 DEBUG(N->dump(&DAG));
2757 DEBUG(cerr << "\nWith: ");
2758 DEBUG(Result.Val->dump(&DAG));
2759 DEBUG(cerr << "\n");
2760 }
2761 #endif
2762
2763 return Result;
26092764 }
26102765
26112766 //===----------------------------------------------------------------------===//
26562811 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26572812 }
26582813
2814 //! Compute used/known bits for a SPU operand
26592815 void
26602816 SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
26612817 const APInt &Mask,
26632819 APInt &KnownOne,
26642820 const SelectionDAG &DAG,
26652821 unsigned Depth ) const {
2666 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2822 const uint64_t uint64_sizebits = sizeof(uint64_t) * 8;
2823
2824 switch (Op.getOpcode()) {
2825 default:
2826 // KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2827 break;
2828
2829 #if 0
2830 case CALL:
2831 case SHUFB:
2832 case INSERT_MASK:
2833 case CNTB:
2834 #endif
2835
2836 case SPUISD::PROMOTE_SCALAR: {
2837 SDOperand Op0 = Op.getOperand(0);
2838 uint64_t InMask = MVT::getIntVTBitMask(Op0.getValueType());
2839 KnownZero |= APInt(uint64_sizebits, ~InMask, false);
2840 KnownOne |= APInt(uint64_sizebits, InMask, false);
2841 break;
2842 }
2843
2844 case SPUISD::LDRESULT:
2845 case SPUISD::EXTRACT_ELT0:
2846 case SPUISD::EXTRACT_ELT0_CHAINED: {
2847 uint64_t InMask = MVT::getIntVTBitMask(Op.getValueType());
2848 KnownZero |= APInt(uint64_sizebits, ~InMask, false);
2849 KnownOne |= APInt(uint64_sizebits, InMask, false);
2850 break;
2851 }
2852
2853 #if 0
2854 case EXTRACT_I1_ZEXT:
2855 case EXTRACT_I1_SEXT:
2856 case EXTRACT_I8_ZEXT:
2857 case EXTRACT_I8_SEXT:
2858 case MPY:
2859 case MPYU:
2860 case MPYH:
2861 case MPYHH:
2862 case SHLQUAD_L_BITS:
2863 case SHLQUAD_L_BYTES:
2864 case VEC_SHL:
2865 case VEC_SRL:
2866 case VEC_SRA:
2867 case VEC_ROTL:
2868 case VEC_ROTR:
2869 case ROTQUAD_RZ_BYTES:
2870 case ROTQUAD_RZ_BITS:
2871 case ROTBYTES_RIGHT_S:
2872 case ROTBYTES_LEFT:
2873 case ROTBYTES_LEFT_CHAINED:
2874 case FSMBI:
2875 case SELB:
2876 case SFPConstant:
2877 case FPInterp:
2878 case FPRecipEst:
2879 case SEXT32TO64:
2880 #endif
2881 }
26672882 }
26682883
26692884 // LowerAsmOperandForConstraint
4949 MPYU, ///< Multiply Unsigned
5050 MPYH, ///< Multiply High
5151 MPYHH, ///< Multiply High-High
52 SHLQUAD_L_BITS, ///< Rotate quad left, by bits
53 SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes
5254 VEC_SHL, ///< Vector shift left
5355 VEC_SRL, ///< Vector shift right (logical)
5456 VEC_SRA, ///< Vector shift right (arithmetic)
5557 VEC_ROTL, ///< Vector rotate left
5658 VEC_ROTR, ///< Vector rotate right
57 ROTBYTES_RIGHT_Z, ///< Vector rotate right, by bytes, zero fill
59 ROTQUAD_RZ_BYTES, ///< Rotate quad right, by bytes, zero fill
60 ROTQUAD_RZ_BITS, ///< Rotate quad right, by bits, zero fill
5861 ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill
5962 ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
6063 ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
1313
1414 // This was kiped from the PPC instruction formats (seemed like a good idea...)
1515
16 class I
16 class SPUInstr
1717 : Instruction {
1818 field bits<32> Inst;
1919
2727 // RR Format
2828 class RRForm opcode, dag OOL, dag IOL, string asmstr,
2929 InstrItinClass itin, list pattern>
30 : I {
30 : SPUInstr {
3131 bits<7> RA;
3232 bits<7> RB;
3333 bits<7> RT;
6969 // RRR Format
7070 class RRRForm opcode, dag OOL, dag IOL, string asmstr,
7171 InstrItinClass itin, list pattern>
72 : I
72 : SPUInstr
7373 {
7474 bits<7> RA;
7575 bits<7> RB;
8888 // RI7 Format
8989 class RI7Form opcode, dag OOL, dag IOL, string asmstr,
9090 InstrItinClass itin, list pattern>
91 : I
91 : SPUInstr
9292 {
9393 bits<7> i7;
9494 bits<7> RA;
105105 // CVTIntFp Format
106106 class CVTIntFPForm opcode, dag OOL, dag IOL, string asmstr,
107107 InstrItinClass itin, list pattern>
108 : I
108 : SPUInstr
109109 {
110110 bits<7> RA;
111111 bits<7> RT;
148148
149149 // Branch indirect external data forms:
150150 class BISLEDForm DE_flag, string asmstr, list pattern>
151 : I<(outs), (ins indcalltarget:$func), asmstr, BranchResolv>
151 : SPUInstr<(outs), (ins indcalltarget:$func), asmstr, BranchResolv>
152152 {
153153 bits<7> Rcalldest;
154154
165165 // RI10 Format
166166 class RI10Form opcode, dag OOL, dag IOL, string asmstr,
167167 InstrItinClass itin, list pattern>
168 : I
168 : SPUInstr
169169 {
170170 bits<10> i10;
171171 bits<7> RA;
181181
182182 // RI10 Format, where the constant is zero (or effectively ignored by the
183183 // SPU)
184 class RI10Form_1 opcode, dag OOL, dag IOL, string asmstr,
185 InstrItinClass itin, list pattern>
186 : I
187 {
188 bits<7> RA;
189 bits<7> RT;
190
191 let Pattern = pattern;
192
193 let Inst{0-7} = opcode;
194 let Inst{8-17} = 0;
195 let Inst{18-24} = RA;
196 let Inst{25-31} = RT;
184 let i10 = 0 in {
185 class RI10Form_1 opcode, dag OOL, dag IOL, string asmstr,
186 InstrItinClass itin, list pattern>
187 : RI10Form
188 { }
197189 }
198190
199191 // RI10 Format, where RT is ignored.
200192 // This format is used primarily by the Halt If ... Immediate set of
201193 // instructions
202 class RI10Form_2 opcode, dag OOL, dag IOL, string asmstr,
203 InstrItinClass itin, list pattern>
204 : I
205 {
206 bits<10> i10;
207 bits<7> RA;
208
209 let Pattern = pattern;
210
211 let Inst{0-7} = opcode;
212 let Inst{8-17} = i10;
213 let Inst{18-24} = RA;
214 let Inst{25-31} = 0;
194 let RT = 0 in {
195 class RI10Form_2 opcode, dag OOL, dag IOL, string asmstr,
196 InstrItinClass itin, list pattern>
197 : RI10Form
198 { }
215199 }
216200
217201 // RI16 Format
218202 class RI16Form opcode, dag OOL, dag IOL, string asmstr,
219203 InstrItinClass itin, list pattern>
220 : I
204 : SPUInstr
221205 {
222206 bits<16> i16;
223207 bits<7> RT;
253237 // RI18 Format
254238 class RI18Form opcode, dag OOL, dag IOL, string asmstr,
255239 InstrItinClass itin, list pattern>
256 : I
240 : SPUInstr
257241 {
258242 bits<18> i18;
259243 bits<7> RT;
305289 //===----------------------------------------------------------------------===//
306290
307291 class Pseudo pattern>
308 : I {
292 : SPUInstr {
309293 let Pattern = pattern;
310294 let Inst{31-0} = 0;
311295 }
4848 break;
4949 case SPU::ORIv4i32:
5050 case SPU::ORIr32:
51 case SPU::ORIr64:
5251 case SPU::ORHIv8i16:
5352 case SPU::ORHIr16:
54 case SPU::ORHI1To2:
53 case SPU::ORHIi8i16:
5554 case SPU::ORBIv16i8:
5655 case SPU::ORBIr8:
57 case SPU::ORI2To4:
58 case SPU::ORI1To4:
56 case SPU::ORIi16i32:
57 case SPU::ORIi8i32:
5958 case SPU::AHIvec:
6059 case SPU::AHIr16:
6160 case SPU::AIvec:
102101 case SPU::ORr64:
103102 case SPU::ORf32:
104103 case SPU::ORf64:
105 case SPU::ORgprc:
106104 assert(MI.getNumOperands() == 3 &&
107105 MI.getOperand(0).isRegister() &&
108106 MI.getOperand(1).isRegister() &&
202200 BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
203201 .addReg(SrcReg);
204202 } else if (DestRC == SPU::R64CRegisterClass) {
205 BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
203 BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
204 .addReg(SrcReg);
206205 } else if (DestRC == SPU::R64FPRegisterClass) {
207206 BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
208207 .addReg(SrcReg);
209 } else if (DestRC == SPU::GPRCRegisterClass) {
208 } /* else if (DestRC == SPU::GPRCRegisterClass) {
210209 BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
211210 .addReg(SrcReg);
212 } else if (DestRC == SPU::VECREGRegisterClass) {
211 } */ else if (DestRC == SPU::VECREGRegisterClass) {
213212 BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
214213 .addReg(SrcReg);
215214 } else {
373373
374374 // ILHUhi: Used for loading high portion of an address. Note the symbolHi
375375 // printer used for the operand.
376 def ILHUhi : RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val),
376 def ILHUhi:
377 RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val),
377378 "ilhu\t$rT, $val", ImmLoad,
378379 [(set R32C:$rT, hi16:$val)]>;
379380
380381 // Immediate load address (can also be used to load 18-bit unsigned constants,
381382 // see the zext 16->32 pattern)
382 def ILAr64:
383 RI18Form<0b1000010, (outs R64C:$rT), (ins u18imm_i64:$val),
384 "ila\t$rT, $val", LoadNOP,
385 [(set R64C:$rT, imm18:$val)]>;
386
387 // TODO: ILAv2i64
388
389 def ILAv2i64:
390 RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
391 "ila\t$rT, $val", LoadNOP,
392 [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>;
393
394 def ILAv4i32:
395 RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
396 "ila\t$rT, $val", LoadNOP,
397 [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>;
398
399 def ILAr32:
400 RI18Form<0b1000010, (outs R32C:$rT), (ins u18imm:$val),
401 "ila\t$rT, $val", LoadNOP,
402 [(set R32C:$rT, imm18:$val)]>;
403
404 def ILAf32:
405 RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val),
406 "ila\t$rT, $val", LoadNOP,
407 [(set R32FP:$rT, fpimm18:$val)]>;
408
409 def ILAf64:
410 RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val),
411 "ila\t$rT, $val", LoadNOP,
412 [(set R64FP:$rT, fpimm18:$val)]>;
413
414 def ILAlo:
415 RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val),
416 "ila\t$rT, $val", ImmLoad,
417 [(set R32C:$rT, imm18:$val)]>;
418
419 def ILAlsa:
420 RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLSA:$val),
421 "ila\t$rT, $val", ImmLoad,
422 [/* no pattern */]>;
383 class ILAInst pattern>:
384 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
385 LoadNOP, pattern>;
386
387 multiclass ImmLoadAddress
388 {
389 def v2i64: ILAInst<(outs VECREG:$rT), (ins u18imm:$val),
390 [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>;
391
392 def v4i32: ILAInst<(outs VECREG:$rT), (ins u18imm:$val),
393 [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>;
394
395 def r64: ILAInst<(outs R64C:$rT), (ins u18imm_i64:$val),
396 [(set R64C:$rT, imm18:$val)]>;
397
398 def r32: ILAInst<(outs R32C:$rT), (ins u18imm:$val),
399 [(set R32C:$rT, imm18:$val)]>;
400
401 def f32: ILAInst<(outs R32FP:$rT), (ins f18imm:$val),
402 [(set R32FP:$rT, fpimm18:$val)]>;
403
404 def f64: ILAInst<(outs R64FP:$rT), (ins f18imm_f64:$val),
405 [(set R64FP:$rT, fpimm18:$val)]>;
406
407 def lo: ILAInst<(outs R32C:$rT), (ins symbolLo:$val),
408 [(set R32C:$rT, imm18:$val)]>;
409
410 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
411 [/* no pattern */]>;
412 }
413
414 defm ILA : ImmLoadAddress;
423415
424416 // Immediate OR, Halfword Lower: The "other" part of loading large constants
425417 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
464456 [(set (vectype VECREG:$rT), (SPUfsmbi immU16:$val))]>
465457 { }
466458
467 multiclass FSMBIs
459 multiclass FormSelectMaskBytesImm
468460 {
469461 def v16i8: FSMBIVec;
470462 def v8i16: FSMBIVec;
472464 def v2i64: FSMBIVec;
473465 }
474466
475 defm FSMBI : FSMBIs;
467 defm FSMBI : FormSelectMaskBytesImm;
468
469 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
470 def FSMB:
471 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
472 "fsmb\t$rT, $rA", SelectOp,
473 []>;
474
475 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
476 // only 8-bits wide (even though it's input as 16-bits here)
477 def FSMH:
478 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
479 "fsmh\t$rT, $rA", SelectOp,
480 []>;
481
482 // fsm: Form select mask for words. Like the other fsm* instructions,
483 // only the lower 4 bits of $rA are significant.
484 def FSM:
485 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
486 "fsm\t$rT, $rA", SelectOp,
487 []>;
476488
477489 //===----------------------------------------------------------------------===//
478490 // Integer and Logical Operations:
485497
486498 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
487499 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
488
489 // [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
490500
491501 def AHr16:
492502 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
499509 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
500510 v8i16SExt10Imm:$val))]>;
501511
502 def AHIr16 : RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
503 "ahi\t$rT, $rA, $val", IntegerOp,
504 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
505
506 def Avec : RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
507 "a\t$rT, $rA, $rB", IntegerOp,
508 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
512 def AHIr16:
513 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
514 "ahi\t$rT, $rA, $val", IntegerOp,
515 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
516
517 def Avec:
518 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
519 "a\t$rT, $rA, $rB", IntegerOp,
520 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
509521
510522 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
511523 (Avec VECREG:$rA, VECREG:$rB)>;
512524
513 def Ar32 : RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
514 "a\t$rT, $rA, $rB", IntegerOp,
515 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
525 def Ar32:
526 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
527 "a\t$rT, $rA, $rB", IntegerOp,
528 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
516529
517530 def Ar8:
518531 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
800813 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
801814 "cntb\t$rT, $rA", IntegerOp,
802815 [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
803
804 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
805 def FSMB:
806 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
807 "fsmb\t$rT, $rA", SelectOp,
808 []>;
809
810 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
811 // only 8-bits wide (even though it's input as 16-bits here)
812 def FSMH:
813 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
814 "fsmh\t$rT, $rA", SelectOp,
815 []>;
816
817 // fsm: Form select mask for words. Like the other fsm* instructions,
818 // only the lower 4 bits of $rA are significant.
819 def FSM:
820 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
821 "fsm\t$rT, $rA", SelectOp,
822 []>;
823816
824817 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
825818 // quantity stored into $rT
922915 (XSWDr32 R32C:$inp)>;
923916
924917 // AND operations
925 def ANDv16i8:
926 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
927 "and\t$rT, $rA, $rB", IntegerOp,
928 [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
929 (v16i8 VECREG:$rB)))]>;
930
931 def ANDv8i16:
932 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
933 "and\t$rT, $rA, $rB", IntegerOp,
934 [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
935 (v8i16 VECREG:$rB)))]>;
936
937 def ANDv4i32:
938 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
939 "and\t$rT, $rA, $rB", IntegerOp,
940 [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
941 (v4i32 VECREG:$rB)))]>;
942
943 def ANDr32:
944 RRForm<0b10000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
945 "and\t$rT, $rA, $rB", IntegerOp,
946 [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>;
947
948 //===---------------------------------------------
949 // Special instructions to perform the fabs instruction
950 def ANDfabs32:
951 RRForm<0b10000011000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
952 "and\t$rT, $rA, $rB", IntegerOp,
953 [/* Intentionally does not match a pattern */]>;
954
955 def ANDfabs64:
956 RRForm<0b10000011000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
957 "and\t$rT, $rA, $rB", IntegerOp,
958 [/* Intentionally does not match a pattern */]>;
959
960 // Could use ANDv4i32, but won't for clarity
961 def ANDfabsvec:
962 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
963 "and\t$rT, $rA, $rB", IntegerOp,
964 [/* Intentionally does not match a pattern */]>;
965
966 //===---------------------------------------------
967
968 def ANDr16:
969 RRForm<0b10000011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
970 "and\t$rT, $rA, $rB", IntegerOp,
971 [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>;
972
973 def ANDr8:
974 RRForm<0b10000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
975 "and\t$rT, $rA, $rB", IntegerOp,
976 [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>;
977
978 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
979 // quantities -- see 16->32 zext pattern.
980 //
981 // This pattern is somewhat artificial, since it might match some
982 // compiler generated pattern but it is unlikely to do so.
983 def AND2To4:
984 RRForm<0b10000011000, (outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
985 "and\t$rT, $rA, $rB", IntegerOp,
986 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
918
919 class ANDInst pattern> :
920 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
921 IntegerOp, pattern>;
922
923 class ANDVecInst:
924 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
925 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
926 (vectype VECREG:$rB)))]>;
927
928 multiclass BitwiseAnd
929 {
930 def v16i8: ANDVecInst;
931 def v8i16: ANDVecInst;
932 def v4i32: ANDVecInst;
933 def v2i64: ANDVecInst;
934
935 def r64: ANDInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB),
936 [(set R64C:$rT, (and R64C:$rA, R64C:$rB))]>;
937
938 def r32: ANDInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
939 [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>;
940
941 def r16: ANDInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
942 [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>;
943
944 def r8: ANDInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
945 [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>;
946
947 //===---------------------------------------------
948 // Special instructions to perform the fabs instruction
949 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
950 [/* Intentionally does not match a pattern */]>;
951
952 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
953 [/* Intentionally does not match a pattern */]>;
954
955 // Could use v4i32, but won't for clarity
956 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
957 [/* Intentionally does not match a pattern */]>;
958
959 //===---------------------------------------------
960
961 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
962 // quantities -- see 16->32 zext pattern.
963 //
964 // This pattern is somewhat artificial, since it might match some
965 // compiler generated pattern but it is unlikely to do so.
966
967 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
968 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
969 }
970
971 defm AND : BitwiseAnd;
987972
988973 // N.B.: vnot_conv is one of those special target selection pattern fragments,
989974 // in which we expect there to be a bit_convert on the constant. Bear in mind
990975 // that llvm translates "not " to "xor , -1" (or in this case, a
991976 // constant -1 vector.)
992 def ANDCv16i8:
993 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
994 "andc\t$rT, $rA, $rB", IntegerOp,
995 [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
996 (vnot (v16i8 VECREG:$rB))))]>;
997
998 def ANDCv8i16:
999 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1000 "andc\t$rT, $rA, $rB", IntegerOp,
1001 [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
1002 (vnot (v8i16 VECREG:$rB))))]>;
1003
1004 def ANDCv4i32:
1005 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1006 "andc\t$rT, $rA, $rB", IntegerOp,
1007 [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
1008 (vnot (v4i32 VECREG:$rB))))]>;
1009
1010 def ANDCr32:
1011 RRForm<0b10000011010, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1012 "andc\t$rT, $rA, $rB", IntegerOp,
1013 [(set R32C:$rT, (and R32C:$rA, (not R32C:$rB)))]>;
1014
1015 def ANDCr16:
1016 RRForm<0b10000011010, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1017 "andc\t$rT, $rA, $rB", IntegerOp,
1018 [(set R16C:$rT, (and R16C:$rA, (not R16C:$rB)))]>;
1019
1020 def ANDCr8:
1021 RRForm<0b10000011010, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1022 "andc\t$rT, $rA, $rB", IntegerOp,
1023 [(set R8C:$rT, (and R8C:$rA, (not R8C:$rB)))]>;
1024
1025 def ANDBIv16i8:
1026 RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1027 "andbi\t$rT, $rA, $val", IntegerOp,
1028 [(set (v16i8 VECREG:$rT),
1029 (and (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
1030
1031 def ANDBIr8:
1032 RI10Form<0b01101000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1033 "andbi\t$rT, $rA, $val", IntegerOp,
1034 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1035
1036 def ANDHIv8i16:
1037 RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1038 "andhi\t$rT, $rA, $val", IntegerOp,
1039 [(set (v8i16 VECREG:$rT),
1040 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1041
1042 def ANDHIr16:
1043 RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1044 "andhi\t$rT, $rA, $val", IntegerOp,
1045 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1046
1047 def ANDHI1To2:
1048 RI10Form<0b10101000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1049 "andhi\t$rT, $rA, $val", IntegerOp,
1050 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmSExt10:$val))]>;
1051
1052 def ANDIv4i32:
1053 RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1054 "andi\t$rT, $rA, $val", IntegerOp,
1055 [(set (v4i32 VECREG:$rT),
1056 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1057
1058 def ANDIr32:
1059 RI10Form<0b10101000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1060 "andi\t$rT, $rA, $val", IntegerOp,
1061 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1062
1063 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1064 // pattern below.
1065 def ANDI1To4:
1066 RI10Form<0b10101000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1067 "andi\t$rT, $rA, $val", IntegerOp,
1068 [(set R32C:$rT, (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1069
1070 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1071 // zext 16->32 pattern below.
1072 //
1073 // Note that this pattern is somewhat artificial, since it might match
1074 // something the compiler generates but is unlikely to occur in practice.
1075 def ANDI2To4:
1076 RI10Form<0b10101000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1077 "andi\t$rT, $rA, $val", IntegerOp,
1078 [(set R32C:$rT, (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1079
977
978 class ANDCInst pattern>:
979 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
980 IntegerOp, pattern>;
981
982 class ANDCVecInst:
983 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
984 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
985 (vnot (vectype VECREG:$rB))))]>;
986
987 class ANDCRegInst:
988 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
989 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
990
991 multiclass AndComplement
992 {
993 def v16i8: ANDCVecInst;
994 def v8i16: ANDCVecInst;
995 def v4i32: ANDCVecInst;
996 def v2i64: ANDCVecInst;
997
998 def r128: ANDCRegInst;
999 def r64: ANDCRegInst;
1000 def r32: ANDCRegInst;
1001 def r16: ANDCRegInst;
1002 def r8: ANDCRegInst;
1003 }
1004
1005 defm ANDC : AndComplement;
1006
1007 class ANDBIInst pattern>:
1008 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1009 IntegerOp, pattern>;
1010
1011 multiclass AndByteImm
1012 {
1013 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1014 [(set (v16i8 VECREG:$rT),
1015 (and (v16i8 VECREG:$rA),
1016 (v16i8 v16i8U8Imm:$val)))]>;
1017
1018 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1019 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1020 }
1021
1022 defm ANDBI : AndByteImm;
1023
1024 class ANDHIInst pattern> :
1025 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1026 IntegerOp, pattern>;
1027
1028 multiclass AndHalfwordImm
1029 {
1030 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1031 [(set (v8i16 VECREG:$rT),
1032 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1033
1034 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1035 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1036
1037 // Zero-extend i8 to i16:
1038 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1039 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1040 }
1041
1042 defm ANDHI : AndHalfwordImm;
1043
1044 class ANDIInst pattern> :
1045 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1046 IntegerOp, pattern>;
1047
1048 multiclass AndWordImm
1049 {
1050 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1051 [(set (v4i32 VECREG:$rT),
1052 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1053
1054 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1055 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1056
1057 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1058 // pattern below.
1059 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1060 [(set R32C:$rT,
1061 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1062
1063 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1064 // zext 16->32 pattern below.
1065 //
1066 // Note that this pattern is somewhat artificial, since it might match
1067 // something the compiler generates but is unlikely to occur in practice.
1068 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1069 [(set R32C:$rT,
1070 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1071 }
1072
1073 defm ANDI : AndWordImm;
1074
1075 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
10801076 // Bitwise OR group:
1077 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1078
10811079 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1082 def ORv16i8:
1083 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1084 "or\t$rT, $rA, $rB", IntegerOp,
1085 [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
1086
1087 def ORv8i16:
1088 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1089 "or\t$rT, $rA, $rB", IntegerOp,
1090 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
1091
1092 def ORv4i32:
1093 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1094 "or\t$rT, $rA, $rB", IntegerOp,
1095 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
1096
1097 def ORv4f32:
1098 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1099 "or\t$rT, $rA, $rB", IntegerOp,
1100 [(set (v4f32 VECREG:$rT),
1101 (v4f32 (bitconvert (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))))]>;
1102
1103 def ORv2f64:
1104 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1105 "or\t$rT, $rA, $rB", IntegerOp,
1106 [(set (v2f64 VECREG:$rT),
1107 (v2f64 (bitconvert (or (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)))))]>;
1108
1109 def ORgprc:
1110 RRForm<0b10000010000, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1111 "or\t$rT, $rA, $rB", IntegerOp,
1112 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
1113
1114 def ORr64:
1115 RRForm<0b10000010000, (outs R64C:$rT), (ins R64C:$rA, R64C:$rB),
1116 "or\t$rT, $rA, $rB", IntegerOp,
1117 [(set R64C:$rT, (or R64C:$rA, R64C:$rB))]>;
1118
1119 def ORr32:
1120 RRForm<0b10000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1121 "or\t$rT, $rA, $rB", IntegerOp,
1122 [(set R32C:$rT, (or R32C:$rA, R32C:$rB))]>;
1123
1124 def ORr16:
1125 RRForm<0b10000010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1126 "or\t$rT, $rA, $rB", IntegerOp,
1127 [(set R16C:$rT, (or R16C:$rA, R16C:$rB))]>;
1128
1129 def ORr8:
1130 RRForm<0b10000010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1131 "or\t$rT, $rA, $rB", IntegerOp,
1132 [(set R8C:$rT, (or R8C:$rA, R8C:$rB))]>;
1133
1134 // OR instruction forms that are used to copy f32 and f64 registers.
1135 // They do not match patterns.
1136 def ORf32:
1137 RRForm<0b10000010000, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1138 "or\t$rT, $rA, $rB", IntegerOp,
1139 [/* no pattern */]>;
1140
1141 def ORf64:
1142 RRForm<0b10000010000, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1143 "or\t$rT, $rA, $rB", IntegerOp,
1144 [/* no pattern */]>;
1145
1146 // ORv*_*: Used in scalar->vector promotions:
1147 def ORv16i8_i8:
1148 RRForm<0b10000010000, (outs VECREG:$rT), (ins R8C:$rA, R8C:$rB),
1149 "or\t$rT, $rA, $rB", IntegerOp,
1150 [/* no pattern */]>;
1151
1080 class ORInst pattern>:
1081 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1082 IntegerOp, pattern>;
1083
1084 class ORVecInst:
1085 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1086 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1087 (vectype VECREG:$rB)))]>;
1088
1089 class ORRegInst:
1090 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1091 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1092
1093 class ORPromoteScalar:
1094 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1095 [/* no pattern */]>;
1096
1097 class ORExtractElt:
1098 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1099 [/* no pattern */]>;
1100
1101 multiclass BitwiseOr
1102 {
1103 def v16i8: ORVecInst;
1104 def v8i16: ORVecInst;
1105 def v4i32: ORVecInst;
1106 def v2i64: ORVecInst;
1107
1108 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1109 [(set (v4f32 VECREG:$rT),
1110 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1111 (v4i32 VECREG:$rB)))))]>;
1112
1113 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1114 [(set (v2f64 VECREG:$rT),
1115 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1116 (v2i64 VECREG:$rB)))))]>;
1117
1118 def r64: ORRegInst;
1119 def r32: ORRegInst;
1120 def r16: ORRegInst;
1121 def r8: ORRegInst;
1122
1123 // OR instructions used to copy f32 and f64 registers.
1124 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1125 [/* no pattern */]>;
1126
1127 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1128 [/* no pattern */]>;
1129
1130 // scalar->vector promotion:
1131 def v16i8_i8: ORPromoteScalar;
1132 def v8i16_i16: ORPromoteScalar;
1133 def v4i32_i32: ORPromoteScalar;
1134 def v2i64_i64: ORPromoteScalar;
1135 def v4f32_f32: ORPromoteScalar;
1136 def v2f64_f64: ORPromoteScalar;
1137
1138 // extract element 0:
1139 def i8_v16i8: ORExtractElt;
1140 def i16_v8i16: ORExtractElt;
1141 def i32_v4i32: ORExtractElt;
1142 def i64_v2i64: ORExtractElt;
1143 def f32_v4f32: ORExtractElt;
1144 def f64_v2f64: ORExtractElt;
1145 }
1146
1147 defm OR : BitwiseOr;
1148
1149 // scalar->vector promotion patterns:
11521150 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
11531151 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
11541152
1155 def ORv8i16_i16:
1156 RRForm<0b10000010000, (outs VECREG:$rT), (ins R16C:$rA, R16C:$rB),
1157 "or\t$rT, $rA, $rB", IntegerOp,
1158 [/* no pattern */]>;
1159
11601153 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
11611154 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
11621155
1163 def ORv4i32_i32:
1164 RRForm<0b10000010000, (outs VECREG:$rT), (ins R32C:$rA, R32C:$rB),
1165 "or\t$rT, $rA, $rB", IntegerOp,
1166 [/* no pattern */]>;
1167
11681156 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
11691157 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
11701158
1171 def ORv2i64_i64:
1172 RRForm<0b10000010000, (outs VECREG:$rT), (ins R64C:$rA, R64C:$rB),
1173 "or\t$rT, $rA, $rB", IntegerOp,
1174 [/* no pattern */]>;
1175
11761159 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
11771160 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
11781161
1179 def ORv4f32_f32:
1180 RRForm<0b10000010000, (outs VECREG:$rT), (ins R32FP:$rA, R32FP:$rB),
1181 "or\t$rT, $rA, $rB", IntegerOp,
1182 [/* no pattern */]>;
1183
11841162 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
11851163 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
11861164
1187 def ORv2f64_f64:
1188 RRForm<0b10000010000, (outs VECREG:$rT), (ins R64FP:$rA, R64FP:$rB),
1189 "or\t$rT, $rA, $rB", IntegerOp,
1190 [/* no pattern */]>;
1191
11921165 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
11931166 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
11941167
11951168 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1196 def ORi8_v16i8:
1197 RRForm<0b10000010000, (outs R8C:$rT), (ins VECREG:$rA, VECREG:$rB),
1198 "or\t$rT, $rA, $rB", IntegerOp,
1199 [/* no pattern */]>;
12001169
12011170 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
12021171 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
12041173 def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)),
12051174 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
12061175
1207 def ORi16_v8i16:
1208 RRForm<0b10000010000, (outs R16C:$rT), (ins VECREG:$rA, VECREG:$rB),
1209 "or\t$rT, $rA, $rB", IntegerOp,
1210 [/* no pattern */]>;
1211
12121176 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
12131177 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
12141178
12151179 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
12161180 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
12171181
1218 def ORi32_v4i32:
1219 RRForm<0b10000010000, (outs R32C:$rT), (ins VECREG:$rA, VECREG:$rB),
1220 "or\t$rT, $rA, $rB", IntegerOp,
1221 [/* no pattern */]>;
1222
12231182 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
12241183 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
12251184
12261185 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
12271186 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
12281187
1229 def ORi64_v2i64:
1230 RRForm<0b10000010000, (outs R64C:$rT), (ins VECREG:$rA, VECREG:$rB),
1231 "or\t$rT, $rA, $rB", IntegerOp,
1232 [/* no pattern */]>;
1233
12341188 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
12351189 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
12361190
12371191 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
12381192 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
12391193
1240 def ORf32_v4f32:
1241 RRForm<0b10000010000, (outs R32FP:$rT), (ins VECREG:$rA, VECREG:$rB),
1242 "or\t$rT, $rA, $rB", IntegerOp,
1243 [/* no pattern */]>;
1244
12451194 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
12461195 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
12471196
12481197 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
12491198 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
12501199
1251 def ORf64_v2f64:
1252 RRForm<0b10000010000, (outs R64FP:$rT), (ins VECREG:$rA, VECREG:$rB),
1253 "or\t$rT, $rA, $rB", IntegerOp,
1254 [/* no pattern */]>;
1255
12561200 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
12571201 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
12581202
12591203 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
12601204 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
12611205
1262 // ORC: Bitwise "or" with complement (match before ORvec, ORr32)
1263 def ORCv16i8:
1264 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1265 "orc\t$rT, $rA, $rB", IntegerOp,
1266 [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA),
1267 (vnot (v16i8 VECREG:$rB))))]>;
1268
1269 def ORCv8i16:
1270 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1271 "orc\t$rT, $rA, $rB", IntegerOp,
1272 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
1273 (vnot (v8i16 VECREG:$rB))))]>;
1274
1275 def ORCv4i32:
1276 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1277 "orc\t$rT, $rA, $rB", IntegerOp,
1278 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
1279 (vnot (v4i32 VECREG:$rB))))]>;
1280
1281 def ORCr32:
1282 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1283 "orc\t$rT, $rA, $rB", IntegerOp,
1284 [(set R32C:$rT, (or R32C:$rA, (not R32C:$rB)))]>;
1285
1286 def ORCr16:
1287 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1288 "orc\t$rT, $rA, $rB", IntegerOp,
1289 [(set R16C:$rT, (or R16C:$rA, (not R16C:$rB)))]>;
1290
1291 def ORCr8:
1292 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1293 "orc\t$rT, $rA, $rB", IntegerOp,
1294 [(set R8C:$rT, (or R8C:$rA, (not R8C:$rB)))]>;
1206 // ORC: Bitwise "or" with complement (c = a | ~b)
1207
1208 class ORCInst pattern>:
1209 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1210 IntegerOp, pattern>;
1211
1212 class ORCVecInst:
1213 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1214 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1215 (vnot (vectype VECREG:$rB))))]>;
1216
1217 class ORCRegInst:
1218 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1219 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1220
1221 multiclass BitwiseOrComplement
1222 {
1223 def v16i8: ORCVecInst;
1224 def v8i16: ORCVecInst;
1225 def v4i32: ORCVecInst;
1226 def v2i64: ORCVecInst;
1227
1228 def r64: ORCRegInst;
1229 def r32: ORCRegInst;
1230 def r16: ORCRegInst;
1231 def r8: ORCRegInst;
1232 }
1233
1234 defm ORC : BitwiseOrComplement;
12951235
12961236 // OR byte immediate
1297 def ORBIv16i8:
1298 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1299 "orbi\t$rT, $rA, $val", IntegerOp,
1300 [(set (v16i8 VECREG:$rT),
1301 (or (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
1302
1303 def ORBIr8:
1304 RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1305 "orbi\t$rT, $rA, $val", IntegerOp,
1306 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1237 class ORBIInst pattern>:
1238 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1239 IntegerOp, pattern>;
1240
1241 class ORBIVecInst:
1242 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1243 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1244 (vectype immpred:$val)))]>;
1245
1246 multiclass BitwiseOrByteImm
1247 {
1248 def v16i8: ORBIVecInst;
1249
1250 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1251 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1252 }
1253
1254 defm ORBI : BitwiseOrByteImm;
13071255
13081256 // OR halfword immediate
1309 def ORHIv8i16:
1310 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1311 "orhi\t$rT, $rA, $val", IntegerOp,
1312 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
1313 v8i16Uns10Imm:$val))]>;
1314
1315 def ORHIr16:
1316 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1317 "orhi\t$rT, $rA, $val", IntegerOp,
1318 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1319
1320 // Hacked form of ORHI used to promote 8-bit registers to 16-bit
1321 def ORHI1To2:
1322 RI10Form<0b10100000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1323 "orhi\t$rT, $rA, $val", IntegerOp,
1324 [(set R16C:$rT, (or (anyext R8C:$rA), i16ImmSExt10:$val))]>;
1257 class ORHIInst pattern>:
1258 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1259 IntegerOp, pattern>;
1260
1261 class ORHIVecInst:
1262 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1263 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1264 immpred:$val))]>;
1265
1266 multiclass BitwiseOrHalfwordImm
1267 {
1268 def v8i16: ORHIVecInst;
1269
1270 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1271 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1272
1273 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1274 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1275 [(set R16C:$rT, (or (anyext R8C:$rA),
1276 i16ImmSExt10:$val))]>;
1277 }
1278
1279 defm ORHI : BitwiseOrHalfwordImm;
1280
1281 class ORIInst pattern>:
1282 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1283 IntegerOp, pattern>;
1284
1285 class ORIVecInst:
1286 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1287 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1288 immpred:$val))]>;
13251289
13261290 // Bitwise "or" with immediate
1327 def ORIv4i32:
1328 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1329 "ori\t$rT, $rA, $val", IntegerOp,
1330 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
1331 v4i32Uns10Imm:$val))]>;
1332
1333 def ORIr32:
1334 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1335 "ori\t$rT, $rA, $val", IntegerOp,
1336 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1337
1338 def ORIr64:
1339 RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val),
1340 "ori\t$rT, $rA, $val", IntegerOp,
1341 [/* no pattern */]>;
1342
1343 // ORI2To4: hacked version of the ori instruction to extend 16-bit quantities
1344 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1345 // infra "anyext 16->32" pattern.)
1346 def ORI2To4:
1347 RI10Form<0b00100000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1348 "ori\t$rT, $rA, $val", IntegerOp,
1349 [(set R32C:$rT, (or (anyext R16C:$rA), i32ImmSExt10:$val))]>;
1350
1351 // ORI1To4: Hacked version of the ORI instruction to extend 16-bit quantities
1352 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1353 // infra "anyext 16->32" pattern.)
1354 def ORI1To4:
1355 RI10Form<0b00100000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1356 "ori\t$rT, $rA, $val", IntegerOp,
1357 [(set R32C:$rT, (or (anyext R8C:$rA), i32ImmSExt10:$val))]>;
1291 multiclass BitwiseOrImm
1292 {
1293 def v4i32: ORIVecInst;
1294
1295 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1296 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1297
1298 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1299 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1300 // infra "anyext 16->32" pattern.)
1301 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1302 [(set R32C:$rT, (or (anyext R16C:$rA),
1303 i32ImmSExt10:$val))]>;
1304
1305 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1306 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1307 // infra "anyext 16->32" pattern.)
1308 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1309 [(set R32C:$rT, (or (anyext R8C:$rA),
1310 i32ImmSExt10:$val))]>;
1311 }
1312
1313 defm ORI : BitwiseOrImm;
13581314
13591315 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
13601316 // $rT[0], slots 1-3 are zeroed.
14221378 "xor\t$rT, $rA, $rB", IntegerOp,
14231379 [(set R8C:$rT, (xor R8C:$rA, R8C:$rB))]>;
14241380
1425 def XORBIv16i8:
1426 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1427 "xorbi\t$rT, $rA, $val", IntegerOp,
1428 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1429
1430 def XORBIr8:
1431 RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1432 "xorbi\t$rT, $rA, $val", IntegerOp,
1433 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1381 class XORBIInst pattern>:
1382 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1383 IntegerOp, pattern>;
1384
1385 multiclass XorByteImm
1386 {
1387 def v16i8:
1388 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1389 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1390
1391 def r8:
1392 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1393 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1394 }
1395
1396 defm XORBI : XorByteImm;
14341397
14351398 def XORHIv8i16:
1436 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1399 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
14371400 "xorhi\t$rT, $rA, $val", IntegerOp,
14381401 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
14391402 v8i16SExt10Imm:$val))]>;
14441407 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
14451408
14461409 def XORIv4i32:
1447 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1410 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
14481411 "xori\t$rT, $rA, $val", IntegerOp,
14491412 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
14501413 v4i32SExt10Imm:$val))]>;
16291592 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
16301593 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
16311594 [(set (v16i8 VECREG:$rT),
1632 (SPUselb_v16i8 (v16i8 VECREG:$rA), (v16i8 VECREG:$rB),
1595 (SPUselb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB),
16331596 (v16i8 VECREG:$rC)))]>;
16341597
16351598 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
17001663 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
17011664 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
17021665 [(set (v8i16 VECREG:$rT),
1703 (SPUselb_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB),
1666 (SPUselb (v8i16 VECREG:$rA), (v8i16 VECREG:$rB),
17041667 (v8i16 VECREG:$rC)))]>;
17051668
17061669 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
17711734 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
17721735 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
17731736 [(set (v4i32 VECREG:$rT),
1774 (SPUselb_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB),
1737 (SPUselb (v4i32 VECREG:$rA), (v4i32 VECREG:$rB),
17751738 (v4i32 VECREG:$rC)))]>;
17761739
17771740 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
19531916 //===----------------------------------------------------------------------===//
19541917 // Vector shuffle...
19551918 //===----------------------------------------------------------------------===//
1956
1957 def SHUFB:
1958 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1959 "shufb\t$rT, $rA, $rB, $rC", IntegerOp,
1960 [/* no pattern */]>;
1961
19621919 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
19631920 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
19641921 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
19651922 // the SPUISD::SHUFB opcode.
1966 def : Pat<(SPUshuffle (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), VECREG:$rC),
1967 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1968
1969 def : Pat<(SPUshuffle (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), VECREG:$rC),
1970 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1971
1972 def : Pat<(SPUshuffle (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), VECREG:$rC),
1973 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1974
1975 def : Pat<(SPUshuffle (v4f32 VECREG:$rA), (v4f32 VECREG:$rB), VECREG:$rC),
1976 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1977
1978 def : Pat<(SPUshuffle (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), VECREG:$rC),
1979 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1980
1981 def : Pat<(SPUshuffle (v2f64 VECREG:$rA), (v2f64 VECREG:$rB), VECREG:$rC),
1982 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1923 //===----------------------------------------------------------------------===//
1924
1925 class SHUFBInst pattern>:
1926 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1927 IntegerOp, pattern>;
1928
1929 class SHUFBVecInst:
1930 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1931 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1932 (vectype VECREG:$rB),
1933 (vectype VECREG:$rC)))]>;
1934
1935 // It's this pattern that's probably the most useful, since SPUISelLowering
1936 // methods create a v16i8 vector for $rC:
1937 class SHUFBVecPat1:
1938 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1939 (v16i8 VECREG:$rC)),
1940 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1941
1942 multiclass ShuffleBytes
1943 {
1944 def v16i8 : SHUFBVecInst;
1945 def v8i16 : SHUFBVecInst;
1946 def v4i32 : SHUFBVecInst;
1947 def v2i64 : SHUFBVecInst;
1948
1949 def v4f32 : SHUFBVecInst;
1950 def v2f64 : SHUFBVecInst;
1951 }
1952
1953 defm SHUFB : ShuffleBytes;
1954
1955 def : SHUFBVecPat1;
1956 def : SHUFBVecPat1;
1957 def : SHUFBVecPat1;
1958 def : SHUFBVecPat1;
1959 def : SHUFBVecPat1;
19831960
19841961 //===----------------------------------------------------------------------===//
19851962 // Shift and rotate group:
19861963 //===----------------------------------------------------------------------===//
19871964
1988 def SHLHv8i16:
1989 RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1990 "shlh\t$rT, $rA, $rB", RotateShift,
1991 [(set (v8i16 VECREG:$rT),
1992 (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), R16C:$rB))]>;
1965 class SHLHInst pattern>:
1966 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1967 RotateShift, pattern>;
1968
1969 class SHLHVecInst:
1970 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1971 [(set (vectype VECREG:$rT),
1972 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
19931973
19941974 // $rB gets promoted to 32-bit register type when confronted with
19951975 // this llvm assembly code:
19981978 // %A = shl i16 %arg1, %arg2
19991979 // ret i16 %A
20001980 // }
2001 //
2002 // However, we will generate this code when lowering 8-bit shifts and rotates.
2003
2004 def SHLHr16:
2005 RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2006 "shlh\t$rT, $rA, $rB", RotateShift,
2007 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
2008
2009 def SHLHr16_r32:
2010 RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2011 "shlh\t$rT, $rA, $rB", RotateShift,
2012 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
2013
2014 def SHLHIv8i16:
2015 RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
2016 "shlhi\t$rT, $rA, $val", RotateShift,
2017 [(set (v8i16 VECREG:$rT),
2018 (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)))]>;
2019
2020 def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2021 (SHLHIv8i16 VECREG:$rA, imm:$val)>;
2022
2023 def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2024 (SHLHIv8i16 VECREG:$rA, imm:$val)>;
2025
2026 def SHLHIr16:
2027 RI7Form<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2028 "shlhi\t$rT, $rA, $val", RotateShift,
2029 [(set R16C:$rT, (shl R16C:$rA, (i32 uimm7:$val)))]>;
2030
2031 def : Pat<(shl R16C:$rA, (i8 uimm7:$val)),
1981
1982 multiclass ShiftLeftHalfword
1983 {
1984 def v8i16: SHLHVecInst;
1985 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1986 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1987 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1988 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1989 }
1990
1991 defm SHLH : ShiftLeftHalfword;
1992
1993 //===----------------------------------------------------------------------===//
1994
1995 class SHLHIInst pattern>:
1996 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1997 RotateShift, pattern>;
1998
1999 class SHLHIVecInst:
2000 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2001 [(set (vectype VECREG:$rT),
2002 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2003
2004 multiclass ShiftLeftHalfwordImm
2005 {
2006 def v8i16: SHLHIVecInst;
2007 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2008 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
2009 }
2010
2011 defm SHLHI : ShiftLeftHalfwordImm;
2012
2013 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2014 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
2015
2016 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
20322017 (SHLHIr16 R16C:$rA, uimm7:$val)>;
20332018
2034 def : Pat<(shl R16C:$rA, (i16 uimm7:$val)),
2035 (SHLHIr16 R16C:$rA, uimm7:$val)>;
2036
2037 def SHLv4i32:
2038 RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2039 "shl\t$rT, $rA, $rB", RotateShift,
2040 [(set (v4i32 VECREG:$rT),
2041 (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), R16C:$rB))]>;
2042
2043 def SHLr32:
2044 RRForm<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2045 "shl\t$rT, $rA, $rB", RotateShift,
2046 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
2047
2048 def SHLIv4i32:
2049 RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
2050 "shli\t$rT, $rA, $val", RotateShift,
2051 [(set (v4i32 VECREG:$rT),
2052 (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)))]>;
2053
2054 def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2055 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
2056
2057 def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)),
2058 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
2059
2060 def SHLIr32:
2061 RI7Form<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2062 "shli\t$rT, $rA, $val", RotateShift,
2063 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2064
2065 def : Pat<(shl R32C:$rA, (i16 uimm7:$val)),
2066 (SHLIr32 R32C:$rA, uimm7:$val)>;
2067
2068 def : Pat<(shl R32C:$rA, (i8 uimm7:$val)),
2069 (SHLIr32 R32C:$rA, uimm7:$val)>;
2070
2019 //===----------------------------------------------------------------------===//
2020
2021 class SHLInst pattern>:
2022 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
2023 RotateShift, pattern>;
2024
2025 multiclass ShiftLeftWord
2026 {
2027 def v4i32:
2028 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2029 [(set (v4i32 VECREG:$rT),
2030 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
2031 def r32:
2032 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2033 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
2034 }
2035
2036 defm SHL: ShiftLeftWord;
2037
2038 //===----------------------------------------------------------------------===//
2039
2040 class SHLIInst pattern>:
2041 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
2042 RotateShift, pattern>;
2043
2044 multiclass ShiftLeftWordImm
2045 {
2046 def v4i32:
2047 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2048 [(set (v4i32 VECREG:$rT),
2049 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2050
2051 def r32:
2052 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2053 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2054 }
2055
2056 defm SHLI : ShiftLeftWordImm;
2057
2058 //===----------------------------------------------------------------------===//
20712059 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
20722060 // register) to the left. Vector form is here to ensure type correctness.
2073 def SHLQBIvec:
2074 RRForm<0b11011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2075 "shlqbi\t$rT, $rA, $rB", RotateShift,
2076 [/* intrinsic */]>;
2077
2078 // See note above on SHLQBI.
2079 def SHLQBIIvec:
2080 RI7Form<0b11011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2081 "shlqbii\t$rT, $rA, $val", RotateShift,
2082 [/* intrinsic */]>;
2061 //
2062 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
2063 // of 7 bits is actually possible.
2064 //
2065 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
2066 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
2067 // bytes with SHLQBY.
2068
2069 class SHLQBIInst pattern>:
2070 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
2071 RotateShift, pattern>;
2072
2073 class SHLQBIVecInst:
2074 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2075 [(set (vectype VECREG:$rT),
2076 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
2077
2078 multiclass ShiftLeftQuadByBits
2079 {
2080 def v16i8: SHLQBIVecInst;
2081 def v8i16: SHLQBIVecInst;
2082 def v4i32: SHLQBIVecInst;
2083 def v2i64: SHLQBIVecInst;
2084 }
2085
2086 defm SHLQBI : ShiftLeftQuadByBits;
2087
2088 // See note above on SHLQBI. In this case, the predicate actually does then
2089 // enforcement, whereas with SHLQBI, we have to "take it on faith."
2090 class SHLQBIIInst pattern>:
2091 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
2092 RotateShift, pattern>;
2093
2094 class SHLQBIIVecInst:
2095 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2096 [(set (vectype VECREG:$rT),
2097 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
2098
2099 multiclass ShiftLeftQuadByBitsImm
2100 {
2101 def v16i8 : SHLQBIIVecInst;
2102 def v8i16 : SHLQBIIVecInst;
2103 def v4i32 : SHLQBIIVecInst;
2104 def v2i64 : SHLQBIIVecInst;
2105 }
2106
2107 defm SHLQBII : ShiftLeftQuadByBitsImm;
20832108
20842109 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
2085 // not by bits.
2086 def SHLQBYvec:
2087 RI7Form<0b11111011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2088 "shlqbyi\t$rT, $rA, $rB", RotateShift,
2089 [/* intrinsic */]>;
2090
2091 def SHLQBYIvec:
2092 RI7Form<0b11111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2093 "shlqbyi\t$rT, $rA, $val", RotateShift,
2094 [/* intrinsic */]>;
2095
2096 // ROTH v8i16 form:
2097 def ROTHv8i16:
2098 RRForm<0b00111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2099 "roth\t$rT, $rA, $rB", RotateShift,
2100 [(set (v8i16 VECREG:$rT),
2101 (SPUvec_rotl_v8i16 VECREG:$rA, VECREG:$rB))]>;
2102
2103 def ROTHr16:
2104 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2105 "roth\t$rT, $rA, $rB", RotateShift,
2106 [(set R16C:$rT, (rotl R16C:$rA, R16C:$rB))]>;
2107
2108 def ROTHr16_r32:
2109 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2110 "roth\t$rT, $rA, $rB", RotateShift,
2111 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2112
2113 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2114 // 32-bit register
2115 def ROTHr16_r8:
2116 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R8C:$rB),
2117 "roth\t$rT, $rA, $rB", RotateShift,
2118 [(set R16C:$rT, (rotl R16C:$rA, (i32 (zext R8C:$rB))))]>;
2119
2120 def : Pat<(rotl R16C:$rA, (i32 (sext R8C:$rB))),
2121 (ROTHr16_r8 R16C:$rA, R8C:$rB)>;
2122
2123 def : Pat<(rotl R16C:$rA, (i32 (zext R8C:$rB))),
2124 (ROTHr16_r8 R16C:$rA, R8C:$rB)>;
2125
2126 def : Pat<(rotl R16C:$rA, (i32 (anyext R8C:$rB))),
2127 (ROTHr16_r8 R16C:$rA, R8C:$rB)>;
2128
2129 def ROTHIv8i16:
2130 RI7Form<0b00111110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
2131 "rothi\t$rT, $rA, $val", RotateShift,
2132 [(set (v8i16 VECREG:$rT),
2133 (SPUvec_rotl_v8i16 VECREG:$rA, (i8 uimm7:$val)))]>;
2134
2135 def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i16 uimm7:$val)),
2136 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2137
2138 def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i32 uimm7:$val)),
2110 // not by bits. See notes above on SHLQBI.
2111
2112 class SHLQBYInst pattern>:
2113 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
2114 RotateShift, pattern>;
2115
2116 class SHLQBYVecInst:
2117 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2118 [(set (vectype VECREG:$rT),
2119 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
2120
2121 multiclass ShiftLeftQuadBytes
2122 {
2123 def v16i8: SHLQBYVecInst;
2124 def v8i16: SHLQBYVecInst;
2125 def v4i32: SHLQBYVecInst;
2126 def v2i64: SHLQBYVecInst;
2127 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
2128 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
2129 }
2130
2131 defm SHLQBY: ShiftLeftQuadBytes;
2132
2133 class SHLQBYIInst pattern>:
2134 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
2135 RotateShift, pattern>;
2136
2137 class SHLQBYIVecInst:
2138 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2139 [(set (vectype VECREG:$rT),
2140 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2141
2142 multiclass ShiftLeftQuadBytesImm
2143 {
2144 def v16i8: SHLQBYIVecInst;
2145 def v8i16: SHLQBYIVecInst;
2146 def v4i32: SHLQBYIVecInst;
2147 def v2i64: SHLQBYIVecInst;
2148 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
2149 [(set GPRC:$rT,
2150 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
2151 }
2152
2153 defm SHLQBYI : ShiftLeftQuadBytesImm;
2154
2155 // Special form for truncating i64 to i32:
2156 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
2157 [/* no pattern, see below */]>;
2158
2159 def : Pat<(trunc R64C:$rSrc),
2160 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
2161
2162 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2163 // Rotate halfword:
2164 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2165 class ROTHInst pattern>:
2166 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2167 RotateShift, pattern>;
2168
2169 class ROTHVecInst:
2170 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2171 [(set (vectype VECREG:$rT),
2172 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2173
2174 class ROTHRegInst:
2175 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2176 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2177
2178 multiclass RotateLeftHalfword
2179 {
2180 def v8i16: ROTHVecInst;
2181 def r16: ROTHRegInst;
2182 }
2183
2184 defm ROTH: RotateLeftHalfword;
2185
2186 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2187 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2188
2189 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2190 // Rotate halfword, immediate:
2191 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2192 class ROTHIInst pattern>:
2193 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2194 RotateShift, pattern>;
2195
2196 class ROTHIVecInst:
2197 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2198 [(set (vectype VECREG:$rT),
2199 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2200
2201 multiclass RotateLeftHalfwordImm
2202 {
2203 def v8i16: ROTHIVecInst;
2204 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2205 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2206 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2207 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2208 }
2209
2210 defm ROTHI: RotateLeftHalfwordImm;
2211
2212 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
21392213 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
21402214
2141 def ROTHIr16:
2142 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2143 "rothi\t$rT, $rA, $val", RotateShift,
2144 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2145
2146 def ROTHIr16_i32:
2147 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2148 "rothi\t$rT, $rA, $val", RotateShift,
2149 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2150
2151 def ROTHIr16_i8:
2152 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i8:$val),
2153 "rothi\t$rT, $rA, $val", RotateShift,
2154 [(set R16C:$rT, (rotl R16C:$rA, (i8 uimm7:$val)))]>;
2155
2156 def ROTv4i32:
2157 RRForm<0b00011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2158 "rot\t$rT, $rA, $rB", RotateShift,
2159 [(set (v4i32 VECREG:$rT),
2160 (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), R32C:$rB))]>;
2161
2162 def ROTr32:
2163 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2164 "rot\t$rT, $rA, $rB", RotateShift,
2165 [(set R32C:$rT, (rotl R32C:$rA, R32C:$rB))]>;
2215 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2216 // Rotate word:
2217 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2218
2219 class ROTInst pattern>:
2220 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2221 RotateShift, pattern>;
2222
2223 class ROTVecInst:
2224 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2225 [(set (vectype VECREG:$rT),
2226 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2227
2228 class ROTRegInst:
2229 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2230 [(set rclass:$rT,
2231 (rotl rclass:$rA, R32C:$rB))]>;
2232
2233 multiclass RotateLeftWord
2234 {
2235 def v4i32: ROTVecInst;
2236 def r32: ROTRegInst;
2237 }
2238
2239 defm ROT: RotateLeftWord;
21662240
21672241 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
21682242 // 32-bit register
21692243 def ROTr32_r16_anyext:
2170 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2171 "rot\t$rT, $rA, $rB", RotateShift,
2172 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2244 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2245 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
21732246
21742247 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
21752248 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
21782251 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
21792252
21802253 def ROTr32_r8_anyext:
2181 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2182 "rot\t$rT, $rA, $rB", RotateShift,
2183 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2254 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2255 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
21842256
21852257 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
21862258 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
21882260 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
21892261 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
21902262
2191 def ROTIv4i32:
2192 RI7Form<0b00011110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2193 "roti\t$rT, $rA, $val", RotateShift,
2194 [(set (v4i32 VECREG:$rT),
2195 (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2196
2197 def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2198 (ROTIv4i32 VECREG:$rA, imm:$val)>;
2199
2200 def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)),
2201 (ROTIv4i32 VECREG:$rA, imm:$val)>;
2202
2203 def ROTIr32:
2204 RI7Form<0b00011110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2205 "roti\t$rT, $rA, $val", RotateShift,
2206 [(set R32C:$rT, (rotl R32C:$rA, (i32 uimm7:$val)))]>;
2207
2208 def ROTIr32_i16:
2209 RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm:$val),
2210 "roti\t$rT, $rA, $val", RotateShift,
2211 [(set R32C:$rT, (rotl R32C:$rA, (i16 uimm7:$val)))]>;
2212
2213 def ROTIr32_i8:
2214 RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i8:$val),
2215 "roti\t$rT, $rA, $val", RotateShift,
2216 [(set R32C:$rT, (rotl R32C:$rA, (i8 uimm7:$val)))]>;
2217
2218 // ROTQBY* vector forms: This rotates the entire vector, but vector registers
2219 // are used here for type checking (instances where ROTQBI is used actually
2220 // use vector registers)
2221 def ROTQBYvec:
2222 RRForm<0b00111011100, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2223 "rotqby\t$rT, $rA, $rB", RotateShift,
2224 [(set (v16i8 VECREG:$rT), (SPUrotbytes_left (v16i8 VECREG:$rA), R32C:$rB))]>;
2263 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2264 // Rotate word, immediate
2265 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2266
2267 class ROTIInst pattern>:
2268 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2269 RotateShift, pattern>;
2270
2271 class ROTIVecInst:
2272 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2273 [(set (vectype VECREG:$rT),
2274 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2275
2276 class ROTIRegInst:
2277 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2278 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2279
2280 multiclass RotateLeftWordImm
2281 {
2282 def v4i32: ROTIVecInst;
2283 def v4i32_i16: ROTIVecInst;
2284 def v4i32_i8: ROTIVecInst;
2285
2286 def r32: ROTIRegInst;
2287 def r32_i16: ROTIRegInst;
2288 def r32_i8: ROTIRegInst;
2289 }
2290
2291 defm ROTI : RotateLeftWordImm;
2292
2293 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2294 // Rotate quad by byte (count)
2295 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2296
2297 class ROTQBYInst pattern>:
2298 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2299 RotateShift, pattern>;
2300
2301 class ROTQBYVecInst:
2302 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2303 [(set (vectype VECREG:$rT),
2304 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2305
2306 multiclass RotateQuadLeftByBytes
2307 {
2308 def v16i8: ROTQBYVecInst;
2309 def v8i16: ROTQBYVecInst;
2310 def v4i32: ROTQBYVecInst;
2311 def v2i64: ROTQBYVecInst;
2312 }
2313
2314 defm ROTQBY: RotateQuadLeftByBytes;
22252315
22262316 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2227 (ROTQBYvec VECREG:$rA, R32C:$rB)>;
2228
2229 // See ROTQBY note above.
2230 def ROTQBYIvec:
2231 RI7Form<0b00111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2232 "rotqbyi\t$rT, $rA, $val", RotateShift,
2233 [(set (v16i8 VECREG:$rT),
2234 (SPUrotbytes_left (v16i8 VECREG:$rA), (i16 uimm7:$val)))]>;
2317 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2318 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2319 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2320 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2321 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2322 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2323 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2324
2325 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2326 // Rotate quad by byte (count), immediate
2327 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2328
2329 class ROTQBYIInst pattern>:
2330 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2331 RotateShift, pattern>;
2332
2333 class ROTQBYIVecInst:
2334 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2335 [(set (vectype VECREG:$rT),
2336 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2337
2338 multiclass RotateQuadByBytesImm
2339 {
2340 def v16i8: ROTQBYIVecInst;
2341 def v8i16: ROTQBYIVecInst;
2342 def v4i32: ROTQBYIVecInst;
2343 def v2i64: ROTQBYIVecInst;
2344 }
2345
2346 defm ROTQBYI: RotateQuadByBytesImm;
22352347
22362348 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2237 (ROTQBYIvec VECREG:$rA, uimm7:$val)>;
2349 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2350 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2351 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2352 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2353 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2354 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2355 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
22382356
22392357 // See ROTQBY note above.
22402358 def ROTQBYBIvec:
22422360 "rotqbybi\t$rT, $rA, $val", RotateShift,
22432361 [/* intrinsic */]>;
22442362
2363 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
22452364 // See ROTQBY note above.
22462365 //
22472366 // Assume that the user of this instruction knows to shift the rotate count
22482367 // into bit 29
2249 def ROTQBIvec:
2250 RRForm<0b00011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2251 "rotqbi\t$rT, $rA, $rB", RotateShift,
2252 [/* insert intrinsic here */]>;
2253
2254 // See ROTQBY note above.
2255 def ROTQBIIvec:
2256 RI7Form<0b00011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2257 "rotqbii\t$rT, $rA, $val", RotateShift,
2258 [/* insert intrinsic here */]>;
2259
2368 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2369
2370 class ROTQBIInst pattern>:
2371 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2372 RotateShift, pattern>;
2373
2374 class ROTQBIVecInst:
2375 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2376 [/* no pattern yet */]>;
2377
2378 class ROTQBIRegInst:
2379 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2380 [/* no pattern yet */]>;
2381
2382 multiclass RotateQuadByBitCount
2383 {
2384 def v16i8: ROTQBIVecInst;
2385 def v8i16: ROTQBIVecInst;
2386 def v4i32: ROTQBIVecInst;
2387 def v2i64: ROTQBIVecInst;
2388
2389 def r128: ROTQBIRegInst;
2390 def r64: ROTQBIRegInst;
2391 }
2392
2393 defm ROTQBI: RotateQuadByBitCount;
2394
2395 class ROTQBIIInst pattern>:
2396 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2397 RotateShift, pattern>;
2398
2399 class ROTQBIIVecInst
2400 PatLeaf pred>:
2401 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2402 [/* no pattern yet */]>;
2403
2404 class ROTQBIIRegInst
2405 PatLeaf pred>:
2406 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2407 [/* no pattern yet */]>;
2408
2409 multiclass RotateQuadByBitCountImm
2410 {
2411 def v16i8: ROTQBIIVecInst;
2412 def v8i16: ROTQBIIVecInst;
2413 def v4i32: ROTQBIIVecInst;
2414 def v2i64: ROTQBIIVecInst;
2415
2416 def r128: ROTQBIIRegInst;
2417 def r64: ROTQBIIRegInst;
2418 }
2419
2420 defm ROTQBII : RotateQuadByBitCountImm;
2421
2422 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
22602423 // ROTHM v8i16 form:
22612424 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
22622425 // so this only matches a synthetically generated/lowered code
22632426 // fragment.
22642427 // NOTE(2): $rB must be negated before the right rotate!
2428 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2429
2430 class ROTHMInst pattern>:
2431 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2432 RotateShift, pattern>;
2433
22652434 def ROTHMv8i16:
2266 RRForm<0b10111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2267 "rothm\t$rT, $rA, $rB", RotateShift,
2268 [/* see patterns below - $rB must be negated */]>;
2269
2270 def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R32C:$rB),
2435 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2436 [/* see patterns below - $rB must be negated */]>;
2437
2438 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
22712439 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
22722440
2273 def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R16C:$rB),
2441 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
22742442 (ROTHMv8i16 VECREG:$rA,
22752443 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
22762444
2277 def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R8C:$rB),
2445 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
22782446 (ROTHMv8i16 VECREG:$rA,
22792447 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
22802448
22812449 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
22822450 // Note: This instruction doesn't match a pattern because rB must be negated
22832451 // for the instruction to work. Thus, the pattern below the instruction!
2452
22842453 def ROTHMr16:
2285 RRForm<0b10111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2286 "rothm\t$rT, $rA, $rB", RotateShift,
2287 [/* see patterns below - $rB must be negated! */]>;
2454 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2455 [/* see patterns below - $rB must be negated! */]>;
22882456
22892457 def : Pat<(srl R16C:$rA, R32C:$rB),
22902458 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
23002468 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
23012469 // that the immediate can be complemented, so that the user doesn't have to
23022470 // worry about it.
2471
2472 class ROTHMIInst pattern>:
2473 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2474 RotateShift, pattern>;
2475
23032476 def ROTHMIv8i16:
2304 RI7Form<0b10111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2305 "rothmi\t$rT, $rA, $val", RotateShift,
2306 [(set (v8i16 VECREG:$rT),
2307 (SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i32 imm:$val)))]>;
2308
2309 def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i16 imm:$val)),
2477 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2478 [/* no pattern */]>;
2479
2480 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2481 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2482
2483 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
23102484 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
23112485
2312 def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i8 imm:$val)),
2486 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
23132487 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
23142488
23152489 def ROTHMIr16:
2316 RI7Form<0b10111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2317 "rothmi\t$rT, $rA, $val", RotateShift,
2318 [(set R16C:$rT, (srl R16C:$rA, (i32 uimm7:$val)))]>;
2490 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2491 [/* no pattern */]>;
2492
2493 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2494 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
23192495
23202496 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
23212497 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
23242500 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
23252501
23262502 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2503 class ROTMInst pattern>:
2504 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2505 RotateShift, pattern>;
2506
23272507 def ROTMv4i32:
2328 RRForm<0b10011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2329 "rotm\t$rT, $rA, $rB", RotateShift,
2330 [/* see patterns below - $rB must be negated */]>;
2331
2332 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R32C:$rB),
2508 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2509 [/* see patterns below - $rB must be negated */]>;
2510
2511 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
23332512 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
23342513
2335 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R16C:$rB),
2514 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
23362515 (ROTMv4i32 VECREG:$rA,
23372516 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
23382517
2339 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, /* R8C */ R16C:$rB),
2518 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
23402519 (ROTMv4i32 VECREG:$rA,
2341 (SFIr32 (XSHWr16 /* (XSBHr8 R8C */ R16C:$rB) /*)*/, 0))>;
2520 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
23422521
23432522 def ROTMr32:
2344 RRForm<0b10011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2345 "rotm\t$rT, $rA, $rB", RotateShift,
2346 [/* see patterns below - $rB must be negated */]>;
2523 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2524 [/* see patterns below - $rB must be negated */]>;
23472525
23482526 def : Pat<(srl R32C:$rA, R32C:$rB),
23492527 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
23612539 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
23622540 "rotmi\t$rT, $rA, $val", RotateShift,
23632541 [(set (v4i32 VECREG:$rT),
2364 (SPUvec_srl_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
2365
2366 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i16 uimm7:$val)),
2542 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2543
2544 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
23672545 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
23682546
2369 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i8 uimm7:$val)),
2547 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
23702548 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
23712549
23722550 // ROTMI r32 form: know how to complement the immediate value.
23812559 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
23822560 (ROTMIr32 R32C:$rA, uimm7:$val)>;
23832561
2562 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
23842563 // ROTQMBYvec: This is a vector form merely so that when used in an
23852564 // instruction pattern, type checking will succeed. This instruction assumes
2386 // that the user knew to complement $rB.
2387 def ROTQMBYvec:
2388 RRForm<0b10111011100, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2389 "rotqmby\t$rT, $rA, $rB", RotateShift,
2390 [(set (v16i8 VECREG:$rT),
2391 (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), R32C:$rB))]>;
2392
2393 def ROTQMBYIvec:
2394 RI7Form<0b10111111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2395 "rotqmbyi\t$rT, $rA, $val", RotateShift,
2396 [(set (v16i8 VECREG:$rT),
2397 (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), (i32 uimm7:$val)))]>;
2398
2399 def : Pat<(SPUrotbytes_right_zfill VECREG:$rA, (i16 uimm7:$val)),
2400 (ROTQMBYIvec VECREG:$rA, uimm7:$val)>;
2401
2402 def ROTQMBYBIvec:
2403 RRForm<0b10110011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2404 "rotqmbybi\t$rT, $rA, $rB", RotateShift,
2405 [/* intrinsic */]>;
2406
2407 def ROTQMBIvec:
2408 RRForm<0b10011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2409 "rotqmbi\t$rT, $rA, $rB", RotateShift,
2410 [/* intrinsic */]>;
2411
2412 def ROTQMBIIvec:
2413 RI7Form<0b10011111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2414 "rotqmbii\t$rT, $rA, $val", RotateShift,
2415 [/* intrinsic */]>;
2565 // that the user knew to negate $rB.
2566 //
2567 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2568 // ensure that $rB is negated.
2569 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2570
2571 class ROTQMBYInst pattern>:
2572 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2573 RotateShift, pattern>;
2574
2575 class ROTQMBYVecInst:
2576 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2577 [/* no pattern, $rB must be negated */]>;
2578
2579 class ROTQMBYRegInst:
2580 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2581 [(set rclass:$rT,
2582 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2583
2584 multiclass RotateQuadBytes
2585 {
2586 def v16i8: ROTQMBYVecInst;
2587 def v8i16: ROTQMBYVecInst;
2588 def v4i32: ROTQMBYVecInst;
2589 def v2i64: ROTQMBYVecInst;
2590
2591 def r128: ROTQMBYRegInst;
2592 def r64: ROTQMBYRegInst;
2593 }
2594
2595 defm ROTQMBY : RotateQuadBytes;
2596
2597 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2598 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2599 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2600 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2601 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2602 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2603 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2604 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2605 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2606 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2607 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2608 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2609
2610 class ROTQMBYIInst pattern>:
2611 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2612 RotateShift, pattern>;
2613
2614 class ROTQMBYIVecInst:
2615 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2616 [(set (vectype VECREG:$rT),
2617 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2618
2619 class ROTQMBYIRegInst:
2620 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2621 [(set rclass:$rT,
2622 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2623
2624 multiclass RotateQuadBytesImm
2625 {
2626 def v16i8: ROTQMBYIVecInst;
2627 def v8i16: ROTQMBYIVecInst;
2628 def v4i32: ROTQMBYIVecInst;
2629 def v2i64: ROTQMBYIVecInst;
2630
2631 def r128: ROTQMBYIRegInst;
2632 def r64: ROTQMBYIRegInst;
2633 }
2634
2635 defm ROTQMBYI : RotateQuadBytesImm;
2636
2637
2638 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2639 // Rotate right and mask by bit count
2640 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2641
2642 class ROTQMBYBIInst pattern>:
2643 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2644 RotateShift, pattern>;
2645
2646 class ROTQMBYBIVecInst:
2647 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2648 [/* no pattern, intrinsic? */]>;
2649
2650 multiclass RotateMaskQuadByBitCount
2651 {
2652 def v16i8: ROTQMBYBIVecInst;
2653 def v8i16: ROTQMBYBIVecInst;
2654 def v4i32: ROTQMBYBIVecInst;
2655 def v2i64: ROTQMBYBIVecInst;
2656 }
2657
2658 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2659
2660 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2661 // Rotate quad and mask by bits
2662 // Note that the rotate amount has to be negated
2663 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2664
2665 class ROTQMBIInst pattern>:
2666 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2667 RotateShift, pattern>;
2668
2669 class ROTQMBIVecInst:
2670 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2671 [/* no pattern */]>;
2672
2673 class ROTQMBIRegInst:
2674 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2675 [/* no pattern */]>;
2676
2677 multiclass RotateMaskQuadByBits
2678 {
2679 def v16i8: ROTQMBIVecInst;
2680 def v8i16: ROTQMBIVecInst;
2681 def v4i32: ROTQMBIVecInst;
2682 def v2i64: ROTQMBIVecInst;
2683
2684 def r128: ROTQMBIRegInst;
2685 def r64: ROTQMBIRegInst;
2686 }
2687
2688 defm ROTQMBI: RotateMaskQuadByBits;
2689
2690 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2691 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2692 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2693 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2694 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2695 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2696 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2697 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2698 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2699 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2700 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2701 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2702
2703 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2704 // Rotate quad and mask by bits, immediate
2705 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2706
2707 class ROTQMBIIInst pattern>:
2708 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2709 RotateShift, pattern>;
2710
2711 class ROTQMBIIVecInst:
2712 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2713 [(set (vectype VECREG:$rT),
2714 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2715
2716 class ROTQMBIIRegInst:
2717 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2718 [(set rclass:$rT,
2719 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2720
2721 multiclass RotateMaskQuadByBitsImm
2722 {
2723 def v16i8: ROTQMBIIVecInst;
2724 def v8i16: ROTQMBIIVecInst;
2725 def v4i32: ROTQMBIIVecInst;
2726 def v2i64: ROTQMBIIVecInst;
2727
2728 def r128: ROTQMBIIRegInst;
2729 def r64: ROTQMBIIRegInst;
2730 }
2731
2732 defm ROTQMBII: RotateMaskQuadByBitsImm;
2733
2734 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2735 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
24162736
24172737 def ROTMAHv8i16:
24182738 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
24192739 "rotmah\t$rT, $rA, $rB", RotateShift,
24202740 [/* see patterns below - $rB must be negated */]>;
24212741
2422 def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R32C:$rB),
2742 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
24232743 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
24242744
2425 def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R16C:$rB),
2745 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
24262746 (ROTMAHv8i16 VECREG:$rA,
24272747 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
24282748
2429 def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R8C:$rB),
2749 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
24302750 (ROTMAHv8i16 VECREG:$rA,
24312751 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
24322752
24502770 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
24512771 "rotmahi\t$rT, $rA, $val", RotateShift,
24522772 [(set (v8i16 VECREG:$rT),
2453 (SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2454
2455 def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2773 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2774
2775 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
24562776 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
24572777
2458 def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2778 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
24592779 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
24602780
24612781 def ROTMAHIr16:
24742794 "rotma\t$rT, $rA, $rB", RotateShift,
24752795 [/* see patterns below - $rB must be negated */]>;
24762796
2477 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R32C:$rB),
2797 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
24782798 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
24792799
2480 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R16C:$rB),
2800 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
24812801 (ROTMAv4i32 (v4i32 VECREG:$rA),
24822802 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
24832803
2484 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R8C:$rB),
2804 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
24852805 (ROTMAv4i32 (v4i32 VECREG:$rA),
24862806 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
24872807
25052825 RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
25062826 "rotmai\t$rT, $rA, $val", RotateShift,
25072827 [(set (v4i32 VECREG:$rT),
2508 (SPUvec_sra_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
2509
2510 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, (i16 uimm7:$val)),
2828 (SPUvec_sra VECREG:$rA, (i32 uimm7:$val)))]>;
2829
2830 def : Pat<(SPUvec_sra VECREG:$rA, (i16 uimm7:$val)),
25112831 (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
25122832
25132833 def ROTMAIr32:
25602880 [/* no pattern to match */]>;
25612881 }
25622882
2883 //------------------------------------------------------------------------
25632884 // Comparison operators:
2564 def CEQBr8:
2565 RRForm<0b00001011110, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2566 "ceqb\t$rT, $rA, $rB", ByteOp,
2567 [/* no pattern to match */]>;
2568
2569 def CEQBv16i8:
2570 RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2571 "ceqb\t$rT, $rA, $rB", ByteOp,
2572 [/* no pattern to match: intrinsic */]>;
2573
2574 def CEQBIr8:
2575 RI10Form<0b01111110, (outs R8C:$rT), (ins R8C:$rA, s7imm_i8:$val),
2576 "ceqbi\t$rT, $rA, $val", ByteOp,
2577 [/* no pattern to match: intrinsic */]>;
2578
2579 def CEQBIv16i8:
2580 RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, s7imm_i8:$val),
2581 "ceqbi\t$rT, $rA, $val", ByteOp,
2582 [/* no pattern to match: intrinsic */]>;
2583
2584 def CEQHr16:
2585 RRForm<0b00010011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2586 "ceqh\t$rT, $rA, $rB", ByteOp,
2587 [/* no pattern to match */]>;
2588
2589 def CEQHv8i16:
2590 RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2591 "ceqh\t$rT, $rA, $rB", ByteOp,
2592 [/* no pattern to match: intrinsic */]>;
2593
2594 def CEQHIr16:
2595 RI10Form<0b10111110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2596 "ceqhi\t$rT, $rA, $val", ByteOp,
2597 [/* no pattern to match: intrinsic */]>;
2598
2599 def CEQHIv8i16:
2600 RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2601 "ceqhi\t$rT, $rA, $val", ByteOp,
2602 [/* no pattern to match: intrinsic */]>;
2603
2604 def CEQr32:
2605 RRForm<0b00000011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2606 "ceq\t$rT, $rA, $rB", ByteOp,
2607 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2608
2609 def CEQv4i32:
2610 RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2611 "ceq\t$rT, $rA, $rB", ByteOp,
2612 [(set (v4i32 VECREG:$rT), (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2613
2614 def CEQIr32:
2615 RI10Form<0b00111110, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2616 "ceqi\t$rT, $rA, $val", ByteOp,
2617 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2618
2619 def CEQIv4i32:
2620 RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2621 "ceqi\t$rT, $rA, $val", ByteOp,
2622 [/* no pattern to match: intrinsic */]>;
2885 //------------------------------------------------------------------------
2886
2887 class CEQBInst pattern> :
2888 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2889 ByteOp, pattern>;
2890
2891 multiclass CmpEqualByte
2892 {
2893 def v16i8 :
2894 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2895 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2896 (v8i16 VECREG:$rB)))]>;
2897
2898 def r8 :
2899 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2900 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2901 }
2902
2903 class CEQBIInst pattern> :
2904 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2905 ByteOp, pattern>;
2906
2907 multiclass CmpEqualByteImm
2908 {
2909 def v16i8 :
2910 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2911 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2912 v16i8SExt8Imm:$val))]>;
2913 def r8:
2914 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2915 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2916 }
2917
2918 class CEQHInst pattern> :
2919 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2920 ByteOp, pattern>;
2921
2922 multiclass CmpEqualHalfword
2923 {
2924 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2925 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2926 (v8i16 VECREG:$rB)))]>;
2927
2928 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2929 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2930 }
2931
2932 class CEQHIInst pattern> :
2933 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2934 ByteOp, pattern>;
2935
2936 multiclass CmpEqualHalfwordImm
2937 {
2938 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2939 [(set (v8i16 VECREG:$rT),
2940 (seteq (v8i16 VECREG:$rA),
2941 (v8i16 v8i16SExt10Imm:$val)))]>;
2942 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2943 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2944 }
2945
2946 class CEQInst pattern> :
2947 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2948 ByteOp, pattern>;
2949
2950 multiclass CmpEqualWord
2951 {
2952 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2953 [(set (v4i32 VECREG:$rT),
2954 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2955
2956 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2957 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2958 }
2959
2960 class CEQIInst pattern> :
2961 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2962 ByteOp, pattern>;
2963
2964 multiclass CmpEqualWordImm
2965 {
2966 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2967 [(set (v4i32 VECREG:$rT),
2968 (seteq (v4i32 VECREG:$rA),
2969 (v4i32 v4i32SExt16Imm:$val)))]>;
2970
2971 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2972 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2973 }
2974
2975 class CGTBInst pattern> :
2976 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2977 ByteOp, pattern>;
2978
2979 multiclass CmpGtrByte
2980 {
2981 def v16i8 :
2982 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2983 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2984 (v8i16 VECREG:$rB)))]>;
2985
2986 def r8 :
2987 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2988 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2989 }
2990
2991 class CGTBIInst pattern> :
2992 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2993 ByteOp, pattern>;
2994
2995 multiclass CmpGtrByteImm
2996 {
2997 def v16i8 :
2998 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2999 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
3000 v16i8SExt8Imm:$val))]>;
3001 def r8:
3002 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3003 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
3004 }
3005
3006 class CGTHInst pattern> :
3007 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
3008 ByteOp, pattern>;
3009
3010 multiclass CmpGtrHalfword
3011 {
3012 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3013 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3014 (v8i16 VECREG:$rB)))]>;
3015
3016 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3017 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
3018 }
3019
3020 class CGTHIInst pattern> :
3021 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
3022 ByteOp, pattern>;
3023
3024 multiclass CmpGtrHalfwordImm
3025 {
3026 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3027 [(set (v8i16 VECREG:$rT),
3028 (setgt (v8i16 VECREG:$rA),
3029 (v8i16 v8i16SExt10Imm:$val)))]>;
3030 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3031 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
3032 }
3033
3034 class CGTInst pattern> :
3035 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
3036 ByteOp, pattern>;
3037
3038 multiclass CmpGtrWord
3039 {
3040 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3041 [(set (v4i32 VECREG:$rT),
3042 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3043
3044 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3045 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
3046 }
3047
3048 class CGTIInst pattern> :
3049 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
3050 ByteOp, pattern>;
3051
3052 multiclass CmpGtrWordImm
3053 {
3054 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3055 [(set (v4i32 VECREG:$rT),
3056 (setgt (v4i32 VECREG:$rA),
3057 (v4i32 v4i32SExt16Imm:$val)))]>;
3058
3059 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3060 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
3061 }
3062
3063 class CLGTBInst pattern> :
3064 RRForm<0b00001011010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
3065 ByteOp, pattern>;
3066
3067 multiclass CmpLGtrByte
3068 {
3069 def v16i8 :
3070 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3071 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3072 (v8i16 VECREG:$rB)))]>;
3073
3074 def r8 :
3075 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3076 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
3077 }
3078
3079 class CLGTBIInst pattern> :
3080 RI10Form<0b01111010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
3081 ByteOp, pattern>;
3082
3083 multiclass CmpLGtrByteImm
3084 {
3085 def v16i8 :
3086 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3087 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
3088 v16i8SExt8Imm:$val))]>;
3089 def r8:
3090 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3091 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
3092 }
3093
3094 class CLGTHInst pattern> :
3095 RRForm<0b00010011010, OOL, IOL, "cgth\t$rT, $rA, $rB",
3096 ByteOp, pattern>;
3097
3098 multiclass CmpLGtrHalfword
3099 {
3100 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3101 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3102 (v8i16 VECREG:$rB)))]>;
3103
3104 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3105 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
3106 }
3107
3108 class CLGTHIInst pattern> :
3109 RI10Form<0b10111010, OOL, IOL, "cgthi\t$rT, $rA, $val",
3110 ByteOp, pattern>;
3111
3112 multiclass CmpLGtrHalfwordImm
3113 {
3114 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3115 [(set (v8i16 VECREG:$rT),
3116 (setugt (v8i16 VECREG:$rA),
3117 (v8i16 v8i16SExt10Imm:$val)))]>;
3118 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3119 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
3120 }
3121
3122 class CLGTInst pattern> :
3123 RRForm<0b00000011010, OOL, IOL, "cgt\t$rT, $rA, $rB",
3124 ByteOp, pattern>;
3125
3126 multiclass CmpLGtrWord
3127 {
3128 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3129 [(set (v4i32 VECREG:$rT),
3130 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3131
3132 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3133 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
3134 }
3135
3136 class CLGTIInst pattern> :
3137 RI10Form<0b00111010, OOL, IOL, "cgti\t$rT, $rA, $val",
3138 ByteOp, pattern>;
3139
3140 multiclass CmpLGtrWordImm
3141 {
3142 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3143 [(set (v4i32 VECREG:$rT),
3144 (setugt (v4i32 VECREG:$rA),
3145 (v4i32 v4i32SExt16Imm:$val)))]>;
3146
3147 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3148 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3149 }
3150
3151 defm CEQB : CmpEqualByte;
3152 defm CEQBI : CmpEqualByteImm;
3153 defm CEQH : CmpEqualHalfword;
3154 defm CEQHI : CmpEqualHalfwordImm;
3155 defm CEQ : CmpEqualWord;
3156 defm CEQI : CmpEqualWordImm;
3157 defm CGTB : CmpGtrByte;
3158 defm CGTBI : CmpGtrByteImm;
3159 defm CGTH : CmpGtrHalfword;
3160 defm CGTHI : CmpGtrHalfwordImm;
3161 defm CGT : CmpGtrWord;
3162