llvm.org GIT mirror llvm / a5971e8
Reorder some parts of the td file to by in alphabetical order git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165590 91177308-0d34-0410-b5e6-96231b3b80d8 Reed Kotler 8 years ago
1 changed file(s) with 94 addition(s) and 83 deletion(s). Raw diff Collapse all Expand all
1010 //
1111 //===----------------------------------------------------------------------===//
1212 //
13
14 //
15 // Address operand
16 def mem16 : Operand {
17 let PrintMethod = "printMemOperand";
18 let MIOperandInfo = (ops CPU16Regs, simm16);
19 let EncoderMethod = "getMemEncoding";
20 }
21
22 //
23 // Assembler formats in alphabetical order.
24 // Natural and pseudos are mixed together.
25 //
26 //
27 // EXT-RI instruction format
28 //
29
30 class FEXT_RI16_ins_base _op, string asmstr, string asmstr2,
31 InstrItinClass itin>:
32 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
33 !strconcat(asmstr, asmstr2), [], itin>;
34
35 class FEXT_RI16_ins _op, string asmstr,
36 InstrItinClass itin>:
37 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
38
39 class FEXT_RI16_PC_ins _op, string asmstr, InstrItinClass itin>:
40 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
41
42 class FEXT_2RI16_ins _op, string asmstr,
43 InstrItinClass itin>:
44 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
45 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
46 let Constraints = "$rx_ = $rx";
47 }
48
49 // this has an explicit sp argument that we ignore to work around a problem
50 // in the compiler
51 class FEXT_RI16_SP_explicit_ins _op, string asmstr,
52 InstrItinClass itin>:
53 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
54 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
55
56 //
57 // EXT-RRI instruction format
58 //
59
60 class FEXT_RRI16_mem_ins op, string asmstr, Operand MemOpnd,
61 InstrItinClass itin>:
62 FEXT_RRI16
63 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
64
65 class FEXT_RRI16_mem2_ins op, string asmstr, Operand MemOpnd,
66 InstrItinClass itin>:
67 FEXT_RRI16
68 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
69
70 //
71 // EXT-SHIFT instruction format
72 //
73 class FEXT_SHIFT16_ins _f, string asmstr, InstrItinClass itin>:
74 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
75 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
76
77
78 //
79 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
80 //
81 class FI8_MOVR3216_ins:
82 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
83 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
84
85 //
86 // I8_MOV32R instruction format (used only by MOV32R instruction)
87 //
88
89 class FI8_MOV32R16_ins:
90 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
91 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
92
93 //
1394 // This are pseudo formats for multiply
1495 // This first one can be changed to non pseudo now.
15 //fmul
96 //
97 // MULT
98 //
1699 class FMULT16_ins :
17100 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
18101 !strconcat(asmstr, "\t$rx, $ry"), []>;
19102
103 //
104 // MULT-LO
105 //
20106 class FMULT16_LO_ins :
21107 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
22108 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
23109 let isCodeGenOnly=1;
24110 }
25 //
26 // RRR-type instruction format
27 //
28
29 class FRRR16_ins _f, string asmstr, InstrItinClass itin> :
30 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
31 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
32
33 //
34 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
35 //
36 class FI8_MOVR3216_ins:
37 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
38 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
39
40 //
41 // I8_MOV32R instruction format (used only by MOV32R instruction)
42 //
43
44 class FI8_MOV32R16_ins:
45 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
46 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
47
48111
49112 //
50113 // RR-type instruction format
58121 InstrItinClass itin> :
59122 FRR16
60123 !strconcat(asmstr, "\t$rx"), [], itin>;
61
124
62125 class FRxRxRy16_ins f, string asmstr,
63126 InstrItinClass itin> :
64127 FRR16
74137 [], itin> ;
75138
76139 //
77 // EXT-RI instruction format
78 //
79
80 class FEXT_RI16_ins_base _op, string asmstr, string asmstr2,
81 InstrItinClass itin>:
82 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
83 !strconcat(asmstr, asmstr2), [], itin>;
84
85 class FEXT_RI16_ins _op, string asmstr,
86 InstrItinClass itin>:
87 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
88
89 class FEXT_RI16_PC_ins _op, string asmstr, InstrItinClass itin>:
90 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
91
92
93 class FEXT_2RI16_ins _op, string asmstr,
94 InstrItinClass itin>:
95 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
96 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
97 let Constraints = "$rx_ = $rx";
98 }
99
100 // this has an explicit sp argument that we ignore to work around a problem
101 // in the compiler
102 class FEXT_RI16_SP_explicit_ins _op, string asmstr,
103 InstrItinClass itin>:
104 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
105 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
106
107 //
108 // EXT-RRI instruction format
109 //
110
111 class FEXT_RRI16_mem_ins op, string asmstr, Operand MemOpnd,
112 InstrItinClass itin>:
113 FEXT_RRI16
114 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
115
116 class FEXT_RRI16_mem2_ins op, string asmstr, Operand MemOpnd,
117 InstrItinClass itin>:
118 FEXT_RRI16
119 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
120
121 //
122 // EXT-SHIFT instruction format
123 //
124 class FEXT_SHIFT16_ins _f, string asmstr, InstrItinClass itin>:
125 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
126 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
127
128 //
129 // Address operand
130 def mem16 : Operand {
131 let PrintMethod = "printMemOperand";
132 let MIOperandInfo = (ops CPU16Regs, simm16);
133 let EncoderMethod = "getMemEncoding";
134 }
140 // RRR-type instruction format
141 //
142
143 class FRRR16_ins _f, string asmstr, InstrItinClass itin> :
144 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
145 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
135146
136147 //
137148 // Some general instruction class info