llvm.org GIT mirror llvm / a593998
[X86][SSE] Add pblendw commuted load test case Reduced test case for the regression caused in D57888/rL353610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354360 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 1 month ago
1 changed file(s) with 15 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
11 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s
22
3 define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) #0 {
3 define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) {
44 ; CHECK-LABEL: commute_fold_pblendw:
55 ; CHECK: # %bb.0:
66 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1,2,3],xmm0[4],mem[5,6,7]
1111 }
1212 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
1313
14 define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) #0 {
14 define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) {
1515 ; CHECK-LABEL: commute_fold_blendps:
1616 ; CHECK: # %bb.0:
1717 ; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3]
2222 }
2323 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
2424
25 define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) #0 {
25 define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) {
2626 ; CHECK-LABEL: commute_fold_blendpd:
2727 ; CHECK: # %bb.0:
2828 ; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
3232 ret <2 x double> %2
3333 }
3434 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
35
36 define <4 x i32> @commute_fold_blend_v4i32(<4 x i32>* %a, <4 x i32> %b) {
37 ; CHECK-LABEL: commute_fold_blend_v4i32:
38 ; CHECK: # %bb.0:
39 ; CHECK-NEXT: paddd %xmm0, %xmm0 ; force integer domain
40 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = mem[0,1,2,3,4,5],xmm0[6,7]
41 ; CHECK-NEXT: retq
42 %1 = load <4 x i32>, <4 x i32>* %a
43 %2 = add <4 x i32> %b, %b
44 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32>
45 ret <4 x i32> %3
46 }