llvm.org GIT mirror llvm / a55f657
Add missing test case for r141410. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141498 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
1 changed file(s) with 39 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc -O0 < %s
1 target triple = "x86_64-apple-macosx10.7"
2
3 ; This test case extracts a sub_8bit_hi sub-register:
4 ;
5 ; %R8B = COPY %BH, %EBX
6 ; %ESI = MOVZX32_NOREXrr8 %R8B
7 ;
8 ; The register allocation above is invalid, %BH can only be encoded without an
9 ; REX prefix, so the destination register must be GR8_NOREX. The code above
10 ; triggers an assertion in copyPhysReg.
11 ;
12 ;
13
14 define void @f() nounwind uwtable ssp {
15 entry:
16 %0 = load i32* undef, align 4
17 %add = add i32 0, %0
18 %conv1 = trunc i32 %add to i16
19 %bf.value = and i16 %conv1, 255
20 %1 = and i16 %bf.value, 255
21 %2 = shl i16 %1, 8
22 %3 = load i16* undef, align 1
23 %4 = and i16 %3, 255
24 %5 = or i16 %4, %2
25 store i16 %5, i16* undef, align 1
26 %6 = load i16* undef, align 1
27 %7 = lshr i16 %6, 8
28 %bf.clear2 = and i16 %7, 255
29 %conv3 = zext i16 %bf.clear2 to i32
30 %rem = srem i32 %conv3, 15
31 %conv4 = trunc i32 %rem to i16
32 %bf.value5 = and i16 %conv4, 255
33 %8 = and i16 %bf.value5, 255
34 %9 = shl i16 %8, 8
35 %10 = or i16 undef, %9
36 store i16 %10, i16* undef, align 1
37 ret void
38 }