llvm.org GIT mirror llvm / a551a48
Initial 64 bit direct object support. This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 8 years ago
6 changed file(s) with 87 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
608608 EF_MIPS_ARCH_3 = 0x20000000, // MIPS3 instruction set
609609 EF_MIPS_ARCH_4 = 0x30000000, // MIPS4 instruction set
610610 EF_MIPS_ARCH_5 = 0x40000000, // MIPS5 instruction set
611 EF_MIPS_ARCH_32 = 0x60000000, // MIPS32 instruction set
611 EF_MIPS_ARCH_32 = 0x50000000, // MIPS32 instruction set per linux not elf.h
612 EF_MIPS_ARCH_64 = 0x60000000, // MIPS64 instruction set per linux not elf.h
612613 EF_MIPS_ARCH_32R2 = 0x70000000, // mips32r2
614 EF_MIPS_ARCH_64R2 = 0x80000000, // mips64r2
613615 EF_MIPS_ARCH = 0xf0000000 // Mask for applying EF_MIPS_ARCH_ variant
614616 };
615617
6666 class MipsAsmBackend : public MCAsmBackend {
6767 Triple::OSType OSType;
6868 bool IsLittle; // Big or little endian
69 bool Is64Bit; // 32 or 64 bit words
6970
7071 public:
71 MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle) :
72 MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle) {}
72 MipsAsmBackend(const Target &T, Triple::OSType _OSType,
73 bool _isLittle, bool _is64Bit)
74 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
7375
7476 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
75 return createMipsELFObjectWriter(OS, OSType, IsLittle);
77 return createMipsELFObjectWriter(OS, OSType, IsLittle, Is64Bit);
7678 }
7779
7880 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
207209 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
208210 return true;
209211 }
210 };
212 }; // class MipsAsmBackend
211213
212214 } // namespace
213215
214216 // MCAsmBackend
215 MCAsmBackend *llvm::createMipsAsmBackendEL(const Target &T, StringRef TT) {
216 return new MipsAsmBackend(T, Triple(TT).getOS(),
217 /*IsLittle*/true);
218 }
219
220 MCAsmBackend *llvm::createMipsAsmBackendEB(const Target &T, StringRef TT) {
221 return new MipsAsmBackend(T, Triple(TT).getOS(),
222 /*IsLittle*/false);
223 }
217 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) {
218 return new MipsAsmBackend(T, Triple(TT).getOS(),
219 /*IsLittle*/true, /*Is64Bit*/false);
220 }
221
222 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) {
223 return new MipsAsmBackend(T, Triple(TT).getOS(),
224 /*IsLittle*/false, /*Is64Bit*/false);
225 }
226
227 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) {
228 return new MipsAsmBackend(T, Triple(TT).getOS(),
229 /*IsLittle*/true, /*Is64Bit*/true);
230 }
231
232 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) {
233 return new MipsAsmBackend(T, Triple(TT).getOS(),
234 /*IsLittle*/false, /*Is64Bit*/true);
235 }
236
3333
3434 class MipsELFObjectWriter : public MCELFObjectTargetWriter {
3535 public:
36 MipsELFObjectWriter(uint8_t OSABI);
36 MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI);
3737
3838 virtual ~MipsELFObjectWriter();
3939
5151 };
5252 }
5353
54 MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI)
55 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_MIPS,
54 MipsELFObjectWriter::MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI)
55 : MCELFObjectTargetWriter(_is64Bit, OSABI, ELF::EM_MIPS,
5656 /*HasRelocationAddend*/ false) {}
5757
5858 MipsELFObjectWriter::~MipsELFObjectWriter() {}
5959
60 // FIXME: get the real EABI Version from the Triple.
60 // FIXME: get the real EABI Version from the Subtarget class.
6161 unsigned MipsELFObjectWriter::getEFlags() const {
62 return ELF::EF_MIPS_NOREORDER | ELF::EF_MIPS_ARCH_32R2;
62
63 // FIXME: We can't tell if we are PIC (dynamic) or CPIC (static)
64 unsigned Flag = ELF::EF_MIPS_NOREORDER;
65
66 if (is64Bit())
67 Flag |= ELF::EF_MIPS_ARCH_64R2;
68 else
69 Flag |= ELF::EF_MIPS_ARCH_32R2;
70 return Flag;
6371 }
6472
6573 const MCSymbol *MipsELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm,
231239 Relocs[--I] = R->Reloc;
232240 }
233241
234 MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
235 bool IsLittleEndian) {
236 MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(OSABI);
242 MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS,
243 uint8_t OSABI,
244 bool IsLittleEndian,
245 bool Is64Bit) {
246 MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(Is64Bit, OSABI);
237247 return createELFObjectWriter(MOTW, OS, IsLittleEndian);
238248 }
144144
145145 // Register the asm backend.
146146 TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
147 createMipsAsmBackendEB);
147 createMipsAsmBackendEB32);
148148 TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
149 createMipsAsmBackendEL);
149 createMipsAsmBackendEL32);
150150 TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
151 createMipsAsmBackendEB);
151 createMipsAsmBackendEB64);
152152 TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
153 createMipsAsmBackendEL);
153 createMipsAsmBackendEL64);
154154
155155 // Register the MC subtarget info.
156156 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
3838 const MCSubtargetInfo &STI,
3939 MCContext &Ctx);
4040
41 MCAsmBackend *createMipsAsmBackendEB(const Target &T, StringRef TT);
42 MCAsmBackend *createMipsAsmBackendEL(const Target &T, StringRef TT);
41 MCAsmBackend *createMipsAsmBackendEB32(const Target &T, StringRef TT);
42 MCAsmBackend *createMipsAsmBackendEL32(const Target &T, StringRef TT);
43 MCAsmBackend *createMipsAsmBackendEB64(const Target &T, StringRef TT);
44 MCAsmBackend *createMipsAsmBackendEL64(const Target &T, StringRef TT);
4345
4446 MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS,
4547 uint8_t OSABI,
46 bool IsLittleEndian);
48 bool IsLittleEndian,
49 bool Is64Bit);
4750 } // End llvm namespace
4851
4952 // Defines symbolic names for Mips registers. This defines a mapping from
None // RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE %s
1 // RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE %s
0 // 32 bit big endian
1 // RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32 %s
2 // 32 bit little endian
3 // RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE32 %s
4 // 64 bit big endian
5 // RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64 %s
6 // 64 bit little endian
7 // RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE64 %s
28
3 // Check that we produce the correct endian.
9 // Check that we produce 32 bit with each endian.
410
5 // CHECK-BE: ('e_indent[EI_DATA]', 0x02)
6 // CHECK-LE: ('e_indent[EI_DATA]', 0x01)
11 // This is 32 bit.
12 // CHECK-BE32: ('e_indent[EI_CLASS]', 0x01)
13 // This is big endian.
14 // CHECK-BE32: ('e_indent[EI_DATA]', 0x02)
15
16 // This is 32 bit.
17 // CHECK-LE32: ('e_indent[EI_CLASS]', 0x01)
18 // This is little endian.
19 // CHECK-LE32: ('e_indent[EI_DATA]', 0x01)
20
21 // Check that we produce 64 bit with each endian.
22
23 // This is 64 bit.
24 // CHECK-BE64: ('e_indent[EI_CLASS]', 0x02)
25 // This is big endian.
26 // CHECK-BE64: ('e_indent[EI_DATA]', 0x02)
27
28 // This is 64 bit.
29 // CHECK-LE64: ('e_indent[EI_CLASS]', 0x02)
30 // This is little endian.
31 // CHECK-LE64: ('e_indent[EI_DATA]', 0x01)