llvm.org GIT mirror llvm / a5378eb
ARM add missing Thumb1 two-operand aliases for shift-by-immediate. rdar://11222742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
3 changed file(s) with 57 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
14061406 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
14071407 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
14081408
1409
1410 // Implied destination operand forms for shifts.
1411 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1412 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1413 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1414 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1415 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1416 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
66496649 return true;
66506650 }
66516651
6652 // Handle encoding choice for the shift-immediate instructions.
6653 case ARM::t2LSLri:
6654 case ARM::t2LSRri:
6655 case ARM::t2ASRri: {
6656 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6657 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6658 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6659 !(static_cast(Operands[3])->isToken() &&
6660 static_cast(Operands[3])->getToken() == ".w")) {
6661 unsigned NewOpc;
6662 switch (Inst.getOpcode()) {
6663 default: llvm_unreachable("unexpected opcode");
6664 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6665 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6666 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6667 }
6668 // The Thumb1 operands aren't in the same order. Awesome, eh?
6669 MCInst TmpInst;
6670 TmpInst.setOpcode(NewOpc);
6671 TmpInst.addOperand(Inst.getOperand(0));
6672 TmpInst.addOperand(Inst.getOperand(5));
6673 TmpInst.addOperand(Inst.getOperand(1));
6674 TmpInst.addOperand(Inst.getOperand(2));
6675 TmpInst.addOperand(Inst.getOperand(3));
6676 TmpInst.addOperand(Inst.getOperand(4));
6677 Inst = TmpInst;
6678 return true;
6679 }
6680 return false;
6681 }
6682
66526683 // Handle the Thumb2 mode MOV complex aliases.
66536684 case ARM::t2MOVsr:
66546685 case ARM::t2MOVSsr: {
9696 asrs r2, r3, #32
9797 asrs r2, r3, #5
9898 asrs r2, r3, #1
99 asrs r5, #21
100 asrs r5, r5, #21
101 asrs r3, r5, #21
99102
100103 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
101104 @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
102105 @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
106 @ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
107 @ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
108 @ CHECK: asrs r3, r5, #21 @ encoding: [0x6b,0x15]
103109
104110
105111 @------------------------------------------------------------------------------
318324 @------------------------------------------------------------------------------
319325 lsls r4, r5, #0
320326 lsls r4, r5, #4
327 lsls r3, #12
328 lsls r3, r3, #12
329 lsls r1, r3, #12
321330
322331 @ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00]
323332 @ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01]
333 @ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
334 @ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
335 @ CHECK: lsls r1, r3, #12 @ encoding: [0x19,0x03]
324336
325337
326338 @------------------------------------------------------------------------------
336348 @------------------------------------------------------------------------------
337349 lsrs r1, r3, #1
338350 lsrs r1, r3, #32
351 lsrs r4, #20
352 lsrs r4, r4, #20
353 lsrs r2, r4, #20
339354
340355 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
341356 @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
357 @ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
358 @ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
359 @ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d]
342360
343361
344362 @------------------------------------------------------------------------------