llvm.org GIT mirror llvm / a52fdfb
R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0 We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but it is easier to just change the definition of SI_SPILL_S32_RESTORE to only allow numbered sgprs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237143 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
2 changed file(s) with 4 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
20462046 } // End UseNamedOperandTable = 1
20472047 }
20482048
2049 defm SI_SPILL_S32 : SI_SPILL_SGPR ;
2049 // It's unclear whether you can use M0 as the output of v_readlane_b32
2050 // instructions, so use SGPR_32 register class for spills to prevent
2051 // this from happening.
2052 defm SI_SPILL_S32 : SI_SPILL_SGPR ;
20502053 defm SI_SPILL_S64 : SI_SPILL_SGPR ;
20512054 defm SI_SPILL_S128 : SI_SPILL_SGPR ;
20522055 defm SI_SPILL_S256 : SI_SPILL_SGPR ;
244244 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
245245 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
246246 &AMDGPU::SGPR_32RegClass, i);
247 bool isM0 = SubReg == AMDGPU::M0;
248247 struct SIMachineFunctionInfo::SpilledReg Spill =
249248 MFI->getSpilledReg(MF, Index, i);
250249
252251 LLVMContext &Ctx = MF->getFunction()->getContext();
253252 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
254253 }
255
256 if (isM0)
257 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
258254
259255 BuildMI(*MBB, MI, DL,
260256 TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
262258 .addReg(Spill.VGPR)
263259 .addImm(Spill.Lane)
264260 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
265 if (isM0) {
266 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
267 .addReg(SubReg);
268 }
269261 }
270262
271263 // TODO: only do this when it is needed