llvm.org GIT mirror llvm / a5106ca
There are a few places where subtarget features are still represented by uint64_t, this patch replaces these usages with the FeatureBitset (std::bitset) type. Differential Revision: http://reviews.llvm.org/D10542 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241058 91177308-0d34-0410-b5e6-96231b3b80d8 Ranjeet Singh 4 years ago
11 changed file(s) with 127 addition(s) and 101 deletion(s). Raw diff Collapse all Expand all
1212 #include "llvm/MC/MCExpr.h"
1313 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
1414 #include "llvm/MC/MCTargetOptions.h"
15 #include "llvm/MC/SubtargetFeature.h"
1516 #include
1617
1718 namespace llvm {
9495 MCTargetAsmParser();
9596
9697 /// AvailableFeatures - The current set of available features.
97 uint64_t AvailableFeatures;
98 FeatureBitset AvailableFeatures;
9899
99100 /// ParsingInlineAsm - Are we parsing ms-style inline assembly?
100101 bool ParsingInlineAsm;
109110 public:
110111 ~MCTargetAsmParser() override;
111112
112 uint64_t getAvailableFeatures() const { return AvailableFeatures; }
113 void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
113 FeatureBitset getAvailableFeatures() const { return AvailableFeatures; }
114 void setAvailableFeatures(FeatureBitset Value) { AvailableFeatures = Value; }
114115
115116 bool isParsingInlineAsm () { return ParsingInlineAsm; }
116117 void setParsingInlineAsm (bool Value) { ParsingInlineAsm = Value; }
168169 virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
169170 OperandVector &Operands, MCStreamer &Out,
170171 uint64_t &ErrorInfo,
172 FeatureBitset &ErrorMissingFeature,
171173 bool MatchingInlineAsm) = 0;
172174
173175 /// Allows targets to let registers opt out of clobber lists.
16801680 // If parsing succeeded, match the instruction.
16811681 if (!HadError) {
16821682 uint64_t ErrorInfo;
1683 FeatureBitset ErrorMissingFeature;
16831684 getTargetParser().MatchAndEmitInstruction(IDLoc, Info.Opcode,
16841685 Info.ParsedOperands, Out,
1685 ErrorInfo, ParsingInlineAsm);
1686 ErrorInfo, ErrorMissingFeature,
1687 ParsingInlineAsm);
16861688 }
16871689
16881690 // Don't skip the rest of the line, the instruction parser is responsible for
3232 #include "llvm/Support/SourceMgr.h"
3333 #include "llvm/Support/TargetRegistry.h"
3434 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/MC/SubtargetFeature.h"
3536 #include
3637 using namespace llvm;
3738
8586 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8687 OperandVector &Operands, MCStreamer &Out,
8788 uint64_t &ErrorInfo,
89 FeatureBitset &ErrorMissingFeature,
8890 bool MatchingInlineAsm) override;
8991 /// @name Auto-generated Match Functions
9092 /// {
36123614 }
36133615 }
36143616
3615 static const char *getSubtargetFeatureName(uint64_t Val);
3617 static const char *getSubtargetFeatureName(uint64_t Feature);
36163618
36173619 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
36183620 OperandVector &Operands,
36193621 MCStreamer &Out,
36203622 uint64_t &ErrorInfo,
3623 FeatureBitset &ErrorMissingFeature,
36213624 bool MatchingInlineAsm) {
36223625 assert(!Operands.empty() && "Unexpect empty operand list!");
36233626 AArch64Operand &Op = static_cast(*Operands[0]);
38933896 // First try to match against the secondary set of tables containing the
38943897 // short-form NEON instructions (e.g. "fadd.2s v0, v1, v2").
38953898 unsigned MatchResult =
3896 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, 1);
3899 MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm, 1);
38973900
38983901 // If that fails, try against the alternate table containing long-form NEON:
38993902 // "fadd v0.2s, v1.2s, v2.2s"
39003903 if (MatchResult != Match_Success)
39013904 MatchResult =
3902 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm, 0);
3905 MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm, 0);
39033906
39043907 switch (MatchResult) {
39053908 case Match_Success: {
39163919 return false;
39173920 }
39183921 case Match_MissingFeature: {
3919 assert(ErrorInfo && "Unknown missing feature!");
3922 assert(ErrorMissingFeature.any() && "Unknown missing feature!");
39203923 // Special case the error message for the very common case where only
39213924 // a single subtarget feature is missing (neon, e.g.).
39223925 std::string Msg = "instruction requires:";
3923 uint64_t Mask = 1;
3924 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
3925 if (ErrorInfo & Mask) {
3926 for (unsigned i = 0; i < ErrorMissingFeature.size(); ++i) {
3927 if (ErrorMissingFeature[i]) {
39263928 Msg += " ";
3927 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
3929 Msg += getSubtargetFeatureName(i);
39283930 }
3929 Mask <<= 1;
39303931 }
39313932 return Error(IDLoc, Msg);
39323933 }
360360 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
361361 OperandVector &Operands, MCStreamer &Out,
362362 uint64_t &ErrorInfo,
363 FeatureBitset &ErrorMissingFeature,
363364 bool MatchingInlineAsm) override;
364365 bool ParseDirective(AsmToken DirectiveID) override;
365366 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
541542 OperandVector &Operands,
542543 MCStreamer &Out,
543544 uint64_t &ErrorInfo,
545 FeatureBitset &ErrorMissingFeature,
544546 bool MatchingInlineAsm) {
545547 MCInst Inst;
546548
547 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
549 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm)) {
548550 default: break;
549551 case Match_Success:
550552 Inst.setLoc(IDLoc);
576578 AMDGPUOperand::ImmTyOMod));
577579 bool Res = MatchAndEmitInstruction(IDLoc, Opcode, Operands,
578580 Out, ErrorInfo,
581 ErrorMissingFeature,
579582 MatchingInlineAsm);
580583 if (!Res)
581584 return Res;
280280 }
281281
282282 void SwitchMode() {
283 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
283 FeatureBitset FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
284284 setAvailableFeatures(FB);
285285 }
286286 bool isMClass() const {
374374 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
375375 OperandVector &Operands, MCStreamer &Out,
376376 uint64_t &ErrorInfo,
377 FeatureBitset &ErrorMissingFeature,
377378 bool MatchingInlineAsm) override;
378379 void onLabelParsed(MCSymbol *Symbol) override;
379380 };
56225623 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
56235624 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
56245625 }
5625 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5626 static void applyMnemonicAliases(StringRef &Mnemonic, FeatureBitset Features,
56265627 unsigned VariantID);
56275628
56285629 static bool RequiresVFPRegListValidation(StringRef Inst,
56615662 // The generic tblgen'erated code does this later, at the start of
56625663 // MatchInstructionImpl(), but that's too late for aliases that include
56635664 // any sort of suffix.
5664 uint64_t AvailableFeatures = getAvailableFeatures();
5665 FeatureBitset AvailableFeatures = getAvailableFeatures();
56655666 unsigned AssemblerDialect = getParser().getAssemblerDialect();
56665667 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
56675668
85728573 }
85738574 }
85748575
8575 static const char *getSubtargetFeatureName(uint64_t Val);
8576 static const char *getSubtargetFeatureName(uint64_t Feature);
85768577 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
85778578 OperandVector &Operands,
85788579 MCStreamer &Out, uint64_t &ErrorInfo,
8580 FeatureBitset &ErrorMissingFeature,
85798581 bool MatchingInlineAsm) {
85808582 MCInst Inst;
85818583 unsigned MatchResult;
85828584
85838585 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8584 MatchingInlineAsm);
8586 ErrorMissingFeature, MatchingInlineAsm);
85858587 switch (MatchResult) {
85868588 case Match_Success:
85878589 // Context sensitive operand constraints aren't handled by the matcher,
86248626 Out.EmitInstruction(Inst, STI);
86258627 return false;
86268628 case Match_MissingFeature: {
8627 assert(ErrorInfo && "Unknown missing feature!");
8629 assert(ErrorMissingFeature.any() && "Unknown missing feature!");
86288630 // Special case the error message for the very common case where only
86298631 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
86308632 std::string Msg = "instruction requires:";
8631 uint64_t Mask = 1;
8632 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8633 if (ErrorInfo & Mask) {
8633 for (unsigned i = 0; i < ErrorMissingFeature.size(); ++i) {
8634 if (ErrorMissingFeature[i]) {
86348635 Msg += " ";
8635 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8636 Msg += getSubtargetFeatureName(i);
86368637 }
8637 Mask <<= 1;
86388638 }
86398639 return Error(IDLoc, Msg);
86408640 }
99159915 // flags below, that were generated by table-gen.
99169916 static const struct {
99179917 const ARM::ArchExtKind Kind;
9918 const unsigned ArchCheck;
9918 const FeatureBitset ArchCheck;
99199919 const FeatureBitset Features;
99209920 } Extensions[] = {
9921 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
9922 { ARM::AEK_CRYPTO, Feature_HasV8,
9921 { ARM::AEK_CRC, {Feature_HasV8}, {ARM::FeatureCRC} },
9922 { ARM::AEK_CRYPTO, {Feature_HasV8},
99239923 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9924 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
9925 { ARM::AEK_HWDIV, Feature_HasV7 | Feature_IsNotMClass,
9924 { ARM::AEK_FP, {Feature_HasV8}, {ARM::FeatureFPARMv8} },
9925 { ARM::AEK_HWDIV, {Feature_HasV7, Feature_IsNotMClass},
99269926 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
9927 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
9928 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9927 { ARM::AEK_MP, {Feature_HasV7 , Feature_IsNotMClass}, {ARM::FeatureMP} },
9928 { ARM::AEK_SIMD, {Feature_HasV8}, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
99299929 // FIXME: Also available in ARMv6-K
9930 { ARM::AEK_SEC, Feature_HasV7, {ARM::FeatureTrustZone} },
9930 { ARM::AEK_SEC, {Feature_HasV7}, {ARM::FeatureTrustZone} },
99319931 // FIXME: Only available in A-class, isel not predicated
9932 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
9932 { ARM::AEK_VIRT, {Feature_HasV7}, {ARM::FeatureVirtualization} },
99339933 // FIXME: Unsupported extensions.
9934 { ARM::AEK_OS, Feature_None, {} },
9935 { ARM::AEK_IWMMXT, Feature_None, {} },
9936 { ARM::AEK_IWMMXT2, Feature_None, {} },
9937 { ARM::AEK_MAVERICK, Feature_None, {} },
9938 { ARM::AEK_XSCALE, Feature_None, {} },
9934 { ARM::AEK_OS, {Feature_None}, {} },
9935 { ARM::AEK_IWMMXT, {Feature_None}, {} },
9936 { ARM::AEK_IWMMXT2, {Feature_None}, {} },
9937 { ARM::AEK_MAVERICK, {Feature_None}, {} },
9938 { ARM::AEK_XSCALE, {Feature_None}, {} },
99399939 };
99409940
99419941 /// parseDirectiveArchExtension
99799979 ? (~STI.getFeatureBits() & Extension.Features)
99809980 : ( STI.getFeatureBits() & Extension.Features);
99819981
9982 uint64_t Features =
9982 FeatureBitset Features =
99839983 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
99849984 setAvailableFeatures(Features);
99859985 return false;
126126 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
127127 OperandVector &Operands, MCStreamer &Out,
128128 uint64_t &ErrorInfo,
129 FeatureBitset &ErrorMissingFeature,
129130 bool MatchingInlineAsm) override;
130131
131132 /// Parse a register as used in CFI directives
27212722 OperandVector &Operands,
27222723 MCStreamer &Out,
27232724 uint64_t &ErrorInfo,
2725 FeatureBitset &ErrorMissingFeature,
27242726 bool MatchingInlineAsm) {
27252727
27262728 MCInst Inst;
27272729 SmallVector Instructions;
27282730 unsigned MatchResult =
2729 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
2731 MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm);
27302732
27312733 switch (MatchResult) {
27322734 case Match_Success: {
276276 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
277277 OperandVector &Operands, MCStreamer &Out,
278278 uint64_t &ErrorInfo,
279 FeatureBitset &ErrorMissingFeature,
279280 bool MatchingInlineAsm) override;
280281
281282 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
11961197 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
11971198 OperandVector &Operands,
11981199 MCStreamer &Out, uint64_t &ErrorInfo,
1200 FeatureBitset &ErrorMissingFeature,
11991201 bool MatchingInlineAsm) {
12001202 MCInst Inst;
12011203
1202 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1204 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm)) {
12031205 case Match_Success:
12041206 // Post-process instructions (typically extended mnemonics)
12051207 ProcessInstruction(Inst, Operands);
4848 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4949 OperandVector &Operands, MCStreamer &Out,
5050 uint64_t &ErrorInfo,
51 FeatureBitset &ErrorMissingFeature,
5152 bool MatchingInlineAsm) override;
5253 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
5354 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
444445 OperandVector &Operands,
445446 MCStreamer &Out,
446447 uint64_t &ErrorInfo,
448 FeatureBitset &ErrorMissingFeature,
447449 bool MatchingInlineAsm) {
448450 MCInst Inst;
449451 SmallVector Instructions;
450452 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
453 ErrorMissingFeature,
451454 MatchingInlineAsm);
452455 switch (MatchResult) {
453456 case Match_Success: {
509512 return Error(StartLoc, "invalid register name");
510513 }
511514
512 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
515 static void applyMnemonicAliases(StringRef &Mnemonic, FeatureBitset Features,
513516 unsigned VariantID);
514517
515518 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
403403 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
404404 OperandVector &Operands, MCStreamer &Out,
405405 uint64_t &ErrorInfo,
406 FeatureBitset &ErrorMissingFeature,
406407 bool MatchingInlineAsm) override;
407408
408409 // Used by the TableGen code to parse particular operand types.
781782 OperandVector &Operands,
782783 MCStreamer &Out,
783784 uint64_t &ErrorInfo,
785 FeatureBitset &ErrorMissingFeature,
784786 bool MatchingInlineAsm) {
785787 MCInst Inst;
786788 unsigned MatchResult;
787789
788790 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
789 MatchingInlineAsm);
791 ErrorMissingFeature, MatchingInlineAsm);
790792 switch (MatchResult) {
791793 case Match_Success:
792794 Inst.setLoc(IDLoc);
794796 return false;
795797
796798 case Match_MissingFeature: {
797 assert(ErrorInfo && "Unknown missing feature!");
799 assert(ErrorMissingFeature.any() && "Unknown missing feature!");
798800 // Special case the error message for the very common case where only
799801 // a single subtarget feature is missing
800802 std::string Msg = "instruction requires:";
801 uint64_t Mask = 1;
802 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
803 if (ErrorInfo & Mask) {
803 for (unsigned I = 0; I < ErrorMissingFeature.size(); ++I) {
804 if (ErrorMissingFeature[I]) {
804805 Msg += " ";
805 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
806 Msg += getSubtargetFeatureName(I);
806807 }
807 Mask <<= 1;
808808 }
809809 return Error(IDLoc, Msg);
810810 }
721721 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
722722 OperandVector &Operands, MCStreamer &Out,
723723 uint64_t &ErrorInfo,
724 FeatureBitset &ErrorMissingFeature,
724725 bool MatchingInlineAsm) override;
725726
726727 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
727728 MCStreamer &Out, bool MatchingInlineAsm);
728729
729 bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
730 bool ErrorMissingFeature(SMLoc IDLoc, FeatureBitset MissingFeature,
730731 bool MatchingInlineAsm);
731732
732733 bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
733734 OperandVector &Operands, MCStreamer &Out,
734735 uint64_t &ErrorInfo,
736 FeatureBitset &ErrorMissingFeature,
735737 bool MatchingInlineAsm);
736738
737739 bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
738740 OperandVector &Operands, MCStreamer &Out,
739741 uint64_t &ErrorInfo,
742 FeatureBitset &ErrorMissingFeature,
740743 bool MatchingInlineAsm);
741744
742745 bool OmitRegisterFromClobberLists(unsigned RegNo) override;
767770 void SwitchMode(unsigned mode) {
768771 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
769772 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
770 unsigned FB = ComputeAvailableFeatures(
773 FeatureBitset FB = ComputeAvailableFeatures(
771774 STI.ToggleFeature(OldMode.flip(mode)));
772775 setAvailableFeatures(FB);
773776
24892492 }
24902493 }
24912494
2492 static const char *getSubtargetFeatureName(uint64_t Val);
2495 static const char *getSubtargetFeatureName(uint64_t Feature);
24932496
24942497 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
24952498 MCStreamer &Out) {
25002503 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
25012504 OperandVector &Operands,
25022505 MCStreamer &Out, uint64_t &ErrorInfo,
2506 FeatureBitset &ErrorMissingFeature,
25032507 bool MatchingInlineAsm) {
25042508 if (isParsingIntelSyntax())
25052509 return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2506 MatchingInlineAsm);
2510 ErrorMissingFeature, MatchingInlineAsm);
25072511 return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2508 MatchingInlineAsm);
2512 ErrorMissingFeature, MatchingInlineAsm);
25092513 }
25102514
25112515 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
25342538 }
25352539 }
25362540
2537 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
2541 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, FeatureBitset MissingFeature,
25382542 bool MatchingInlineAsm) {
2539 assert(ErrorInfo && "Unknown missing feature!");
2543 assert(MissingFeature.any() && "Unknown missing feature!");
25402544 ArrayRef EmptyRanges = None;
25412545 SmallString<126> Msg;
25422546 raw_svector_ostream OS(Msg);
25432547 OS << "instruction requires:";
2544 uint64_t Mask = 1;
2545 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2546 if (ErrorInfo & Mask)
2547 OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
2548 Mask <<= 1;
2548 for (unsigned i = 0; i < MissingFeature.size(); ++i) {
2549 if (MissingFeature[i])
2550 OS << ' ' << getSubtargetFeatureName(i);
25492551 }
25502552 return Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
25512553 }
25542556 OperandVector &Operands,
25552557 MCStreamer &Out,
25562558 uint64_t &ErrorInfo,
2559 FeatureBitset &ErrMissingFeature,
25572560 bool MatchingInlineAsm) {
25582561 assert(!Operands.empty() && "Unexpect empty operand list!");
25592562 X86Operand &Op = static_cast(*Operands[0]);
25682571
25692572 // First, try a direct match.
25702573 switch (MatchInstructionImpl(Operands, Inst,
2571 ErrorInfo, MatchingInlineAsm,
2574 ErrorInfo, ErrMissingFeature,
2575 MatchingInlineAsm,
25722576 isParsingIntelSyntax())) {
25732577 default: llvm_unreachable("Unexpected match result!");
25742578 case Match_Success:
25882592 Opcode = Inst.getOpcode();
25892593 return false;
25902594 case Match_MissingFeature:
2591 return ErrorMissingFeature(IDLoc, ErrorInfo, MatchingInlineAsm);
2595 return ErrorMissingFeature(IDLoc, ErrMissingFeature, MatchingInlineAsm);
25922596 case Match_InvalidOperand:
25932597 WasOriginallyInvalidOperand = true;
25942598 break;
26182622
26192623 // Check for the various suffix matches.
26202624 uint64_t ErrorInfoIgnore;
2621 uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2625 FeatureBitset ErrorInfoMissingFeature;
26222626 unsigned Match[4];
26232627
26242628 for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
26252629 Tmp.back() = Suffixes[I];
2626 Match[I] = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2627 MatchingInlineAsm, isParsingIntelSyntax());
2630 Match[I] = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore, ErrMissingFeature,
2631 MatchingInlineAsm, isParsingIntelSyntax());
26282632 // If this returned as a missing feature failure, remember that.
26292633 if (Match[I] == Match_MissingFeature)
2630 ErrorInfoMissingFeature = ErrorInfoIgnore;
2634 ErrorInfoMissingFeature = ErrMissingFeature;
26312635 }
26322636
26332637 // Restore the old token.
27062710 // missing feature.
27072711 if (std::count(std::begin(Match), std::end(Match),
27082712 Match_MissingFeature) == 1) {
2709 ErrorInfo = ErrorInfoMissingFeature;
2710 return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
2713 ErrMissingFeature = ErrorInfoMissingFeature;
2714 return ErrorMissingFeature(IDLoc, ErrMissingFeature,
27112715 MatchingInlineAsm);
27122716 }
27132717
27292733 OperandVector &Operands,
27302734 MCStreamer &Out,
27312735 uint64_t &ErrorInfo,
2736 FeatureBitset& ErrMissingFeature,
27322737 bool MatchingInlineAsm) {
27332738 assert(!Operands.empty() && "Unexpect empty operand list!");
27342739 X86Operand &Op = static_cast(*Operands[0]);
27652770 // operand size. In Intel assembly, the size is not part of the instruction
27662771 // mnemonic.
27672772 SmallVector Match;
2768 uint64_t ErrorInfoMissingFeature = 0;
2773 FeatureBitset ErrorInfoMissingFeature;
27692774 if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
27702775 static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
27712776 for (unsigned Size : MopSizes) {
27722777 UnsizedMemOp->Mem.Size = Size;
27732778 uint64_t ErrorInfoIgnore;
2779 FeatureBitset MissingFeature;
27742780 unsigned LastOpcode = Inst.getOpcode();
27752781 unsigned M =
2776 MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2782 MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore, MissingFeature,
27772783 MatchingInlineAsm, isParsingIntelSyntax());
27782784 if (Match.empty() || LastOpcode != Inst.getOpcode())
27792785 Match.push_back(M);
27802786
27812787 // If this returned as a missing feature failure, remember that.
27822788 if (Match.back() == Match_MissingFeature)
2783 ErrorInfoMissingFeature = ErrorInfoIgnore;
2789 ErrorInfoMissingFeature = MissingFeature;
27842790 }
27852791
27862792 // Restore the size of the unsized memory operand if we modified it.
27932799 // matching with the unsized operand.
27942800 if (Match.empty()) {
27952801 Match.push_back(MatchInstructionImpl(Operands, Inst, ErrorInfo,
2802 ErrMissingFeature,
27962803 MatchingInlineAsm,
27972804 isParsingIntelSyntax()));
27982805 // If this returned as a missing feature failure, remember that.
27992806 if (Match.back() == Match_MissingFeature)
2800 ErrorInfoMissingFeature = ErrorInfo;
2807 ErrorInfoMissingFeature = ErrMissingFeature;
28012808 }
28022809
28032810 // Restore the size of the unsized memory operand if we modified it.
28462853 // missing feature.
28472854 if (std::count(std::begin(Match), std::end(Match),
28482855 Match_MissingFeature) == 1) {
2849 ErrorInfo = ErrorInfoMissingFeature;
2856 ErrMissingFeature = ErrorInfoMissingFeature;
28502857 return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
28512858 MatchingInlineAsm);
28522859 }
22222222 << " {\n";
22232223 for (const auto &SF : Info.SubtargetFeatures) {
22242224 const SubtargetFeatureInfo &SFI = SF.second;
2225 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2225 OS << " " << SFI.getEnumName() << " = " << SFI.Index << ",\n";
22262226 }
22272227 OS << " Feature_None = 0\n";
22282228 OS << "};\n\n";
22532253 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
22542254 OS << "// User-level names for subtarget features that participate in\n"
22552255 << "// instruction matching.\n"
2256 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2256 << "static const char *getSubtargetFeatureName(uint64_t Feature) {\n";
22572257 if (!Info.SubtargetFeatures.empty()) {
2258 OS << " switch(Val) {\n";
2258 OS << " switch(Feature) {\n";
22592259 for (const auto &SF : Info.SubtargetFeatures) {
22602260 const SubtargetFeatureInfo &SFI = SF.second;
22612261 // FIXME: Totally just a placeholder name to get the algorithm working.
22782278 std::string ClassName =
22792279 Info.AsmParser->getValueAsString("AsmParserClassName");
22802280
2281 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2281 OS << "FeatureBitset " << Info.Target.getName() << ClassName << "::\n"
22822282 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
2283 OS << " uint64_t Features = 0;\n";
2283 OS << " FeatureBitset Features;\n";
22842284 for (const auto &SF : Info.SubtargetFeatures) {
22852285 const SubtargetFeatureInfo &SFI = SF.second;
22862286
23142314 } while (true);
23152315
23162316 OS << ")\n";
2317 OS << " Features |= " << SFI.getEnumName() << ";\n";
2317 OS << " Features.set(" << SFI.getEnumName() << ", 1);\n";
23182318 }
23192319 OS << " return Features;\n";
23202320 OS << "}\n\n";
23992399
24002400 if (!MatchCode.empty())
24012401 MatchCode += "else ";
2402 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2402 MatchCode += "if ((Features & FeatureBitset({"+FeatureMask+"})) == FeatureBitset({"+FeatureMask+"}))\n";
24032403 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
24042404 }
24052405
24302430 if (Aliases.empty()) return false;
24312431
24322432 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2433 "uint64_t Features, unsigned VariantID) {\n";
2433 "FeatureBitset Features, unsigned VariantID) {\n";
24342434 OS << " switch (VariantID) {\n";
24352435 unsigned VariantCount = Target.getAsmParserVariantCount();
24362436 for (unsigned VC = 0; VC != VariantCount; ++VC) {
24662466 // Emit the static custom operand parsing table;
24672467 OS << "namespace {\n";
24682468 OS << " struct OperandMatchEntry {\n";
2469 OS << " " << getMinimalRequiredFeaturesType(Info)
2470 << " RequiredFeatures;\n";
2469 OS << " FeatureBitset RequiredFeatures;\n";
24712470 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
24722471 << " Mnemonic;\n";
24732472 OS << " " << getMinimalTypeForRange(std::distance(
25102509
25112510 // Write the required features mask.
25122511 if (!II.RequiredFeatures.empty()) {
2512 OS << "{";
25132513 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2514 if (i) OS << "|";
2514 if (i) OS << ",";
25152515 OS << II.RequiredFeatures[i]->getEnumName();
25162516 }
2517 OS << "}";
25172518 } else
2518 OS << "0";
2519 OS << "{}";
25192520
25202521 // Store a pascal-style length byte in the mnemonic.
25212522 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
25712572
25722573 // Emit code to get the available features.
25732574 OS << " // Get the current feature set.\n";
2574 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2575 OS << " FeatureBitset AvailableFeatures = getAvailableFeatures();\n\n";
25752576
25762577 OS << " // Get the next operand index.\n";
25772578 OS << " unsigned NextOpNum = Operands.size()-1;\n";
26742675 OS << "#undef GET_ASSEMBLER_HEADER\n";
26752676 OS << " // This should be included into the middle of the declaration of\n";
26762677 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2677 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2678 OS << " FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
26782679 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
26792680 << "unsigned Opcode,\n"
26802681 << " const OperandVector "
26842685 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
26852686 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
26862687 << " MCInst &Inst,\n"
2687 << " uint64_t &ErrorInfo,"
2688 << " bool matchingInlineAsm,\n"
2688 << " uint64_t &ErrorInfo,\n"
2689 << " FeatureBitset &ErrorMissingFeature,\n"
2690 << " bool matchingInlineAsm,\n"
26892691 << " unsigned VariantID = 0);\n";
26902692
26912693 if (!Info.OperandMatchInfo.empty()) {
27962798 OS << " uint16_t Opcode;\n";
27972799 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
27982800 << " ConvertFn;\n";
2799 OS << " " << getMinimalRequiredFeaturesType(Info)
2800 << " RequiredFeatures;\n";
2801 OS << " FeatureBitset RequiredFeatures;\n";
28012802 OS << " " << getMinimalTypeForRange(
28022803 std::distance(Info.Classes.begin(), Info.Classes.end()))
28032804 << " Classes[" << MaxNumOperands << "];\n";
28432844
28442845 // Write the required features mask.
28452846 if (!MI->RequiredFeatures.empty()) {
2847 OS << "{";
28462848 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2847 if (i) OS << "|";
2849 if (i) OS << ",";
28482850 OS << MI->RequiredFeatures[i]->getEnumName();
28492851 }
2852 OS << "}";
28502853 } else
2851 OS << "0";
2854 OS << "{}";
28522855
28532856 OS << ", { ";
28542857 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
28872890 OS << "unsigned " << Target.getName() << ClassName << "::\n"
28882891 << "MatchInstructionImpl(const OperandVector &Operands,\n";
28892892 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2893 << " FeatureBitset &ErrorMissingFeature,\n"
28902894 << " bool matchingInlineAsm, unsigned VariantID) {\n";
28912895
28922896 OS << " // Eliminate obvious mismatches.\n";
28972901
28982902 // Emit code to get the available features.
28992903 OS << " // Get the current feature set.\n";
2900 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2904 OS << " FeatureBitset AvailableFeatures = getAvailableFeatures();\n\n";
29012905
29022906 OS << " // Get the instruction mnemonic, which is the first token.\n";
29032907 OS << " StringRef Mnemonic = ((" << Target.getName()
29132917 OS << " bool HadMatchOtherThanFeatures = false;\n";
29142918 OS << " bool HadMatchOtherThanPredicate = false;\n";
29152919 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2916 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2920 OS << " FeatureBitset MissingFeatures(~0ULL);\n";
29172921 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
29182922 OS << " // wrong for all instances of the instruction.\n";
29192923 OS << " ErrorInfo = ~0ULL;\n";
29892993 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
29902994 << "!= it->RequiredFeatures) {\n";
29912995 OS << " HadMatchOtherThanFeatures = true;\n";
2992 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2996 OS << " FeatureBitset NewMissingFeatures = it->RequiredFeatures & "
29932997 "~AvailableFeatures;\n";
2994 OS << " if (countPopulation(NewMissingFeatures) <=\n"
2995 " countPopulation(MissingFeatures))\n";
2998 OS << " if (NewMissingFeatures.count() <=\n"
2999 " MissingFeatures.count())\n";
29963000 OS << " MissingFeatures = NewMissingFeatures;\n";
29973001 OS << " continue;\n";
29983002 OS << " }\n";
30423046 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
30433047 OS << " return RetCode;\n\n";
30443048 OS << " // Missing feature matches return which features were missing\n";
3045 OS << " ErrorInfo = MissingFeatures;\n";
3049 OS << " ErrorMissingFeature = MissingFeatures;\n";
30463050 OS << " return Match_MissingFeature;\n";
30473051 OS << "}\n\n";
30483052