llvm.org GIT mirror llvm / a4e6435
add the memri memory operand this makes it possible for ldr instructions with non-zero immediate git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 14 years ago
4 changed file(s) with 41 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
5555
5656 virtual const char *getPassName() const {
5757 return "ARM Assembly Printer";
58 }
59
60 void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
61 printOperand(MI, OpNo + 1);
62 O << ", ";
63 printOperand(MI, OpNo);
5864 }
5965
6066 void printOperand(const MachineInstr *MI, int opNum);
163163
164164 void Select(SDOperand &Result, SDOperand Op);
165165 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
166 bool SelectAddrReg(SDOperand N, SDOperand &Base);
166 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
167167
168168 // Include the pieces autogenerated from the target description.
169169 #include "ARMGenDAGISel.inc"
182182 ScheduleAndEmitDAG(DAG);
183183 }
184184
185 bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) {
185 //register plus/minus 12 bit offset
186 bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
187 SDOperand &Base) {
188 Offset = CurDAG->getTargetConstant(0, MVT::i32);
186189 if (FrameIndexSDNode *FI = dyn_cast(N)) {
187190 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
188191 }
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 // Address operands
15 def memri : Operand {
16 let PrintMethod = "printMemRegImm";
17 let NumMIOperands = 2;
18 let MIOperandInfo = (ops i32imm, ptr_rc);
19 }
20
1421 // Define ARM specific addressing mode.
15 //register or frame index
16 def raddr : ComplexPattern;
22 //register plus/minus 12 bit offset
23 def iaddr : ComplexPattern;
24 //register plus scaled register
25 //def raddr : ComplexPattern;
1726
1827 //===----------------------------------------------------------------------===//
1928 // Instructions
4150
4251 def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
4352
44 def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
53 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
4554 "ldr $dst, [$addr]",
46 [(set IntRegs:$dst, (load raddr:$addr))]>;
55 [(set IntRegs:$dst, (load iaddr:$addr))]>;
4756
4857 def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
4958 "str $src, [$addr]",
8282
8383 assert (MI.getOpcode() == ARM::ldr);
8484
85 unsigned FrameIdx = 1;
85 unsigned FrameIdx = 2;
86 unsigned OffIdx = 1;
8687
8788 int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
8889
8990 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
91 assert (MI.getOperand(OffIdx).getImmedValue() == 0);
9092
9193 unsigned StackSize = MF.getFrameInfo()->getStackSize();
9294
9395 Offset += StackSize;
9496
95 // Insert a set of r12 with the full address
96 // r12 = r13 + offset
97 MachineBasicBlock *MBB2 = MI.getParent();
98 BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
97 assert (Offset >= 0);
98 if (Offset < 4096) {
99 // Replace the FrameIndex with r13
100 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
101 // Replace the ldr offset with Offset
102 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
103 } else {
104 // Insert a set of r12 with the full address
105 // r12 = r13 + offset
106 MachineBasicBlock *MBB2 = MI.getParent();
107 BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
99108
100 // Replace the FrameIndex with r12
101 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
109 // Replace the FrameIndex with r12
110 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
111 }
102112 }
103113
104114 void ARMRegisterInfo::