llvm.org GIT mirror llvm / a493812
[x86] Add OpSize16 to instructions that need it This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8 David Woodhouse 6 years ago
9 changed file(s) with 552 addition(s) and 228 deletion(s). Raw diff Collapse all Expand all
2323 (outs GR32:$dst), (ins i32mem:$src),
2424 "lea{l}\t{$src|$dst}, {$dst|$src}",
2525 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
26 Requires<[Not64BitMode]>;
26 OpSize16, Requires<[Not64BitMode]>;
2727
2828 def LEA64_32r : I<0x8D, MRMSrcMem,
2929 (outs GR32:$dst), (ins lea64_32mem:$src),
7373 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
7474 "mul{l}\t$src",
7575 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
76 IIC_MUL32_REG>, Sched<[WriteIMul]>;
76 IIC_MUL32_REG>, OpSize16, Sched<[WriteIMul]>;
7777 // RAX,RDX = RAX*GR64
7878 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
7979 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
9999 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
100100 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
101101 "mul{l}\t$src",
102 [], IIC_MUL32_MEM>, SchedLoadReg;
102 [], IIC_MUL32_MEM>, OpSize16, SchedLoadReg;
103103 // RAX,RDX = RAX*[mem64]
104104 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
105105 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
118118 // EAX,EDX = EAX*GR32
119119 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
120120 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
121 IIC_IMUL32_RR>, Sched<[WriteIMul]>;
121 IIC_IMUL32_RR>, OpSize16, Sched<[WriteIMul]>;
122122 // RAX,RDX = RAX*GR64
123123 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
124124 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
137137 // EAX,EDX = EAX*[mem32]
138138 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
139139 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
140 "imul{l}\t$src", [], IIC_IMUL32_MEM>, SchedLoadReg;
140 "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize16,
141 SchedLoadReg;
141142 // RAX,RDX = RAX*[mem64]
142143 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
143144 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
161162 "imul{l}\t{$src2, $dst|$dst, $src2}",
162163 [(set GR32:$dst, EFLAGS,
163164 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
164 TB;
165 TB, OpSize16;
165166 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
166167 (ins GR64:$src1, GR64:$src2),
167168 "imul{q}\t{$src2, $dst|$dst, $src2}",
185186 [(set GR32:$dst, EFLAGS,
186187 (X86smul_flag GR32:$src1, (load addr:$src2)))],
187188 IIC_IMUL32_RM>,
188 TB;
189 TB, OpSize16;
189190 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
190191 (ins GR64:$src1, i64mem:$src2),
191192 "imul{q}\t{$src2, $dst|$dst, $src2}",
220221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
221222 [(set GR32:$dst, EFLAGS,
222223 (X86smul_flag GR32:$src1, imm:$src2))],
223 IIC_IMUL32_RRI>;
224 IIC_IMUL32_RRI>, OpSize16;
224225 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
225226 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
226227 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
227228 [(set GR32:$dst, EFLAGS,
228229 (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
229 IIC_IMUL32_RRI>;
230 IIC_IMUL32_RRI>, OpSize16;
230231 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
231232 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
232233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262263 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
263264 [(set GR32:$dst, EFLAGS,
264265 (X86smul_flag (load addr:$src1), imm:$src2))],
265 IIC_IMUL32_RMI>;
266 IIC_IMUL32_RMI>, OpSize16;
266267 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
267268 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
268269 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
269270 [(set GR32:$dst, EFLAGS,
270271 (X86smul_flag (load addr:$src1),
271272 i32immSExt8:$src2))],
272 IIC_IMUL32_RMI>;
273 IIC_IMUL32_RMI>, OpSize16;
273274 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
274275 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
275276 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
301302 "div{w}\t$src", [], IIC_DIV16>, OpSize;
302303 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
303304 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
304 "div{l}\t$src", [], IIC_DIV32>;
305 "div{l}\t$src", [], IIC_DIV32>, OpSize16;
305306 // RDX:RAX/r64 = RAX,RDX
306307 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
307308 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
320321 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
321322 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
322323 "div{l}\t$src", [], IIC_DIV32>,
323 SchedLoadReg;
324 SchedLoadReg, OpSize16;
324325 // RDX:RAX/[mem64] = RAX,RDX
325326 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
326327 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
338339 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
339340 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
340341 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
341 "idiv{l}\t$src", [], IIC_IDIV32>;
342 "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16;
342343 // RDX:RAX/r64 = RAX,RDX
343344 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
344345 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
356357 SchedLoadReg;
357358 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
358359 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
359 "idiv{l}\t$src", [], IIC_IDIV32>,
360 "idiv{l}\t$src", [], IIC_IDIV32>, OpSize16,
360361 SchedLoadReg;
361362 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
362363 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
384385 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
385386 "neg{l}\t$dst",
386387 [(set GR32:$dst, (ineg GR32:$src1)),
387 (implicit EFLAGS)], IIC_UNARY_REG>;
388 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
388389 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
389390 [(set GR64:$dst, (ineg GR64:$src1)),
390391 (implicit EFLAGS)], IIC_UNARY_REG>;
403404 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
404405 "neg{l}\t$dst",
405406 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
406 (implicit EFLAGS)], IIC_UNARY_MEM>;
407 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
407408 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
408409 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
409410 (implicit EFLAGS)], IIC_UNARY_MEM>;
424425 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
425426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
426427 "not{l}\t$dst",
427 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;
428 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize16;
428429 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
429430 [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
430431 }
440441 OpSize;
441442 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
442443 "not{l}\t$dst",
443 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
444 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
445 OpSize16;
444446 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
445447 [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
446448 } // SchedRW
464466 "inc{l}\t$dst",
465467 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
466468 IIC_UNARY_REG>,
467 Requires<[Not64BitMode]>;
469 OpSize16, Requires<[Not64BitMode]>;
468470 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
469471 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
470472 IIC_UNARY_REG>;
503505 OpSize, Requires<[Not64BitMode]>;
504506 def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
505507 "inc{l}\t$dst", [], IIC_UNARY_REG>,
506 Requires<[Not64BitMode]>;
508 OpSize16, Requires<[Not64BitMode]>;
507509 def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
508510 "dec{w}\t$dst", [], IIC_UNARY_REG>,
509511 OpSize, Requires<[Not64BitMode]>;
510512 def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
511513 "dec{l}\t$dst", [], IIC_UNARY_REG>,
512 Requires<[Not64BitMode]>;
514 OpSize16, Requires<[Not64BitMode]>;
513515 } // isCodeGenOnly = 1, ForceDisassemble = 1, HasSideEffects = 0, CodeSize = 2
514516
515517 } // Constraints = "$src1 = $dst", SchedRW
525527 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
526528 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
527529 (implicit EFLAGS)], IIC_UNARY_MEM>,
528 Requires<[Not64BitMode]>;
530 OpSize16, Requires<[Not64BitMode]>;
529531 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
530532 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
531533 (implicit EFLAGS)], IIC_UNARY_MEM>;
567569 "dec{l}\t$dst",
568570 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
569571 IIC_UNARY_REG>,
570 Requires<[Not64BitMode]>;
572 OpSize16, Requires<[Not64BitMode]>;
571573 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
572574 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
573575 IIC_UNARY_REG>;
586588 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
587589 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
588590 (implicit EFLAGS)], IIC_UNARY_MEM>,
589 Requires<[Not64BitMode]>;
591 OpSize16, Requires<[Not64BitMode]>;
590592 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
591593 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
592594 (implicit EFLAGS)], IIC_UNARY_MEM>;
600602 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
601603 Operand immoperand, SDPatternOperator immoperator,
602604 Operand imm8operand, SDPatternOperator imm8operator,
603 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
605 bit hasOddOpcode, bit hasOpSizePrefix, bit hasOpSize16Prefix,
606 bit hasREX_WPrefix> {
604607 /// VT - This is the value type itself.
605608 ValueType VT = vt;
606609
651654 bit HasOddOpcode = hasOddOpcode;
652655
653656 /// HasOpSizePrefix - This bit is set to true if the instruction should have
654 /// the 0x66 operand size prefix. This is set for i16 types.
657 /// the 0x66 operand size prefix in 32-bit or 64-bit modes. This is set for
658 /// i16 types.
655659 bit HasOpSizePrefix = hasOpSizePrefix;
660
661 /// HasOpSizePrefix - This bit is set to true if the instruction should have
662 /// the 0x66 operand size prefix in 16-bit mode. This is set for i32 types.
663 bit HasOpSize16Prefix = hasOpSize16Prefix;
656664
657665 /// HasREX_WPrefix - This bit is set to true if the instruction should have
658666 /// the 0x40 REX prefix. This is set for i64 types.
664672
665673 def Xi8 : X86TypeInfo
666674 Imm8 , i8imm , imm, i8imm , invalid_node,
667 0, 0, 0>;
675 0, 0, 0, 0>;
668676 def Xi16 : X86TypeInfo
669677 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
670 1, 1, 0>;
678 1, 1, 0, 0>;
671679 def Xi32 : X86TypeInfo
672680 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
673 1, 0, 0>;
681 1, 0, 1, 0>;
674682 def Xi64 : X86TypeInfo
675683 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
676 1, 0, 1>;
684 1, 0, 0, 1>;
677685
678686 /// ITy - This instruction base class takes the type info for the instruction.
679687 /// Using this, it:
694702
695703 // Infer instruction prefixes from type info.
696704 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
705 let hasOpSize16Prefix = typeinfo.HasOpSize16Prefix;
697706 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
698707 }
699708
2727 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
2828 [(set GR32:$dst,
2929 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
30 IIC_CMOV32_RR>, TB;
30 IIC_CMOV32_RR>, TB, OpSize16;
3131 def NAME#64rr
3232 :RI
3333 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
4848 : I
4949 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
5050 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
51 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
51 CondNode, EFLAGS))], IIC_CMOV32_RM>,
52 TB, OpSize16;
5253 def NAME#64rm
5354 :RI
5455 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
222222 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
223223 isPseudo = 1 in
224224 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
225 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
225 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, OpSize16,
226 Sched<[WriteZero]>;
226227
227228 // Other widths can also make use of the 32-bit xor, which may have a smaller
228229 // encoding and avoid partial register updates.
322323 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
323324 Requires<[Not64BitMode]>;
324325 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
325 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
326 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize16,
326327 Requires<[Not64BitMode]>;
327328 }
328329
353354 Requires<[Not64BitMode]>;
354355 let Uses = [EAX,ECX,EDI] in
355356 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
356 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
357 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize16,
357358 Requires<[Not64BitMode]>;
358359 }
359360
623624 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
624625 !strconcat(mnemonic, "{l}\t",
625626 "{$src2, $dst|$dst, $src2}"),
626 [], IIC_ALU_NONMEM>, LOCK;
627 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
627628 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
628629 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
629630 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
650651 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
651652 !strconcat(mnemonic, "{l}\t",
652653 "{$src2, $dst|$dst, $src2}"),
653 [], IIC_ALU_MEM>, LOCK;
654 [], IIC_ALU_MEM>, OpSize16, LOCK;
654655
655656 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
656657 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
670671 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
671672 !strconcat(mnemonic, "{l}\t",
672673 "{$src2, $dst|$dst, $src2}"),
673 [], IIC_ALU_MEM>, LOCK;
674 [], IIC_ALU_MEM>, OpSize16, LOCK;
674675 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
675676 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
676677 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
702703 [], IIC_UNARY_MEM>, OpSize, LOCK;
703704 def NAME#32m : I
704705 !strconcat(mnemonic, "{l}\t$dst"),
705 [], IIC_UNARY_MEM>, LOCK;
706 [], IIC_UNARY_MEM>, OpSize16, LOCK;
706707 def NAME#64m : RI
707708 !strconcat(mnemonic, "{q}\t$dst"),
708709 [], IIC_UNARY_MEM>, LOCK;
738739 let Defs = [EAX, EFLAGS], Uses = [EAX] in
739740 def NAME#32 : I
740741 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
741 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
742 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize16, LOCK;
742743 let Defs = [RAX, EFLAGS], Uses = [RAX] in
743744 def NAME#64 : RI
744745 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
788789 [(set
789790 GR32:$dst,
790791 (!cast(frag # "_32") addr:$ptr, GR32:$val))],
791 itin>;
792 itin>, OpSize16;
792793 def NAME#64 : RI
793794 (ins GR64:$val, i64mem:$ptr),
794795 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
2222 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
2323 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
2424 "ret",
25 [(X86retflag 0)], IIC_RET>;
25 [(X86retflag 0)], IIC_RET>, OpSize16;
2626 def RETW : I <0xC3, RawFrm, (outs), (ins),
2727 "ret{w}",
2828 [], IIC_RET>, OpSize;
2929 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
3030 "ret\t$amt",
31 [(X86retflag timm:$amt)], IIC_RET_IMM>;
31 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize16;
3232 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
3333 "ret{w}\t$amt",
3434 [], IIC_RET_IMM>, OpSize;
3535 def LRETL : I <0xCB, RawFrm, (outs), (ins),
36 "{l}ret{l|f}", [], IIC_RET>;
36 "{l}ret{l|f}", [], IIC_RET>, OpSize16;
3737 def LRETW : I <0xCB, RawFrm, (outs), (ins),
3838 "{l}ret{w|f}", [], IIC_RET>, OpSize;
3939 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
4040 "{l}ret{q|f}", [], IIC_RET>;
4141 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
42 "{l}ret{l|f}\t$amt", [], IIC_RET>;
42 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize16;
4343 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
4444 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
4545 }
4747 // Unconditional branches.
4848 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
4949 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
50 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
50 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16;
5151 let hasSideEffects = 0 in
5252 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
5353 "jmp\t$dst", [], IIC_JMP_REL>;
6060 def _1 : Ii8PCRel
6161 IIC_Jcc>;
6262 def _4 : Ii32PCRel
63 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB;
63 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
64 OpSize16;
6465 }
6566 }
6667
108109 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
109110 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
110111 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
111 Sched<[WriteJump]>;
112 OpSize16, Sched<[WriteJump]>;
112113 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
113114 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
114 Requires<[Not64BitMode]>, Sched<[WriteJumpLd]>;
115 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
115116
116117 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
117118 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
127128 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
128129 (ins i32imm:$off, i16imm:$seg),
129130 "ljmp{l}\t{$seg, $off|$off, $seg}", [],
130 IIC_JMP_FAR_PTR>, Sched<[WriteJump]>;
131 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
131132 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
132133 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
133134 Sched<[WriteJump]>;
136137 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
137138 Sched<[WriteJumpLd]>;
138139 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
139 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
140 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
140141 Sched<[WriteJumpLd]>;
141142 }
142143
159160 let Uses = [ESP] in {
160161 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
161162 (outs), (ins i32imm_pcrel:$dst),
162 "call{l}\t$dst", [], IIC_CALL_RI>,
163 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize16,
163164 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
164165 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
165166 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
166 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
167 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
167168 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
168169 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
169 IIC_CALL_MEM>,
170 IIC_CALL_MEM>, OpSize16,
170171 Requires<[Not64BitMode,FavorMemIndirectCall]>,
171172 Sched<[WriteJumpLd]>;
172173
177178 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
178179 (ins i32imm:$off, i16imm:$seg),
179180 "lcall{l}\t{$seg, $off|$off, $seg}", [],
180 IIC_CALL_FAR_PTR>, Sched<[WriteJump]>;
181 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
181182
182183 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
183184 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
184185 Sched<[WriteJumpLd]>;
185186 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
186 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
187 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
187188 Sched<[WriteJumpLd]>;
188189
189190 // callw for 16 bit code for the assembler.
1616 "{cbtw|cbw}", [], IIC_CBW>, OpSize; // AX = signext(AL)
1717 let Defs = [EAX], Uses = [AX] in
1818 def CWDE : I<0x98, RawFrm, (outs), (ins),
19 "{cwtl|cwde}", [], IIC_CBW>; // EAX = signext(AX)
19 "{cwtl|cwde}", [], IIC_CBW>, OpSize16; // EAX = signext(AX)
2020
2121 let Defs = [AX,DX], Uses = [AX] in
2222 def CWD : I<0x99, RawFrm, (outs), (ins),
2323 "{cwtd|cwd}", [], IIC_CBW>, OpSize; // DX:AX = signext(AX)
2424 let Defs = [EAX,EDX], Uses = [EAX] in
2525 def CDQ : I<0x99, RawFrm, (outs), (ins),
26 "{cltd|cdq}", [], IIC_CBW>; // EDX:EAX = signext(EAX)
26 "{cltd|cdq}", [], IIC_CBW>, OpSize16; // EDX:EAX = signext(EAX)
2727
2828
2929 let Defs = [RAX], Uses = [EAX] in
5050 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
5151 "movs{bl|x}\t{$src, $dst|$dst, $src}",
5252 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
53 Sched<[WriteALU]>;
53 OpSize16, Sched<[WriteALU]>;
5454 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
5555 "movs{bl|x}\t{$src, $dst|$dst, $src}",
5656 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
57 Sched<[WriteALULd]>;
57 OpSize16, Sched<[WriteALULd]>;
5858 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
5959 "movs{wl|x}\t{$src, $dst|$dst, $src}",
6060 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
61 Sched<[WriteALU]>;
61 OpSize16, Sched<[WriteALU]>;
6262 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
6363 "movs{wl|x}\t{$src, $dst|$dst, $src}",
6464 [(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>,
65 TB, Sched<[WriteALULd]>;
65 OpSize16, TB, Sched<[WriteALULd]>;
6666
6767 let neverHasSideEffects = 1 in {
6868 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
7676 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
7777 "movz{bl|x}\t{$src, $dst|$dst, $src}",
7878 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
79 Sched<[WriteALU]>;
79 OpSize16, Sched<[WriteALU]>;
8080 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
8181 "movz{bl|x}\t{$src, $dst|$dst, $src}",
8282 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
83 Sched<[WriteALULd]>;
83 OpSize16, Sched<[WriteALULd]>;
8484 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
8585 "movz{wl|x}\t{$src, $dst|$dst, $src}",
8686 [(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB,
87 Sched<[WriteALU]>;
87 OpSize16, Sched<[WriteALU]>;
8888 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
8989 "movz{wl|x}\t{$src, $dst|$dst, $src}",
9090 [(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>,
91 TB, Sched<[WriteALULd]>;
91 TB, OpSize16, Sched<[WriteALULd]>;
9292
9393 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
9494 // except that they use GR32_NOREX for the output operand register class
887887 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
888888 IIC_POP_REG16>, OpSize;
889889 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
890 IIC_POP_REG>, Requires<[Not64BitMode]>;
890 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
891891 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
892892 IIC_POP_REG>, OpSize;
893893 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
894894 IIC_POP_MEM>, OpSize;
895895 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
896 IIC_POP_REG>, Requires<[Not64BitMode]>;
896 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
897897 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
898898 IIC_POP_MEM>, Requires<[Not64BitMode]>;
899899
900900 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
901901 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
902 Requires<[Not64BitMode]>;
902 OpSize16, Requires<[Not64BitMode]>;
903903 } // mayLoad, SchedRW
904904
905905 let mayStore = 1, SchedRW = [WriteStore] in {
906906 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
907907 IIC_PUSH_REG>, OpSize;
908908 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
909 IIC_PUSH_REG>, Requires<[Not64BitMode]>;
909 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
910910 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
911911 IIC_PUSH_REG>, OpSize;
912912 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
913 IIC_PUSH_MEM>,
914 OpSize;
913 IIC_PUSH_MEM>, OpSize;
915914 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
916 IIC_PUSH_REG>, Requires<[Not64BitMode]>;
915 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
917916 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
918 IIC_PUSH_MEM>, Requires<[Not64BitMode]>;
917 IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
919918
920919 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
921 "push{l}\t$imm", [], IIC_PUSH_IMM>, Requires<[Not64BitMode]>;
920 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
921 Requires<[Not64BitMode]>;
922922 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
923923 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
924924 Requires<[Not64BitMode]>;
925925 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
926 "push{l}\t$imm", [], IIC_PUSH_IMM>, Requires<[Not64BitMode]>;
926 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
927 Requires<[Not64BitMode]>;
927928
928929 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
929930 OpSize;
930931 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
931 Requires<[Not64BitMode]>;
932 OpSize16, Requires<[Not64BitMode]>;
932933
933934 } // mayStore, SchedRW
934935 }
973974 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
974975 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
975976 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
976 Requires<[Not64BitMode]>;
977 OpSize16, Requires<[Not64BitMode]>;
977978 }
978979 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
979980 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
980981 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
981 Requires<[Not64BitMode]>;
982 OpSize16, Requires<[Not64BitMode]>;
982983 }
983984
984985 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
986987 def BSWAP32r : I<0xC8, AddRegFrm,
987988 (outs GR32:$dst), (ins GR32:$src),
988989 "bswap{l}\t$dst",
989 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
990 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
990991
991992 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
992993 "bswap{q}\t$dst",
10061007 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
10071008 "bsf{l}\t{$src, $dst|$dst, $src}",
10081009 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1009 IIC_BIT_SCAN_REG>, TB,
1010 IIC_BIT_SCAN_REG>, TB, OpSize16,
10101011 Sched<[WriteShift]>;
10111012 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
10121013 "bsf{l}\t{$src, $dst|$dst, $src}",
10131014 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1014 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1015 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
10151016 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
10161017 "bsf{q}\t{$src, $dst|$dst, $src}",
10171018 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
10341035 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
10351036 "bsr{l}\t{$src, $dst|$dst, $src}",
10361037 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1037 IIC_BIT_SCAN_REG>, TB,
1038 IIC_BIT_SCAN_REG>, TB, OpSize16,
10381039 Sched<[WriteShift]>;
10391040 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
10401041 "bsr{l}\t{$src, $dst|$dst, $src}",
10411042 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1042 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1043 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
10431044 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
10441045 "bsr{q}\t{$src, $dst|$dst, $src}",
10451046 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
10551056 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
10561057 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
10571058 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
1058 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
1059 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>, OpSize16;
10591060 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
10601061 }
10611062
10651066 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
10661067 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
10671068 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1068 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
1069 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>, OpSize16;
10691070 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
10701071 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
10711072
10721073 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
10731074 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
1074 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
1075 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,
1076 OpSize16;
10751077 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
10761078
10771079 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
10781080 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
1079 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
1081 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>,
1082 OpSize16;
10801083 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
10811084 } // SchedRW
10821085
10901093 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
10911094 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
10921095 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1093 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1096 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
10941097 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
10951098 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
10961099 }
11041107 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
11051108 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
11061109 "mov{l}\t{$src, $dst|$dst, $src}",
1107 [(set GR32:$dst, imm:$src)], IIC_MOV>;
1110 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
11081111 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
11091112 "movabs{q}\t{$src, $dst|$dst, $src}",
11101113 [(set GR64:$dst, imm:$src)], IIC_MOV>;
11231126 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
11241127 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
11251128 "mov{l}\t{$src, $dst|$dst, $src}",
1126 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1129 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
11271130 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
11281131 "mov{q}\t{$src, $dst|$dst, $src}",
11291132 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
11431146 Requires<[Not64BitMode]>;
11441147 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
11451148 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1146 Requires<[Not64BitMode]>;
1149 OpSize16, Requires<[Not64BitMode]>;
11471150 }
11481151 let mayStore = 1 in {
11491152 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
11541157 Requires<[Not64BitMode]>;
11551158 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
11561159 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1157 Requires<[Not64BitMode]>;
1160 OpSize16, Requires<[Not64BitMode]>;
11581161 }
11591162 }
11601163
11981201 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
11991202 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
12001203 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1201 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1204 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
12021205 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
12031206 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
12041207 }
12121215 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
12131216 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
12141217 "mov{l}\t{$src, $dst|$dst, $src}",
1215 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1218 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
12161219 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
12171220 "mov{q}\t{$src, $dst|$dst, $src}",
12181221 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
12271230 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
12281231 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
12291232 "mov{l}\t{$src, $dst|$dst, $src}",
1230 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1233 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
12311234 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
12321235 "mov{q}\t{$src, $dst|$dst, $src}",
12331236 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
12771280 OpSize, TB;
12781281 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
12791282 "bt{l}\t{$src2, $src1|$src1, $src2}",
1280 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1283 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1284 OpSize16, TB;
12811285 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
12821286 "bt{q}\t{$src2, $src1|$src1, $src2}",
12831287 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
13001304 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
13011305 // (implicit EFLAGS)]
13021306 [], IIC_BT_MR
1303 >, TB, Requires<[FastBTMem]>;
1307 >, OpSize16, TB, Requires<[FastBTMem]>;
13041308 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
13051309 "bt{q}\t{$src2, $src1|$src1, $src2}",
13061310 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
13171321 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
13181322 "bt{l}\t{$src2, $src1|$src1, $src2}",
13191323 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1320 IIC_BT_RI>, TB;
1324 IIC_BT_RI>, OpSize16, TB;
13211325 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
13221326 "bt{q}\t{$src2, $src1|$src1, $src2}",
13231327 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
13351339 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
13361340 "bt{l}\t{$src2, $src1|$src1, $src2}",
13371341 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1338 ], IIC_BT_MI>, TB;
1342 ], IIC_BT_MI>, OpSize16, TB;
13391343 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
13401344 "bt{q}\t{$src2, $src1|$src1, $src2}",
13411345 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
13481352 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
13491353 OpSize, TB;
13501354 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1351 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1355 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1356 OpSize16, TB;
13521357 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
13531358 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
13541359 } // SchedRW
13581363 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
13591364 OpSize, TB;
13601365 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1361 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1366 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1367 OpSize16, TB;
13621368 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
13631369 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
13641370 }
13681374 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
13691375 OpSize, TB;
13701376 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1371 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1377 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1378 OpSize16, TB;
13721379 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
13731380 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
13741381 } // SchedRW
13781385 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
13791386 OpSize, TB;
13801387 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1381 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1388 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1389 OpSize16, TB;
13821390 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
13831391 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
13841392 }
13881396 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
13891397 OpSize, TB;
13901398 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1391 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1399 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1400 OpSize16, TB;
13921401 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
13931402 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
13941403 } // SchedRW
13981407 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
13991408 OpSize, TB;
14001409 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1401 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1410 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1411 OpSize16, TB;
14021412 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
14031413 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
14041414 }
14081418 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
14091419 OpSize, TB;
14101420 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1411 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1421 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1422 OpSize16, TB;
14121423 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
14131424 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
14141425 } // SchedRW
14181429 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
14191430 OpSize, TB;
14201431 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1421 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1432 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1433 OpSize16, TB;
14221434 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
14231435 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
14241436 }
14281440 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
14291441 OpSize, TB;
14301442 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1431 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1443 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1444 OpSize16, TB;
14321445 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
14331446 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
14341447 } // SchedRW
14381451 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
14391452 OpSize, TB;
14401453 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1441 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1454 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1455 OpSize16, TB;
14421456 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
14431457 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
14441458 }
14481462 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
14491463 OpSize, TB;
14501464 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1451 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1465 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1466 OpSize16, TB;
14521467 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
14531468 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
14541469 } // SchedRW
14581473 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
14591474 OpSize, TB;
14601475 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1461 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1476 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1477 OpSize16, TB;
14621478 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
14631479 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
14641480 }
14951511 [(set
14961512 GR32:$dst,
14971513 (!cast(frag # "_32") addr:$ptr, GR32:$val))],
1498 itin>;
1514 itin>, OpSize16;
14991515 def NAME#64rm : RI
15001516 (ins GR64:$val, i64mem:$ptr),
15011517 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
15161532 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
15171533 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
15181534 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1519 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1535 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1536 OpSize16;
15201537 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
15211538 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
15221539 }
15261543 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
15271544 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
15281545 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1529 Requires<[Not64BitMode]>;
1546 OpSize16, Requires<[Not64BitMode]>;
15301547 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
15311548 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
15321549 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
15431560 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
15441561 OpSize;
15451562 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1546 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1563 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1564 OpSize16;
15471565 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
15481566 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
15491567 } // SchedRW
15551573 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
15561574 OpSize;
15571575 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1558 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1576 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1577 OpSize16;
15591578 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
15601579 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
15611580
15701589 IIC_CMPXCHG_REG>, TB, OpSize;
15711590 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
15721591 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1573 IIC_CMPXCHG_REG>, TB;
1592 IIC_CMPXCHG_REG>, TB, OpSize16;
15741593 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
15751594 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
15761595 IIC_CMPXCHG_REG>, TB;
15861605 IIC_CMPXCHG_MEM>, TB, OpSize;
15871606 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
15881607 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1589 IIC_CMPXCHG_MEM>, TB;
1608 IIC_CMPXCHG_MEM>, TB, OpSize16;
15901609 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
15911610 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
15921611 IIC_CMPXCHG_MEM>, TB;
16271646 let SchedRW = [WriteMicrocoded] in {
16281647 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
16291648 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1630 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1649 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>, OpSize16;
16311650 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
16321651 }
16331652
16341653 let SchedRW = [WriteSystem] in {
16351654 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
16361655 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1637 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1656 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>, OpSize16;
16381657 }
16391658
16401659 // Flag instructions
16921711 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
16931712 Requires<[Not64BitMode]>;
16941713 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1695 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1714 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
16961715 Requires<[Not64BitMode]>;
16971716
16981717 // Adjust RPL Field of Segment Selector
17161735 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
17171736 "movbe{l}\t{$src, $dst|$dst, $src}",
17181737 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1719 T8;
1738 OpSize16, T8;
17201739 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
17211740 "movbe{q}\t{$src, $dst|$dst, $src}",
17221741 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
17301749 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
17311750 "movbe{l}\t{$src, $dst|$dst, $src}",
17321751 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1733 T8;
1752 OpSize16, T8;
17341753 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
17351754 "movbe{q}\t{$src, $dst|$dst, $src}",
17361755 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
17471766 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
17481767 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
17491768 "rdrand{l}\t$dst",
1750 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1769 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
17511770 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
17521771 "rdrand{q}\t$dst",
17531772 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
17621781 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
17631782 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
17641783 "rdseed{l}\t$dst",
1765 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB;
1784 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
17661785 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
17671786 "rdseed{q}\t$dst",
17681787 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
17831802
17841803 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
17851804 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1786 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1805 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1806 OpSize16;
17871807 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
17881808 "lzcnt{l}\t{$src, $dst|$dst, $src}",
17891809 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1790 (implicit EFLAGS)]>, XS;
1810 (implicit EFLAGS)]>, XS, OpSize16;
17911811
17921812 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
17931813 "lzcnt{q}\t{$src, $dst|$dst, $src}",
18141834
18151835 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
18161836 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1817 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1837 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
1838 OpSize16;
18181839 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
18191840 "tzcnt{l}\t{$src, $dst|$dst, $src}",
18201841 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1821 (implicit EFLAGS)]>, XS;
1842 (implicit EFLAGS)]>, XS, OpSize16;
18221843
18231844 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
18241845 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2424 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
2525 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2626 "shl{l}\t{%cl, $dst|$dst, cl}",
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize16;
2828 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
2929 "shl{q}\t{%cl, $dst|$dst, cl}",
3030 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
4141 OpSize;
4242 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
4343 "shl{l}\t{$src2, $dst|$dst, $src2}",
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>;
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
45 OpSize16;
4546 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
4647 (ins GR64:$src1, i8imm:$src2),
4748 "shl{q}\t{$src2, $dst|$dst, $src2}",
5657 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
5758 "shl{w}\t$dst", [], IIC_SR>, OpSize;
5859 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
59 "shl{l}\t$dst", [], IIC_SR>;
60 "shl{l}\t$dst", [], IIC_SR>, OpSize16;
6061 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
6162 "shl{q}\t$dst", [], IIC_SR>;
6263 } // hasSideEffects = 0
7778 OpSize;
7879 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
7980 "shl{l}\t{%cl, $dst|$dst, cl}",
80 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
81 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
82 OpSize16;
8183 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
8284 "shl{q}\t{%cl, $dst|$dst, cl}",
8385 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
9496 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
9597 "shl{l}\t{$src, $dst|$dst, $src}",
9698 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
97 IIC_SR>;
99 IIC_SR>, OpSize16;
98100 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
99101 "shl{q}\t{$src, $dst|$dst, $src}",
100102 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
113115 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
114116 "shl{l}\t$dst",
115117 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
116 IIC_SR>;
118 IIC_SR>, OpSize16;
117119 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
118120 "shl{q}\t$dst",
119121 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
130132 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
131133 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
132134 "shr{l}\t{%cl, $dst|$dst, cl}",
133 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
135 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize16;
134136 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
135137 "shr{q}\t{%cl, $dst|$dst, cl}",
136138 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
146148 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
147149 "shr{l}\t{$src2, $dst|$dst, $src2}",
148150 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
149 IIC_SR>;
151 IIC_SR>, OpSize16;
150152 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
151153 "shr{q}\t{$src2, $dst|$dst, $src2}",
152154 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
160162 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
161163 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
162164 "shr{l}\t$dst",
163 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>;
165 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize16;
164166 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
165167 "shr{q}\t$dst",
166168 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
178180 OpSize;
179181 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
180182 "shr{l}\t{%cl, $dst|$dst, cl}",
181 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
183 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
184 OpSize16;
182185 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
183186 "shr{q}\t{%cl, $dst|$dst, cl}",
184187 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
195198 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
196199 "shr{l}\t{$src, $dst|$dst, $src}",
197200 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
198 IIC_SR>;
201 IIC_SR>, OpSize16;
199202 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
200203 "shr{q}\t{$src, $dst|$dst, $src}",
201204 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
213216 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
214217 "shr{l}\t$dst",
215218 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
216 IIC_SR>;
219 IIC_SR>, OpSize16;
217220 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
218221 "shr{q}\t$dst",
219222 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
233236 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
234237 "sar{l}\t{%cl, $dst|$dst, cl}",
235238 [(set GR32:$dst, (sra GR32:$src1, CL))],
236 IIC_SR>;
239 IIC_SR>, OpSize16;
237240 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
238241 "sar{q}\t{%cl, $dst|$dst, cl}",
239242 [(set GR64:$dst, (sra GR64:$src1, CL))],
252255 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
253256 "sar{l}\t{$src2, $dst|$dst, $src2}",
254257 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
255 IIC_SR>;
258 IIC_SR>, OpSize16;
256259 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
257260 (ins GR64:$src1, i8imm:$src2),
258261 "sar{q}\t{$src2, $dst|$dst, $src2}",
271274 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
272275 "sar{l}\t$dst",
273276 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
274 IIC_SR>;
277 IIC_SR>, OpSize16;
275278 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
276279 "sar{q}\t$dst",
277280 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
292295 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
293296 "sar{l}\t{%cl, $dst|$dst, cl}",
294297 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
295 IIC_SR>;
298 IIC_SR>, OpSize16;
296299 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
297300 "sar{q}\t{%cl, $dst|$dst, cl}",
298301 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
310313 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
311314 "sar{l}\t{$src, $dst|$dst, $src}",
312315 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
313 IIC_SR>;
316 IIC_SR>, OpSize16;
314317 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
315318 "sar{q}\t{$src, $dst|$dst, $src}",
316319 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
329332 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
330333 "sar{l}\t$dst",
331334 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
332 IIC_SR>;
335 IIC_SR>, OpSize16;
333336 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
334337 "sar{q}\t$dst",
335338 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
359362 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
360363
361364 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
362 "rcl{l}\t$dst", [], IIC_SR>;
365 "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
363366 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
364 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
367 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
365368 let Uses = [CL] in
366369 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
367 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
370 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
368371
369372
370373 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
393396 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
394397
395398 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
396 "rcr{l}\t$dst", [], IIC_SR>;
399 "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
397400 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
398 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
401 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
399402 let Uses = [CL] in
400403 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
401 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
404 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
402405
403406 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
404407 "rcr{q}\t$dst", [], IIC_SR>;
420423 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
421424 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
422425 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
423 "rcl{l}\t$dst", [], IIC_SR>;
426 "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
424427 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
425 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
428 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
426429 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
427430 "rcl{q}\t$dst", [], IIC_SR>;
428431 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
437440 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
438441 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
439442 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
440 "rcr{l}\t$dst", [], IIC_SR>;
443 "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
441444 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
442 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
445 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
443446 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
444447 "rcr{q}\t$dst", [], IIC_SR>;
445448 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
451454 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
452455 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
453456 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
454 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
457 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
455458 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
456459 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
457460
460463 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
461464 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
462465 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
463 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
466 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
464467 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
465468 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
466469 }
478481 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
479482 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
480483 "rol{l}\t{%cl, $dst|$dst, cl}",
481 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
484 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize16;
482485 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
483486 "rol{q}\t{%cl, $dst|$dst, cl}",
484487 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
495498 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
496499 "rol{l}\t{$src2, $dst|$dst, $src2}",
497500 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
498 IIC_SR>;
501 IIC_SR>, OpSize16;
499502 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
500503 (ins GR64:$src1, i8imm:$src2),
501504 "rol{q}\t{$src2, $dst|$dst, $src2}",
514517 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
515518 "rol{l}\t$dst",
516519 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
517 IIC_SR>;
520 IIC_SR>, OpSize16;
518521 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
519522 "rol{q}\t$dst",
520523 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
534537 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
535538 "rol{l}\t{%cl, $dst|$dst, cl}",
536539 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
537 IIC_SR>;
540 IIC_SR>, OpSize16;
538541 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
539542 "rol{q}\t{%cl, $dst|$dst, cl}",
540543 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
552555 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
553556 "rol{l}\t{$src1, $dst|$dst, $src1}",
554557 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
555 IIC_SR>;
558 IIC_SR>, OpSize16;
556559 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
557560 "rol{q}\t{$src1, $dst|$dst, $src1}",
558561 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
571574 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
572575 "rol{l}\t$dst",
573576 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
574 IIC_SR>;
577 IIC_SR>, OpSize16;
575578 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
576579 "rol{q}\t$dst",
577580 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
588591 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
589592 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
590593 "ror{l}\t{%cl, $dst|$dst, cl}",
591 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
594 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize16;
592595 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
593596 "ror{q}\t{%cl, $dst|$dst, cl}",
594597 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
605608 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
606609 "ror{l}\t{$src2, $dst|$dst, $src2}",
607610 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
608 IIC_SR>;
611 IIC_SR>, OpSize16;
609612 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
610613 (ins GR64:$src1, i8imm:$src2),
611614 "ror{q}\t{$src2, $dst|$dst, $src2}",
624627 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
625628 "ror{l}\t$dst",
626629 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
627 IIC_SR>;
630 IIC_SR>, OpSize16;
628631 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
629632 "ror{q}\t$dst",
630633 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
644647 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
645648 "ror{l}\t{%cl, $dst|$dst, cl}",
646649 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
647 IIC_SR>;
650 IIC_SR>, OpSize16;
648651 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
649652 "ror{q}\t{%cl, $dst|$dst, cl}",
650653 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
662665 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
663666 "ror{l}\t{$src, $dst|$dst, $src}",
664667 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
665 IIC_SR>;
668 IIC_SR>, OpSize16;
666669 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
667670 "ror{q}\t{$src, $dst|$dst, $src}",
668671 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
681684 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
682685 "ror{l}\t$dst",
683686 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
684 IIC_SR>;
687 IIC_SR>, OpSize16;
685688 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
686689 "ror{q}\t$dst",
687690 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
712715 (ins GR32:$src1, GR32:$src2),
713716 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
714717 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
715 IIC_SHD32_REG_CL>, TB;
718 IIC_SHD32_REG_CL>, TB, OpSize16;
716719 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
717720 (ins GR32:$src1, GR32:$src2),
718721 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
719722 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
720 IIC_SHD32_REG_CL>, TB;
723 IIC_SHD32_REG_CL>, TB, OpSize16;
721724 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
722725 (ins GR64:$src1, GR64:$src2),
723726 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
753756 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
754757 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
755758 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
756 TB;
759 TB, OpSize16;
757760 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
758761 (outs GR32:$dst),
759762 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
760763 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
761764 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
762765 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
763 TB;
766 TB, OpSize16;
764767 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
765768 (outs GR64:$dst),
766769 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
792795 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
793796 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
794797 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
795 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
798 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
796799 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
797800 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
798801 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
799 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
802 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
800803
801804 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
802805 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
829832 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
830833 (i8 imm:$src3)), addr:$dst)],
831834 IIC_SHD32_MEM_IM>,
832 TB;
835 TB, OpSize16;
833836 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
834837 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
835838 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
836839 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
837840 (i8 imm:$src3)), addr:$dst)],
838841 IIC_SHD32_MEM_IM>,
839 TB;
842 TB, OpSize16;
840843
841844 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
842845 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
6464 Requires<[In64BitMode]>;
6565
6666 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
67 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;
67 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
68 OpSize16;
6869 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
6970 Requires<[In64BitMode]>;
7071 } // SchedRW
8283 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
8384 let Defs = [EAX], Uses = [DX] in
8485 def IN32rr : I<0xED, RawFrm, (outs), (ins),
85 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>;
86 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;
8687
8788 let Defs = [AL] in
8889 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
9293 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
9394 let Defs = [EAX] in
9495 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
95 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>;
96 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize16;
9697
9798 let Uses = [DX, AL] in
9899 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
102103 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
103104 let Uses = [DX, EAX] in
104105 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
105 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>;
106 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;
106107
107108 let Uses = [AL] in
108109 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
112113 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
113114 let Uses = [EAX] in
114115 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
115 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>;
116 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
116117
117118 def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
118119 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
119 def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;
120 def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>, OpSize16;
120121 } // SchedRW
121122
122123 //===----------------------------------------------------------------------===//
176177 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
177178 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
178179 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
179 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
180 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
180181 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
181182 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
182183
183184 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
184185 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
185186 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
186 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
187 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
187188 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
188189 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
189190
190191 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
191192 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
192193 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
193 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
194 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
194195 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
195196 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
196197
197198 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
198199 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
199200 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
200 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
201 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
201202 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
202203 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
203204 } // SchedRW
215216
216217 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
217218 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
218 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
219 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
220 OpSize16;
219221 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
220 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
222 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
223 OpSize16;
221224 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
222225 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
223226 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
229232 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
230233 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
231234 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
232 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
235 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
236 OpSize16;
233237 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
234 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
238 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
239 OpSize16;
235240 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
236241 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
237242 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
243248 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
244249 "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
245250 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
246 "str{l}\t$dst", [], IIC_STR>, TB;
251 "str{l}\t$dst", [], IIC_STR>, TB, OpSize16;
247252 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
248253 "str{q}\t$dst", [], IIC_STR>, TB;
249254 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
255260 "ltr{w}\t$src", [], IIC_LTR>, TB;
256261
257262 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
258 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,
259 OpSize;
263 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
264 OpSize, Requires<[Not64BitMode]>;
260265 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
261 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>, Requires<[Not64BitMode]>;
266 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
267 OpSize16, Requires<[Not64BitMode]>;
262268 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
263 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,
264 OpSize;
269 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
270 OpSize, Requires<[Not64BitMode]>;
265271 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
266 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>;
272 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
273 OpSize16, Requires<[Not64BitMode]>;
267274 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
268 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,
269 OpSize;
275 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
276 OpSize, Requires<[Not64BitMode]>;
270277 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
271 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>;
278 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
279 OpSize16, Requires<[Not64BitMode]>;
272280 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
273 "push{w}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>,
274 OpSize;
281 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
282 OpSize, Requires<[Not64BitMode]>;
275283 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
276 "push{l}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[Not64BitMode]>;
277
284 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
285 OpSize16, Requires<[Not64BitMode]>;
278286 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
279287 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
280288 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
281 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[Not64BitMode]>;
289 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
290 OpSize16, Requires<[Not64BitMode]>;
282291 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
283292 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
284293 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
285 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[Not64BitMode]>;
286
294 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
295 OpSize16, Requires<[Not64BitMode]>;
287296 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
288297 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
289298 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
295304 OpSize, Requires<[Not64BitMode]>;
296305 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
297306 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
298 Requires<[Not64BitMode]>;
307 OpSize16, Requires<[Not64BitMode]>;
299308
300309 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
301310 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
302311 OpSize, Requires<[Not64BitMode]>;
303312 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
304313 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
305 Requires<[Not64BitMode]>;
314 OpSize16, Requires<[Not64BitMode]>;
306315
307316 def POPES16 : I<0x07, RawFrm, (outs), (ins),
308317 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
309318 OpSize, Requires<[Not64BitMode]>;
310319 def POPES32 : I<0x07, RawFrm, (outs), (ins),
311320 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
312 Requires<[Not64BitMode]>;
321 OpSize16, Requires<[Not64BitMode]>;
313322
314323 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
315324 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
316325 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
317 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[Not64BitMode]>;
326 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
327 OpSize16, Requires<[Not64BitMode]>;
318328 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
319329 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
320330
321331 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
322332 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
323333 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
324 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[Not64BitMode]>;
334 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
335 OpSize16, Requires<[Not64BitMode]>;
325336 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
326337 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
327338
329340 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
330341 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
331342 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
332 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
343 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
333344
334345 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
335346 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
336347 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
337 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
348 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
338349 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
339350 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
340351
341352 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
342353 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
343354 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
344 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
355 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
345356
346357 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
347358 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
348359 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
349 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
360 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
350361 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
351362 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
352363
353364 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
354365 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
355366 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
356 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
367 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
357368
358369 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
359370 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
376387 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
377388 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[Not64BitMode]>;
378389 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
379 "sgdt\t$dst", [], IIC_SGDT>, TB;
390 "sgdt\t$dst", [], IIC_SGDT>, OpSize16, TB;
380391 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
381392 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[Not64BitMode]>;
382393 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
383 "sidt\t$dst", []>, TB;
394 "sidt\t$dst", []>, OpSize16, TB;
384395 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
385396 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
386397 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
387398 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
388399 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
389 "sldt{l}\t$dst", [], IIC_SLDT>, TB;
400 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;
390401
391402 // LLDT is not interpreted specially in 64-bit mode because there is no sign
392403 // extension.
398409 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
399410 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[Not64BitMode]>;
400411 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
401 "lgdt\t$src", [], IIC_LGDT>, TB;
412 "lgdt\t$src", [], IIC_LGDT>, OpSize16, TB;
402413 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
403414 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[Not64BitMode]>;
404415 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
405 "lidt\t$src", [], IIC_LIDT>, TB;
416 "lidt\t$src", [], IIC_LIDT>, OpSize16, TB;
406417 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
407418 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
408419 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
419430 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
420431 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
421432 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
422 "smsw{l}\t$dst", [], IIC_SMSW>, TB;
433 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;
423434 // no m form encodable; use SMSW16m
424435 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
425436 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
11
22 .code16
33
4 movl $0x12345678, %ebx
5 // CHECK: movl
6 // CHECK: encoding: [0x66,0xbb,0x78,0x56,0x34,0x12]
47 pause
58 // CHECK: pause
69 // CHECK: encoding: [0xf3,0x90]
2326 // CHECK: encoding: [0x0f,0x01,0xf9]
2427
2528
29 // CHECK: movl %eax, 16(%ebp) # encoding: [0x67,0x66,0x89,0x45,0x10]
30 movl %eax, 16(%ebp)
31 // CHECK: movl %eax, -16(%ebp) # encoding: [0x67,0x66,0x89,0x45,0xf0]
32 movl %eax, -16(%ebp)
33
2634 // CHECK: testb %bl, %cl # encoding: [0x84,0xcb]
2735 testb %bl, %cl
2836
37 // CHECK: cmpl %eax, %ebx # encoding: [0x66,0x39,0xc3]
38 cmpl %eax, %ebx
39
2940 // CHECK: addw %ax, %ax # encoding: [0x01,0xc0]
3041 addw %ax, %ax
42
43 // CHECK: shrl %eax # encoding: [0x66,0xd1,0xe8]
44 shrl $1, %eax
45
46 // CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]
47 sall $1, %eax
48 // CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]
49 sal $1, %eax
3150
3251 into
3352 // CHECK: into
4261 // CHECK: int $255
4362 // CHECK: encoding: [0xcd,0xff]
4463
64 // CHECK: pushfl # encoding: [0x66,0x9c]
65 pushfl
66 // CHECK: popfl # encoding: [0x66,0x9d]
67 popfl
68
69 // CHECK: cmoval %eax, %edx
70 // CHECK: encoding: [0x66,0x0f,0x47,0xd0]
71 cmoval %eax,%edx
72
73 // CHECK: cmovael %eax, %edx
74 // CHECK: encoding: [0x66,0x0f,0x43,0xd0]
75 cmovael %eax,%edx
76
77 // CHECK: cmovbel %eax, %edx
78 // CHECK: encoding: [0x66,0x0f,0x46,0xd0]
79 cmovbel %eax,%edx
80
81 // CHECK: cmovbl %eax, %edx
82 // CHECK: encoding: [0x66,0x0f,0x42,0xd0]
83 cmovbl %eax,%edx
84
4585 // CHECK: cmovbw %bx, %bx
4686 cmovnae %bx,%bx
4787
88
89 // CHECK: cmovbel %eax, %edx
90 // CHECK: encoding: [0x66,0x0f,0x46,0xd0]
91 cmovbel %eax,%edx
92
93 // CHECK: cmovbl %eax, %edx
94 // CHECK: encoding: [0x66,0x0f,0x42,0xd0]
95 cmovcl %eax,%edx
96
97 // CHECK: cmovel %eax, %edx
98 // CHECK: encoding: [0x66,0x0f,0x44,0xd0]
99 cmovel %eax,%edx
100
101 // CHECK: cmovgl %eax, %edx
102 // CHECK: encoding: [0x66,0x0f,0x4f,0xd0]
103 cmovgl %eax,%edx
104
105 // CHECK: cmovgel %eax, %edx
106 // CHECK: encoding: [0x66,0x0f,0x4d,0xd0]
107 cmovgel %eax,%edx
108
109 // CHECK: cmovll %eax, %edx
110 // CHECK: encoding: [0x66,0x0f,0x4c,0xd0]
111 cmovll %eax,%edx
112
113 // CHECK: cmovlel %eax, %edx
114 // CHECK: encoding: [0x66,0x0f,0x4e,0xd0]
115 cmovlel %eax,%edx
116
117 // CHECK: cmovbel %eax, %edx
118 // CHECK: encoding: [0x66,0x0f,0x46,0xd0]
119 cmovnal %eax,%edx
120
121 // CHECK: cmovnel %eax, %edx
122 // CHECK: encoding: [0x66,0x0f,0x45,0xd0]
123 cmovnel %eax,%edx
124
125 // CHECK: cmovael %eax, %edx
126 // CHECK: encoding: [0x66,0x0f,0x43,0xd0]
127 cmovnbl %eax,%edx
128
129 // CHECK: cmoval %eax, %edx
130 // CHECK: encoding: [0x66,0x0f,0x47,0xd0]
131 cmovnbel %eax,%edx
132
133 // CHECK: cmovael %eax, %edx
134 // CHECK: encoding: [0x66,0x0f,0x43,0xd0]
135 cmovncl %eax,%edx
136
137 // CHECK: cmovnel %eax, %edx
138 // CHECK: encoding: [0x66,0x0f,0x45,0xd0]
139 cmovnel %eax,%edx
140
141 // CHECK: cmovlel %eax, %edx
142 // CHECK: encoding: [0x66,0x0f,0x4e,0xd0]
143 cmovngl %eax,%edx
144
145 // CHECK: cmovgel %eax, %edx
146 // CHECK: encoding: [0x66,0x0f,0x4d,0xd0]
147 cmovnl %eax,%edx
148
149 // CHECK: cmovnel %eax, %edx
150 // CHECK: encoding: [0x66,0x0f,0x45,0xd0]
151 cmovnel %eax,%edx
152
153 // CHECK: cmovlel %eax, %edx
154 // CHECK: encoding: [0x66,0x0f,0x4e,0xd0]
155 cmovngl %eax,%edx
156
157 // CHECK: cmovll %eax, %edx
158 // CHECK: encoding: [0x66,0x0f,0x4c,0xd0]
159 cmovngel %eax,%edx
160
161 // CHECK: cmovgel %eax, %edx
162 // CHECK: encoding: [0x66,0x0f,0x4d,0xd0]
163 cmovnll %eax,%edx
164
165 // CHECK: cmovgl %eax, %edx
166 // CHECK: encoding: [0x66,0x0f,0x4f,0xd0]
167 cmovnlel %eax,%edx
168
169 // CHECK: cmovnol %eax, %edx
170 // CHECK: encoding: [0x66,0x0f,0x41,0xd0]
171 cmovnol %eax,%edx
172
173 // CHECK: cmovnpl %eax, %edx
174 // CHECK: encoding: [0x66,0x0f,0x4b,0xd0]
175 cmovnpl %eax,%edx
176
177 // CHECK: cmovnsl %eax, %edx
178 // CHECK: encoding: [0x66,0x0f,0x49,0xd0]
179 cmovnsl %eax,%edx
180
181 // CHECK: cmovnel %eax, %edx
182 // CHECK: encoding: [0x66,0x0f,0x45,0xd0]
183 cmovnzl %eax,%edx
184
185 // CHECK: cmovol %eax, %edx
186 // CHECK: encoding: [0x66,0x0f,0x40,0xd0]
187 cmovol %eax,%edx
188
189 // CHECK: cmovpl %eax, %edx
190 // CHECK: encoding: [0x66,0x0f,0x4a,0xd0]
191 cmovpl %eax,%edx
192
193 // CHECK: cmovsl %eax, %edx
194 // CHECK: encoding: [0x66,0x0f,0x48,0xd0]
195 cmovsl %eax,%edx
196
197 // CHECK: cmovel %eax, %edx
198 // CHECK: encoding: [0x66,0x0f,0x44,0xd0]
199 cmovzl %eax,%edx
48200
49201 // CHECK: fmul %st(0)
50202 // CHECK: encoding: [0xd8,0xc8]
70222 // CHECK: encoding: [0xd8,0xf0]
71223 fdiv %st(0), %st
72224
225 // CHECK: movl %cs, %eax
226 // CHECK: encoding: [0x66,0x8c,0xc8]
227 movl %cs, %eax
228
73229 // CHECK: movw %cs, %ax
74230 // CHECK: encoding: [0x8c,0xc8]
75231 movw %cs, %ax
76232
233 // CHECK: movl %cs, (%eax)
234 // CHECK: encoding: [0x67,0x66,0x8c,0x08]
235 movl %cs, (%eax)
236
77237 // CHECK: movw %cs, (%eax)
78238 // CHECK: encoding: [0x67,0x8c,0x08]
79239 movw %cs, (%eax)
80240
241 // CHECK: movl %eax, %cs
242 // CHECK: encoding: [0x66,0x8e,0xc8]
243 movl %eax, %cs
244
245 // CHECK: movl (%eax), %cs
246 // CHECK: encoding: [0x67,0x66,0x8e,0x08]
247 movl (%eax), %cs
248
81249 // CHECK: movw (%eax), %cs
82250 // CHECK: encoding: [0x67,0x8e,0x08]
83251 movw (%eax), %cs
141309 // CHECK: wait
142310 // CHECK: encoding: [0x9b]
143311 fwait
312
313 // CHECK: pushal
314 // CHECK: encoding: [0x66,0x60]
315 pushal
316
317 // CHECK: popal
318 // CHECK: encoding: [0x66,0x61]
319 popal
320
321 // CHECK: jmpl *8(%eax)
322 // CHECK: encoding: [0x67,0x66,0xff,0x60,0x08]
323 jmpl *8(%eax)
324
325 // CHECK: lcalll $2, $4660
326 // CHECK: encoding: [0x66,0x9a,0x34,0x12,0x00,0x00,0x02,0x00]
327 lcalll $0x2, $0x1234
328
144329
145330 sysret
146331 // CHECK: sysretl
174359 // CHECK: pushw %gs
175360 // CHECK: encoding: [0x0f,0xa8]
176361
362 pushl %cs
363 // CHECK: pushl %cs
364 // CHECK: encoding: [0x66,0x0e]
365 pushl %ds
366 // CHECK: pushl %ds
367 // CHECK: encoding: [0x66,0x1e]
368 pushl %ss
369 // CHECK: pushl %ss
370 // CHECK: encoding: [0x66,0x16]
371 pushl %es
372 // CHECK: pushl %es
373 // CHECK: encoding: [0x66,0x06]
374 pushl %fs
375 // CHECK: pushl %fs
376 // CHECK: encoding: [0x66,0x0f,0xa0]
377 pushl %gs
378 // CHECK: pushl %gs
379 // CHECK: encoding: [0x66,0x0f,0xa8]
380
381 popl %ss
382 // CHECK: popl %ss
383 // CHECK: encoding: [0x66,0x17]
384 popl %ds
385 // CHECK: popl %ds
386 // CHECK: encoding: [0x66,0x1f]
387 popl %es
388 // CHECK: popl %es
389 // CHECK: encoding: [0x66,0x07]
390
177391 pushfd
178392 // CHECK: pushfl
179393 popfd
221435 // CHECK: incw %ax # encoding: [0x40]
222436 incw %ax
223437
438 // CHECK: incl %eax # encoding: [0x66,0x40]
439 incl %eax
440
224441 // CHECK: decb %al # encoding: [0xfe,0xc8]
225442 decb %al
226443
227444 // CHECK: decw %ax # encoding: [0x48]
228445 decw %ax
446
447 // CHECK: decl %eax # encoding: [0x66,0x48]
448 decl %eax
229449
230450 // CHECK: pshufw $14, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x0e]
231451 pshufw $14, %mm4, %mm0
276496 // CHECK: bound 2(%eax), %bx
277497 // CHECK: encoding: [0x67,0x62,0x58,0x02]
278498 bound 2(%eax),%bx
499
500 // CHECK: bound 4(%ebx), %ecx
501 // CHECK: encoding: [0x67,0x66,0x62,0x4b,0x04]
502 bound 4(%ebx),%ecx
279503
280504 // CHECK: arpl %bx, %bx
281505 // CHECK: encoding: [0x63,0xdb]
351575 outsw %ds:(%si), %dx
352576 outsw (%si), %dx
353577
578 // CHECK: outsl # encoding: [0x66,0x6f]
579 // CHECK: outsl
580 outsl
581 outsl %ds:(%si), %dx
582 outsl (%si), %dx
583
354584 // CHECK: insb # encoding: [0x6c]
355585 // CHECK: insb
356586 insb
360590 // CHECK: insw
361591 insw
362592 insw %dx, %es:(%di)
593
594 // CHECK: insl # encoding: [0x66,0x6d]
595 // CHECK: insl
596 insl
597 insl %dx, %es:(%di)
363598
364599 // CHECK: movsb # encoding: [0xa4]
365600 // CHECK: movsb
374609 movsw
375610 movsw %ds:(%si), %es:(%di)
376611 movsw (%si), %es:(%di)
612
613 // CHECK: movsl # encoding: [0x66,0xa5]
614 // CHECK: movsl
615 // CHECK: movsl
616 movsl
617 movsl %ds:(%si), %es:(%di)
618 movsl (%si), %es:(%di)
377619
378620 // CHECK: lodsb # encoding: [0xac]
379621 // CHECK: lodsb
397639 lods %ds:(%si), %ax
398640 lods (%si), %ax
399641
642 // CHECK: lodsl # encoding: [0x66,0xad]
643 // CHECK: lodsl
644 // CHECK: lodsl
645 // CHECK: lodsl
646 // CHECK: lodsl
647 lodsl
648 lodsl %ds:(%si), %eax
649 lodsl (%si), %eax
650 lods %ds:(%si), %eax
651 lods (%si), %eax
652
400653 // CHECK: stosb # encoding: [0xaa]
401654 // CHECK: stosb
402655 // CHECK: stosb
411664 stosw %ax, %es:(%di)
412665 stos %ax, %es:(%di)
413666
667 // CHECK: stosl # encoding: [0x66,0xab]
668 // CHECK: stosl
669 // CHECK: stosl
670 stosl
671 stosl %eax, %es:(%di)
672 stos %eax, %es:(%di)
673
414674 // CHECK: strw
415675 // CHECK: encoding: [0x0f,0x00,0xc8]
416676 str %ax
417677
678 // CHECK: strl
679 // CHECK: encoding: [0x66,0x0f,0x00,0xc8]
680 str %eax
681
682
418683 // CHECK: fsubp
419684 // CHECK: encoding: [0xde,0xe1]
420685 fsubp %st,%st(1)
423688 // CHECK: encoding: [0xde,0xe2]
424689 fsubp %st, %st(2)
425690
691 // CHECK: xchgl %eax, %eax
692 // CHECK: encoding: [0x66,0x90]
693 xchgl %eax, %eax
694
426695 // CHECK: xchgw %ax, %ax
427696 // CHECK: encoding: [0x90]
428697 xchgw %ax, %ax
698
699 // CHECK: xchgl %ecx, %eax
700 // CHECK: encoding: [0x66,0x91]
701 xchgl %ecx, %eax
702
703 // CHECK: xchgl %ecx, %eax
704 // CHECK: encoding: [0x66,0x91]
705 xchgl %eax, %ecx