llvm.org GIT mirror llvm / a44d688
Only enable LiveRangeShrink for x86. Summary: Moving LiveRangeShrink to x86 as this pass is mostly useful for archtectures with great register pressure. Reviewers: MatzeB, qcolombet Reviewed By: qcolombet Subscribers: jholewinski, jyknight, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33294 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303292 91177308-0d34-0410-b5e6-96231b3b80d8 Dehao Chen 3 years ago
6 changed file(s) with 8 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
622622 addPass(&LocalStackSlotAllocationID, false);
623623 }
624624
625 if (getOptLevel() != CodeGenOpt::None)
626 addPass(&LiveRangeShrinkID);
627
628625 // Run pre-ra passes.
629626 addPreRegAlloc();
630627
437437
438438 void X86PassConfig::addPreRegAlloc() {
439439 if (getOptLevel() != CodeGenOpt::None) {
440 addPass(&LiveRangeShrinkID);
440441 addPass(createX86FixupSetCC());
441442 addPass(createX86OptimizeLEAs());
442443 addPass(createX86CallFrameOptimization());
377377 ; CHECK-NEXT: cmp x0, #13
378378 ; CHECK-NOT: ccmp
379379 ; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
380 ; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
381380 ; CHECK-NEXT: cmp x2, #2
382381 ; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt
383382 ; CHECK-NEXT: cmp x2, #4
384383 ; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt
384 ; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
385385 ; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]
386386 ; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]
387387 ; CHECK-NEXT: cmp [[REG6]], #0
55 ; CHECK: .func foo
66 ; CHECK: ld.u32
77 ; CHECK-NEXT: ld.u32
8 ; CHECK-NEXT: add.s32
8 ; CHECK-NEXT: ld.u32
99 ; CHECK-NEXT: ld.u32
1010 ; CHECK-NEXT: add.s32
11 ; CHECK-NEXT: ld.u32
11 ; CHECK-NEXT: add.s32
1212 ; CHECK-NEXT: add.s32
1313 %ptr0 = getelementptr i32, i32* %a, i32 0
1414 %val0 = load i32, i32* %ptr0
33 ; CHECK: .func foo
44 ; CHECK: ld.v2.u32
55 ; CHECK-NEXT: ld.v2.u32
6 ; CHECK-NEXT: add.s32
7 ; CHECK-NEXT: add.s32
6 ; CHECK-NEXT: ld.v2.u32
87 ; CHECK-NEXT: ld.v2.u32
98 ; CHECK-NEXT: add.s32
109 ; CHECK-NEXT: add.s32
11 ; CHECK-NEXT: ld.v2.u32
10 ; CHECK-NEXT: add.s32
11 ; CHECK-NEXT: add.s32
1212 ; CHECK-NEXT: add.s32
1313 ; CHECK-NEXT: add.s32
1414 %ptr0 = getelementptr <2 x i32>, <2 x i32>* %a, i32 0
2727 ; LEON3_4_ITIN-LABEL: f32_ops:
2828 ; LEON3_4_ITIN: ld
2929 ; LEON3_4_ITIN-NEXT: ld
30 ; LEON3_4_ITIN-NEXT: ld
3031 ; LEON3_4_ITIN-NEXT: fadds
31 ; LEON3_4_ITIN-NEXT: ld
3232 ; LEON3_4_ITIN-NEXT: ld
3333 ; LEON3_4_ITIN-NEXT: fsubs
3434 ; LEON3_4_ITIN-NEXT: fmuls