llvm.org GIT mirror llvm / a44126f
Use 32-bit ebp for NaCl64 in a limited case: llvm.frameaddress. Summary: Follow up to [x32] "Use ebp/esp as frame and stack pointer": http://reviews.llvm.org/D4617 In that earlier patch, NaCl64 was made to always use rbp. That's needed for most cases because rbp should hold a full 64-bit address within the NaCl sandbox so that load/stores off of rbp don't require sandbox adjustment (zeroing the top 32-bits, then filling those by adding r15). However, llvm.frameaddress returns a pointer and pointers are 32-bit for NaCl64. In this case, use ebp instead, which will make the register copy type check. A similar mechanism may be needed for llvm.eh.return, but is not added in this change. Test Plan: test/CodeGen/X86/frameaddr.ll Reviewers: dschuff, nadav Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223510 91177308-0d34-0410-b5e6-96231b3b80d8 Jan Wen Voung 5 years ago
5 changed file(s) with 25 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
21422142 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
21432143 }
21442144
2145 // This needs to be set before we call getFrameRegister, otherwise we get
2146 // the wrong frame register.
2145 // This needs to be set before we call getPtrSizedFrameRegister, otherwise
2146 // we get the wrong frame register.
21472147 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
21482148 MFI->setFrameAddressIsTaken(true);
21492149
21502150 const X86RegisterInfo *RegInfo = static_cast(
21512151 TM.getSubtargetImpl()->getRegisterInfo());
2152 unsigned FrameReg = RegInfo->getFrameRegister(*(FuncInfo.MF));
2152 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*(FuncInfo.MF));
21532153 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
21542154 (FrameReg == X86::EBP && VT == MVT::i32)) &&
21552155 "Invalid Frame Register!");
1763517635 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
1763617636 const X86RegisterInfo *RegInfo = static_cast(
1763717637 DAG.getSubtarget().getRegisterInfo());
17638 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17638 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17639 DAG.getMachineFunction());
1763917640 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
1764017641 (FrameReg == X86::EBP && VT == MVT::i32)) &&
1764117642 "Invalid Frame Register!");
532532 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
533533 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
534534 return TFI->hasFP(MF) ? FramePtr : StackPtr;
535 }
536
537 unsigned X86RegisterInfo::getPtrSizedFrameRegister(
538 const MachineFunction &MF) const {
539 unsigned FrameReg = getFrameRegister(MF);
540 if (Subtarget.isTarget64BitILP32())
541 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
542 return FrameReg;
535543 }
536544
537545 namespace llvm {
121121
122122 // Debug information queries.
123123 unsigned getFrameRegister(const MachineFunction &MF) const override;
124 unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
124125 unsigned getStackRegister() const { return StackPtr; }
125126 unsigned getBaseRegister() const { return BasePtr; }
126127 // FIXME: Move to FrameInfok
33 ; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-64
44 ; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
55 ; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-X32ABI
6 ; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64
7 ; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-NACL64
68
79 define i8* @test1() nounwind {
810 entry:
2426 ; CHECK-X32ABI-NEXT: movl %ebp, %eax
2527 ; CHECK-X32ABI-NEXT: popq %rbp
2628 ; CHECK-X32ABI-NEXT: ret
29 ; CHECK-NACL64-LABEL: test1
30 ; CHECK-NACL64: pushq %rbp
31 ; CHECK-NACL64-NEXT: movq %rsp, %rbp
32 ; CHECK-NACL64-NEXT: movl %ebp, %eax
2733 %0 = tail call i8* @llvm.frameaddress(i32 0)
2834 ret i8* %0
2935 }
5157 ; CHECK-X32ABI-NEXT: movl (%eax), %eax
5258 ; CHECK-X32ABI-NEXT: popq %rbp
5359 ; CHECK-X32ABI-NEXT: ret
60 ; CHECK-NACL64-LABEL: test2
61 ; CHECK-NACL64: pushq %rbp
62 ; CHECK-NACL64-NEXT: movq %rsp, %rbp
63 ; CHECK-NACL64-NEXT: movl (%ebp), %eax
64 ; CHECK-NACL64-NEXT: movl (%eax), %eax
5465 %0 = tail call i8* @llvm.frameaddress(i32 2)
5566 ret i8* %0
5667 }