llvm.org GIT mirror llvm / a425991
Target: Remove unused patterns and transforms. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283515 91177308-0d34-0410-b5e6-96231b3b80d8 Peter Collingbourne 3 years ago
13 changed file(s) with 0 addition(s) and 203 deletion(s). Raw diff Collapse all Expand all
361361
362362 defm atomic_cmp_swap : AtomicCmpSwapLocal ;
363363
364 def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
365 (AMDGPUstore_mskor node:$val, node:$ptr), [{
366 return cast(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
367 }]>;
368
369364 class global_binary_atomic_op : PatFrag<
370365 (ops node:$ptr, node:$value),
371366 (atomic_op node:$ptr, node:$value),
384379 def atomic_xor_global : global_binary_atomic_op;
385380
386381 def atomic_cmp_swap_global : global_binary_atomic_op;
387 def atomic_cmp_swap_global_nortn : PatFrag<
388 (ops node:$ptr, node:$value),
389 (atomic_cmp_swap_global node:$ptr, node:$value),
390 [{ return SDValue(N, 0).use_empty(); }]
391 >;
392382
393383 //===----------------------------------------------------------------------===//
394384 // Misc Pattern Fragments
602592
603593 def select_oneuse : HasOneUseTernaryOp
604594
605 // 24-bit arithmetic patterns
606 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
607
608595 // Special conversion patterns
609596
610597 def cvt_rpi_i32_f32 : PatFrag <
697697 //===----------------------------------------------------------------------===//
698698 // MUBUF Patterns
699699 //===----------------------------------------------------------------------===//
700
701 def mubuf_vaddr_offset : PatFrag<
702 (ops node:$ptr, node:$offset, node:$imm_offset),
703 (add (add node:$ptr, node:$offset), node:$imm_offset)
704 >;
705
706700
707701 let Predicates = [isGCN] in {
708702
238238 (imm),
239239 [{uint32_t TType = (uint32_t)N->getZExtValue();
240240 return TType == 11 || TType == 12 || TType == 17;
241 }]
242 >;
243
244 def TEX_MSAA : PatLeaf<
245 (imm),
246 [{uint32_t TType = (uint32_t)N->getZExtValue();
247 return TType == 14;
248 }]
249 >;
250
251 def TEX_ARRAY_MSAA : PatLeaf<
252 (imm),
253 [{uint32_t TType = (uint32_t)N->getZExtValue();
254 return TType == 15;
255241 }]
256242 >;
257243
145145 return isShiftedInt<29,3>(v);
146146 }]>;
147147
148 def s16ImmPred : PatLeaf<(i32 imm), [{
149 int64_t v = (int64_t)N->getSExtValue();
150 return isInt<16>(v);
151 }]>;
152
153 def s11_0ImmPred : PatLeaf<(i32 imm), [{
154 int64_t v = (int64_t)N->getSExtValue();
155 return isInt<11>(v);
156 }]>;
157
158 def s11_1ImmPred : PatLeaf<(i32 imm), [{
159 int64_t v = (int64_t)N->getSExtValue();
160 return isShiftedInt<11,1>(v);
161 }]>;
162
163 def s11_2ImmPred : PatLeaf<(i32 imm), [{
164 int64_t v = (int64_t)N->getSExtValue();
165 return isShiftedInt<11,2>(v);
166 }]>;
167
168 def s11_3ImmPred : PatLeaf<(i32 imm), [{
169 int64_t v = (int64_t)N->getSExtValue();
170 return isShiftedInt<11,3>(v);
171 }]>;
172
173148 def s10ImmPred : PatLeaf<(i32 imm), [{
174149 int64_t v = (int64_t)N->getSExtValue();
175150 return isInt<10>(v);
210185 return isShiftedInt<4,3>(v);
211186 }]>;
212187
213 def u64ImmPred : PatLeaf<(i64 imm), [{
214 // Adding "N ||" to suppress gcc unused warning.
215 return (N || true);
216 }]>;
217
218188 def u32ImmPred : PatLeaf<(i32 imm), [{
219189 int64_t v = (int64_t)N->getSExtValue();
220190 return isUInt<32>(v);
221191 }]>;
222192
223 def u32_0ImmPred : PatLeaf<(i32 imm), [{
224 int64_t v = (int64_t)N->getSExtValue();
225 return isUInt<32>(v);
226 }]>;
227
228 def u31_1ImmPred : PatLeaf<(i32 imm), [{
229 int64_t v = (int64_t)N->getSExtValue();
230 return isShiftedUInt<31,1>(v);
231 }]>;
232
233 def u30_2ImmPred : PatLeaf<(i32 imm), [{
234 int64_t v = (int64_t)N->getSExtValue();
235 return isShiftedUInt<30,2>(v);
236 }]>;
237
238 def u29_3ImmPred : PatLeaf<(i32 imm), [{
239 int64_t v = (int64_t)N->getSExtValue();
240 return isShiftedUInt<29,3>(v);
241 }]>;
242
243 def u26_6ImmPred : PatLeaf<(i32 imm), [{
244 int64_t v = (int64_t)N->getSExtValue();
245 return isShiftedUInt<26,6>(v);
246 }]>;
247
248193 def u16_0ImmPred : PatLeaf<(i32 imm), [{
249194 int64_t v = (int64_t)N->getSExtValue();
250195 return isUInt<16>(v);
251196 }]>;
252197
253 def u16_1ImmPred : PatLeaf<(i32 imm), [{
254 int64_t v = (int64_t)N->getSExtValue();
255 return isShiftedUInt<16,1>(v);
256 }]>;
257
258 def u16_2ImmPred : PatLeaf<(i32 imm), [{
259 int64_t v = (int64_t)N->getSExtValue();
260 return isShiftedUInt<16,2>(v);
261 }]>;
262
263198 def u11_3ImmPred : PatLeaf<(i32 imm), [{
264199 int64_t v = (int64_t)N->getSExtValue();
265200 return isShiftedUInt<11,3>(v);
266 }]>;
267
268 def u10ImmPred : PatLeaf<(i32 imm), [{
269 int64_t v = (int64_t)N->getSExtValue();
270 return isUInt<10>(v);
271201 }]>;
272202
273203 def u9ImmPred : PatLeaf<(i32 imm), [{
286216 return isUInt<7>(Imm) && Imm > 0;
287217 }]>;
288218
289 def u7ImmPred : PatLeaf<(i32 imm), [{
290 int64_t v = (int64_t)N->getSExtValue();
291 return isUInt<7>(v);
292 }]>;
293
294219 def u6ImmPred : PatLeaf<(i32 imm), [{
295220 int64_t v = (int64_t)N->getSExtValue();
296221 return isUInt<6>(v);
311236 return isShiftedUInt<6,2>(v);
312237 }]>;
313238
314 def u6_3ImmPred : PatLeaf<(i32 imm), [{
315 int64_t v = (int64_t)N->getSExtValue();
316 return isShiftedUInt<6,3>(v);
317 }]>;
318
319239 def u5ImmPred : PatLeaf<(i32 imm), [{
320240 int64_t v = (int64_t)N->getSExtValue();
321241 return isUInt<5>(v);
334254 def u2ImmPred : PatLeaf<(i32 imm), [{
335255 int64_t v = (int64_t)N->getSExtValue();
336256 return isUInt<2>(v);
337 }]>;
338
339 def u1ImmPred : PatLeaf<(i1 imm), [{
340 int64_t v = (int64_t)N->getSExtValue();
341 return isUInt<1>(v);
342 }]>;
343
344 def u1ImmPred32 : PatLeaf<(i32 imm), [{
345 int64_t v = (int64_t)N->getSExtValue();
346 return isUInt<1>(v);
347257 }]>;
348258
349259 def m5ImmPred : PatLeaf<(i32 imm), [{
459369 return false;
460370 }]>;
461371
462 def s3_7ImmPred : PatLeaf<(i32 imm), [{
463 int64_t v = (int64_t)N->getSExtValue();
464 if (HST->hasV60TOps())
465 // Return true if the immediate can fit in a 9-bit sign extended field and
466 // is 128-byte aligned.
467 return isShiftedInt<3,7>(v);
468 return false;
469 }]>;
470
471372 def s4_6ImmPred : PatLeaf<(i32 imm), [{
472373 int64_t v = (int64_t)N->getSExtValue();
473374 if (HST->hasV60TOps())
474375 // Return true if the immediate can fit in a 10-bit sign extended field and
475376 // is 64-byte aligned.
476377 return isShiftedInt<4,6>(v);
477 return false;
478 }]>;
479
480 def s3_6ImmPred : PatLeaf<(i32 imm), [{
481 int64_t v = (int64_t)N->getSExtValue();
482 if (HST->hasV60TOps())
483 // Return true if the immediate can fit in a 9-bit sign extended field and
484 // is 64-byte aligned.
485 return isShiftedInt<3,6>(v);
486378 return false;
487379 }]>;
488380
114114 let ParserMatchClass = Imm10AsmOperand;
115115 }
116116
117 def immZExt21 : PatLeaf<(imm),
118 [{return isUInt<21>(N->getZExtValue()); }], LO21>;
119
120117 def LoImm16AsmOperand : AsmOperandClass { let Name = "LoImm16"; }
121118 def i32lo16z : Operand, PatLeaf<(i32 imm), [{
122119 // i32lo16 predicate - true if the 32-bit immediate has only rightmost 16
1313 //===----------------------------------------------------------------------===//
1414 // Mips Operand, Complex Patterns and Transformations Definitions.
1515 //===----------------------------------------------------------------------===//
16
17 // Transformation Function - get Imm - 32.
18 def Subtract32 : SDNodeXForm
19 return getImm(N, (unsigned)N->getZExtValue() - 32);
20 }]>;
2116
2217 // shamt must fit in 6 bits.
2318 def immZExt6 : ImmLeaf;
10801080 // e.g. addi, andi
10811081 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
10821082
1083 // Node immediate fits as 15-bit sign extended on target immediate.
1084 // e.g. addi, andi
1085 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
1086
10871083 // Node immediate fits as 7-bit zero extended on target immediate.
10881084 def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;
10891085
387387
388388 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
389389 (fmul node:$ws, (fexp2 node:$wt))>;
390
391 // Immediates
392 def immSExt5 : ImmLeaf(Imm);}]>;
393 def immSExt10: ImmLeaf(Imm);}]>;
394390
395391 // Instruction encoding.
396392 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
7070 def CmpLE : PatLeaf<(i32 3)>;
7171 def CmpGT : PatLeaf<(i32 4)>;
7272 def CmpGE : PatLeaf<(i32 5)>;
73 def CmpLO : PatLeaf<(i32 6)>;
74 def CmpLS : PatLeaf<(i32 7)>;
75 def CmpHI : PatLeaf<(i32 8)>;
76 def CmpHS : PatLeaf<(i32 9)>;
7773 def CmpEQU : PatLeaf<(i32 10)>;
7874 def CmpNEU : PatLeaf<(i32 11)>;
7975 def CmpLTU : PatLeaf<(i32 12)>;
8985 def CmpLE_FTZ : PatLeaf<(i32 0x103)>;
9086 def CmpGT_FTZ : PatLeaf<(i32 0x104)>;
9187 def CmpGE_FTZ : PatLeaf<(i32 0x105)>;
92 def CmpLO_FTZ : PatLeaf<(i32 0x106)>;
93 def CmpLS_FTZ : PatLeaf<(i32 0x107)>;
94 def CmpHI_FTZ : PatLeaf<(i32 0x108)>;
95 def CmpHS_FTZ : PatLeaf<(i32 0x109)>;
9688 def CmpEQU_FTZ : PatLeaf<(i32 0x10A)>;
9789 def CmpNEU_FTZ : PatLeaf<(i32 0x10B)>;
9890 def CmpLTU_FTZ : PatLeaf<(i32 0x10C)>;
10597 def CmpMode : Operand {
10698 let PrintMethod = "printCmpMode";
10799 }
108
109 def F32ConstZero : Operand, PatLeaf<(f32 fpimm)>, SDNodeXForm
110 return CurDAG->getTargetConstantFP(0.0, MVT::f32);
111 }]>;
112 def F32ConstOne : Operand, PatLeaf<(f32 fpimm)>, SDNodeXForm
113 return CurDAG->getTargetConstantFP(1.0, MVT::f32);
114 }]>;
115100
116101 //===----------------------------------------------------------------------===//
117102 // NVPTX Instruction Predicate Definitions
6262 // Transformation function: 64 - imm
6363 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N))
6464 : getI32Imm(0, SDLoc(N));
65 }]>;
66
67 def HI32_48 : SDNodeXForm
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N)));
70 }]>;
71
72 def HI48_64 : SDNodeXForm
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N)));
7565 }]>;
7666
7767
386386 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
387387 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
388388
389 // Match extensions of an i32 to an i64, followed by an AND of the low
390 // i8 or i16 part.
391 def zext8dbl : PatFrag<(ops node:$src), (zext8 (anyext node:$src))>;
392 def zext16dbl : PatFrag<(ops node:$src), (zext16 (anyext node:$src))>;
393
394 // Typed floating-point loads.
395 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
396 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
397
398389 // Extending loads in which the extension type can be signed.
399390 def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
400391 unsigned Type = cast(N)->getExtensionType();
2828 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
2929 def load_mvmmx : PatFrag<(ops node:$ptr),
3030 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
31 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
3231
3332 //===----------------------------------------------------------------------===//
3433 // SSE specific DAG Nodes.
703702 || cast(N)->getAlignment() >= 16;
704703 }]>;
705704
706 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
707 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
708
709705 // 128-bit memop pattern fragments
710706 // NOTE: all 128-bit integer vector loads are promoted to v2i64
711707 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
145145 return (uint32_t)N->getZExtValue() < (1 << 6);
146146 }]>;
147147
148 def immU10 : PatLeaf<(imm), [{
149 return (uint32_t)N->getZExtValue() < (1 << 10);
150 }]>;
151
152148 def immU16 : PatLeaf<(imm), [{
153149 return (uint32_t)N->getZExtValue() < (1 << 16);
154 }]>;
155
156 def immU20 : PatLeaf<(imm), [{
157 return (uint32_t)N->getZExtValue() < (1 << 20);
158150 }]>;
159151
160152 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;