llvm.org GIT mirror llvm / a3af6bb
GlobalISel: Remove unsigned variant of SrcOp Force using Register. One downside is the generated register enums require explicit conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364194 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 1 year, 1 month ago
28 changed file(s) with 479 addition(s) and 478 deletion(s). Raw diff Collapse all Expand all
144144
145145 bool needsCustom() const { return isCustom; }
146146
147 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
147 Register getLocReg() const { assert(isRegLoc()); return Loc; }
148148 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
149149 unsigned getExtraInfo() const { return Loc; }
150150 MVT getLocVT() const { return LocVT; }
4141 virtual void anchor();
4242 public:
4343 struct ArgInfo {
44 unsigned Reg;
44 Register Reg;
4545 Type *Ty;
4646 ISD::ArgFlagsTy Flags;
4747 bool IsFixed;
7676 /// direct SP manipulation, depending on the context. \p MPO
7777 /// should be initialized to an appropriate description of the
7878 /// address created.
79 virtual unsigned getStackAddress(uint64_t Size, int64_t Offset,
79 virtual Register getStackAddress(uint64_t Size, int64_t Offset,
8080 MachinePointerInfo &MPO) = 0;
8181
8282 /// The specified value has been assigned to a physical register,
8383 /// handle the appropriate COPY (either to or from) and mark any
8484 /// relevant uses/defines as needed.
85 virtual void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
85 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
8686 CCValAssign &VA) = 0;
8787
8888 /// The specified value has been assigned to a stack
8989 /// location. Load or store it there, with appropriate extension
9090 /// if necessary.
91 virtual void assignValueToAddress(unsigned ValVReg, unsigned Addr,
91 virtual void assignValueToAddress(Register ValVReg, Register Addr,
9292 uint64_t Size, MachinePointerInfo &MPO,
9393 CCValAssign &VA) = 0;
9494
103103 llvm_unreachable("Custom values not supported");
104104 }
105105
106 unsigned extendRegister(unsigned ValReg, CCValAssign &VA);
106 Register extendRegister(Register ValReg, CCValAssign &VA);
107107
108108 virtual bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
109109 CCValAssign::LocInfo LocInfo, const ArgInfo &Info,
1717 #define LLVM_CODEGEN_GLOBALISEL_COMBINER_HELPER_H
1818
1919 #include "llvm/CodeGen/LowLevelType.h"
20 #include "llvm/CodeGen/Register.h"
2021
2122 namespace llvm {
2223
4142 CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B);
4243
4344 /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
44 void replaceRegWith(MachineRegisterInfo &MRI, unsigned FromReg, unsigned ToReg) const;
45 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
4546
4647 /// Replace a single register operand with a new register and inform the
4748 /// observer of the changes.
4849 void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp,
49 unsigned ToReg) const;
50 Register ToReg) const;
5051
5152 /// If \p MI is COPY, try to combine it.
5253 /// Returns true if MI changed.
199199 /// the function.
200200 ///
201201 /// \return true if the materialization succeeded.
202 bool translate(const Constant &C, unsigned Reg);
202 bool translate(const Constant &C, Register Reg);
203203
204204 /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
205205 /// emitted.
215215 bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
216216 unsigned ID);
217217
218 void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
218 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
219219
220220 bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
221221 MachineIRBuilder &MIRBuilder);
240240 // until it is refactored.
241241 /// Combines all component registers of \p V into a single scalar with size
242242 /// "max(Offsets) + last size".
243 unsigned packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
244
245 void unpackRegs(const Value &V, unsigned Src, MachineIRBuilder &MIRBuilder);
243 Register packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
244
245 void unpackRegs(const Value &V, Register Src, MachineIRBuilder &MIRBuilder);
246246
247247 /// Returns true if the value should be split into multiple LLTs.
248248 /// If \p Offsets is given then the split type's offsets will be stored in it.
125125
126126 public:
127127 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
128 SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129128 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
130129 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
131130 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
157156 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
158157 }
159158
160 unsigned getReg() const {
159 Register getReg() const {
161160 switch (Ty) {
162161 case SrcType::Ty_Predicate:
163162 llvm_unreachable("Not a register operand");
8181 /// Get the register for the operand index.
8282 /// The operand at the index should be a register (asserted by
8383 /// MachineOperand).
84 unsigned getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
84 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
8585
8686 /// Add a new virtual register operand.
8787 const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
7676
7777 /// Get or create the swifterror value virtual register in
7878 /// VRegDefMap for this basic block.
79 unsigned getOrCreateVReg(const MachineBasicBlock *, const Value *);
79 Register getOrCreateVReg(const MachineBasicBlock *, const Value *);
8080
8181 /// Set the swifterror virtual register in the VRegDefMap for this
8282 /// basic block.
8484
8585 /// Get or create the swifterror value virtual register for a def of a
8686 /// swifterror by an instruction.
87 unsigned getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *,
87 Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *,
8888 const Value *);
8989
9090 /// Get or create the swifterror value virtual register for a use of a
9191 /// swifterror by an instruction.
92 unsigned getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *,
92 Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *,
9393 const Value *);
9494
9595 /// Create initial definitions of swifterror values in the entry block of the
194194 return true;
195195 }
196196
197 unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg,
197 Register CallLowering::ValueHandler::extendRegister(Register ValReg,
198198 CCValAssign &VA) {
199199 LLT LocTy{VA.getLocVT()};
200200 if (LocTy.getSizeInBits() == MRI.getType(ValReg).getSizeInBits())
2121 MachineIRBuilder &B)
2222 : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer) {}
2323
24 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, unsigned FromReg,
25 unsigned ToReg) const {
24 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
25 Register ToReg) const {
2626 Observer.changingAllUsesOfReg(MRI, FromReg);
2727
2828 if (MRI.constrainRegAttrs(ToReg, FromReg))
3535
3636 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI,
3737 MachineOperand &FromRegOp,
38 unsigned ToReg) const {
38 Register ToReg) const {
3939 assert(FromRegOp.getParent() && "Expected an operand in an MI");
4040 Observer.changingInstr(*FromRegOp.getParent());
4141
234234 void CombinerHelper::applyCombineExtendingLoads(MachineInstr &MI,
235235 PreferredTuple &Preferred) {
236236 // Rewrite the load to the chosen extending load.
237 unsigned ChosenDstReg = Preferred.MI->getOperand(0).getReg();
237 Register ChosenDstReg = Preferred.MI->getOperand(0).getReg();
238238
239239 // Inserter to insert a truncate back to the original type at a given point
240240 // with some basic CSE to limit truncate duplication to one per BB.
251251 }
252252
253253 Builder.setInsertPt(*InsertIntoBB, InsertBefore);
254 unsigned NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
254 Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
255255 MachineInstr *NewMI = Builder.buildTrunc(NewDstReg, ChosenDstReg);
256256 EmittedInsns[InsertIntoBB] = NewMI;
257257 replaceRegOpWith(MRI, UseMO, NewDstReg);
288288 // Unless the value is a Constant => loadimm cst?
289289 // or inline constant each time?
290290 // Creation of a virtual register needs to have a size.
291 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
292 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
293 unsigned Res = getOrCreateVReg(U);
291 Register Op0 = getOrCreateVReg(*U.getOperand(0));
292 Register Op1 = getOrCreateVReg(*U.getOperand(1));
293 Register Res = getOrCreateVReg(U);
294294 uint16_t Flags = 0;
295295 if (isa(U)) {
296296 const Instruction &I = cast(U);
305305 // -0.0 - X --> G_FNEG
306306 if (isa(U.getOperand(0)) &&
307307 U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
308 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
309 unsigned Res = getOrCreateVReg(U);
308 Register Op1 = getOrCreateVReg(*U.getOperand(1));
309 Register Res = getOrCreateVReg(U);
310310 uint16_t Flags = 0;
311311 if (isa(U)) {
312312 const Instruction &I = cast(U);
320320 }
321321
322322 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
323 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
324 unsigned Res = getOrCreateVReg(U);
323 Register Op0 = getOrCreateVReg(*U.getOperand(0));
324 Register Res = getOrCreateVReg(U);
325325 uint16_t Flags = 0;
326326 if (isa(U)) {
327327 const Instruction &I = cast(U);
334334 bool IRTranslator::translateCompare(const User &U,
335335 MachineIRBuilder &MIRBuilder) {
336336 const CmpInst *CI = dyn_cast(&U);
337 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
338 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
339 unsigned Res = getOrCreateVReg(U);
337 Register Op0 = getOrCreateVReg(*U.getOperand(0));
338 Register Op1 = getOrCreateVReg(*U.getOperand(1));
339 Register Res = getOrCreateVReg(U);
340340 CmpInst::Predicate Pred =
341341 CI ? CI->getPredicate() : static_cast(
342342 cast(U).getPredicate());
383383 unsigned Succ = 0;
384384 if (!BrInst.isUnconditional()) {
385385 // We want a G_BRCOND to the true BB followed by an unconditional branch.
386 unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
386 Register Tst = getOrCreateVReg(*BrInst.getCondition());
387387 const BasicBlock &TrueTgt = *cast(BrInst.getSuccessor(Succ++));
388388 MachineBasicBlock &TrueBB = getMBB(TrueTgt);
389389 MIRBuilder.buildBrCond(Tst, TrueBB);
525525 const Value &SValue = *JTH.SValue;
526526 // Subtract the lowest switch case value from the value being switched on.
527527 const LLT SwitchTy = getLLTForType(*SValue.getType(), *DL);
528 unsigned SwitchOpReg = getOrCreateVReg(SValue);
528 Register SwitchOpReg = getOrCreateVReg(SValue);
529529 auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First);
530530 auto Sub = MIB.buildSub({SwitchTy}, SwitchOpReg, FirstCst);
531531
562562 void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
563563 MachineBasicBlock *SwitchBB,
564564 MachineIRBuilder &MIB) {
565 unsigned CondLHS = getOrCreateVReg(*CB.CmpLHS);
566 unsigned Cond = 0;
565 Register CondLHS = getOrCreateVReg(*CB.CmpLHS);
566 Register Cond;
567567 DebugLoc OldDbgLoc = MIB.getDebugLoc();
568568 MIB.setDebugLoc(CB.DbgLoc);
569569 MIB.setMBB(*CB.ThisBB);
583583 const LLT i1Ty = LLT::scalar(1);
584584 // Build the compare.
585585 if (!CB.CmpMHS) {
586 unsigned CondRHS = getOrCreateVReg(*CB.CmpRHS);
586 Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
587587 Cond = MIB.buildICmp(CB.PredInfo.Pred, i1Ty, CondLHS, CondRHS).getReg(0);
588588 } else {
589589 assert(CB.PredInfo.Pred == CmpInst::ICMP_ULE &&
592592 const APInt& Low = cast(CB.CmpLHS)->getValue();
593593 const APInt& High = cast(CB.CmpRHS)->getValue();
594594
595 unsigned CmpOpReg = getOrCreateVReg(*CB.CmpMHS);
595 Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS);
596596 if (cast(CB.CmpLHS)->isMinValue(true)) {
597 unsigned CondRHS = getOrCreateVReg(*CB.CmpRHS);
597 Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
598598 Cond =
599599 MIB.buildICmp(CmpInst::ICMP_ULE, i1Ty, CmpOpReg, CondRHS).getReg(0);
600600 } else {
828828 MachineIRBuilder &MIRBuilder) {
829829 const IndirectBrInst &BrInst = cast(U);
830830
831 const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
831 const Register Tgt = getOrCreateVReg(*BrInst.getAddress());
832832 MIRBuilder.buildBrIndirect(Tgt);
833833
834834 // Link successors.
859859
860860 ArrayRef Regs = getOrCreateVRegs(LI);
861861 ArrayRef Offsets = *VMap.getOffsets(LI);
862 unsigned Base = getOrCreateVReg(*LI.getPointerOperand());
862 Register Base = getOrCreateVReg(*LI.getPointerOperand());
863863
864864 Type *OffsetIRTy = DL->getIntPtrType(LI.getPointerOperandType());
865865 LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
866866
867867 if (CLI->supportSwiftError() && isSwiftError(LI.getPointerOperand())) {
868868 assert(Regs.size() == 1 && "swifterror should be single pointer");
869 unsigned VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(),
869 Register VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(),
870870 LI.getPointerOperand());
871871 MIRBuilder.buildCopy(Regs[0], VReg);
872872 return true;
900900
901901 ArrayRef Vals = getOrCreateVRegs(*SI.getValueOperand());
902902 ArrayRef Offsets = *VMap.getOffsets(*SI.getValueOperand());
903 unsigned Base = getOrCreateVReg(*SI.getPointerOperand());
903 Register Base = getOrCreateVReg(*SI.getPointerOperand());
904904
905905 Type *OffsetIRTy = DL->getIntPtrType(SI.getPointerOperandType());
906906 LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
908908 if (CLI->supportSwiftError() && isSwiftError(SI.getPointerOperand())) {
909909 assert(Vals.size() == 1 && "swifterror should be single pointer");
910910
911 unsigned VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
911 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
912912 SI.getPointerOperand());
913913 MIRBuilder.buildCopy(VReg, Vals[0]);
914914 return true;
990990
991991 bool IRTranslator::translateSelect(const User &U,
992992 MachineIRBuilder &MIRBuilder) {
993 unsigned Tst = getOrCreateVReg(*U.getOperand(0));
993 Register Tst = getOrCreateVReg(*U.getOperand(0));
994994 ArrayRef ResRegs = getOrCreateVRegs(U);
995995 ArrayRef Op0Regs = getOrCreateVRegs(*U.getOperand(1));
996996 ArrayRef Op1Regs = getOrCreateVRegs(*U.getOperand(2));
10131013 // If we're bitcasting to the source type, we can reuse the source vreg.
10141014 if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
10151015 getLLTForType(*U.getType(), *DL)) {
1016 unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
1016 Register SrcReg = getOrCreateVReg(*U.getOperand(0));
10171017 auto &Regs = *VMap.getVRegs(U);
10181018 // If we already assigned a vreg for this bitcast, we can't change that.
10191019 // Emit a copy to satisfy the users we already emitted.
10301030
10311031 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
10321032 MachineIRBuilder &MIRBuilder) {
1033 unsigned Op = getOrCreateVReg(*U.getOperand(0));
1034 unsigned Res = getOrCreateVReg(U);
1033 Register Op = getOrCreateVReg(*U.getOperand(0));
1034 Register Res = getOrCreateVReg(U);
10351035 MIRBuilder.buildInstr(Opcode, {Res}, {Op});
10361036 return true;
10371037 }
10431043 return false;
10441044
10451045 Value &Op0 = *U.getOperand(0);
1046 unsigned BaseReg = getOrCreateVReg(Op0);
1046 Register BaseReg = getOrCreateVReg(Op0);
10471047 Type *PtrIRTy = Op0.getType();
10481048 LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
10491049 Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
10681068 }
10691069
10701070 if (Offset != 0) {
1071 unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
1071 Register NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
10721072 LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
10731073 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
10741074 MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetMIB.getReg(0));
10771077 Offset = 0;
10781078 }
10791079
1080 unsigned IdxReg = getOrCreateVReg(*Idx);
1080 Register IdxReg = getOrCreateVReg(*Idx);
10811081 if (MRI->getType(IdxReg) != OffsetTy) {
1082 unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
1082 Register NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
10831083 MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
10841084 IdxReg = NewIdxReg;
10851085 }
10861086
10871087 // N = N + Idx * ElementSize;
10881088 // Avoid doing it for ElementSize of 1.
1089 unsigned GepOffsetReg;
1089 Register GepOffsetReg;
10901090 if (ElementSize != 1) {
10911091 GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
10921092 auto ElementSizeMIB = MIRBuilder.buildConstant(
10951095 } else
10961096 GepOffsetReg = IdxReg;
10971097
1098 unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
1098 Register NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
10991099 MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
11001100 BaseReg = NewBaseReg;
11011101 }
11621162 CallLowering::ArgInfo(0, CI.getType()), Args);
11631163 }
11641164
1165 void IRTranslator::getStackGuard(unsigned DstReg,
1165 void IRTranslator::getStackGuard(Register DstReg,
11661166 MachineIRBuilder &MIRBuilder) {
11671167 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
11681168 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
13721372 } else if (const auto *CI = dyn_cast(V)) {
13731373 MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
13741374 } else {
1375 unsigned Reg = getOrCreateVReg(*V);
1375 Register Reg = getOrCreateVReg(*V);
13761376 // FIXME: This does not handle register-indirect values at offset 0. The
13771377 // direct/indirect thing shouldn't really be handled by something as
13781378 // implicit as reg+noreg vs reg+imm in the first palce, but it seems
13961396 case Intrinsic::fmuladd: {
13971397 const TargetMachine &TM = MF->getTarget();
13981398 const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1399 unsigned Dst = getOrCreateVReg(CI);
1400 unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
1401 unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
1402 unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
1399 Register Dst = getOrCreateVReg(CI);
1400 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0));
1401 Register Op1 = getOrCreateVReg(*CI.getArgOperand(1));
1402 Register Op2 = getOrCreateVReg(*CI.getArgOperand(2));
14031403 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
14041404 TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
14051405 // TODO: Revisit this to see if we should move this part of the
14211421 return translateMemfunc(CI, MIRBuilder, ID);
14221422 case Intrinsic::eh_typeid_for: {
14231423 GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
1424 unsigned Reg = getOrCreateVReg(CI);
1424 Register Reg = getOrCreateVReg(CI);
14251425 unsigned TypeID = MF->getTypeIDFor(GV);
14261426 MIRBuilder.buildConstant(Reg, TypeID);
14271427 return true;
14431443 return true;
14441444 case Intrinsic::stackprotector: {
14451445 LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1446 unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
1446 Register GuardVal = MRI->createGenericVirtualRegister(PtrTy);
14471447 getStackGuard(GuardVal, MIRBuilder);
14481448
14491449 AllocaInst *Slot = cast(CI.getArgOperand(1));
14601460 }
14611461 case Intrinsic::stacksave: {
14621462 // Save the stack pointer to the location provided by the intrinsic.
1463 unsigned Reg = getOrCreateVReg(CI);
1464 unsigned StackPtr = MF->getSubtarget()
1463 Register Reg = getOrCreateVReg(CI);
1464 Register StackPtr = MF->getSubtarget()
14651465 .getTargetLowering()
14661466 ->getStackPointerRegisterToSaveRestore();
14671467
14741474 }
14751475 case Intrinsic::stackrestore: {
14761476 // Restore the stack pointer from the location provided by the intrinsic.
1477 unsigned Reg = getOrCreateVReg(*CI.getArgOperand(0));
1478 unsigned StackPtr = MF->getSubtarget()
1477 Register Reg = getOrCreateVReg(*CI.getArgOperand(0));
1478 Register StackPtr = MF->getSubtarget()
14791479 .getTargetLowering()
14801480 ->getStackPointerRegisterToSaveRestore();
14811481
15021502 }
15031503 case Intrinsic::invariant_start: {
15041504 LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1505 unsigned Undef = MRI->createGenericVirtualRegister(PtrTy);
1505 Register Undef = MRI->createGenericVirtualRegister(PtrTy);
15061506 MIRBuilder.buildUndef(Undef);
15071507 return true;
15081508 }
15361536 return true;
15371537 }
15381538
1539 unsigned IRTranslator::packRegs(const Value &V,
1539 Register IRTranslator::packRegs(const Value &V,
15401540 MachineIRBuilder &MIRBuilder) {
15411541 ArrayRef Regs = getOrCreateVRegs(V);
15421542 ArrayRef Offsets = *VMap.getOffsets(V);
15451545 if (Regs.size() == 1)
15461546 return Regs[0];
15471547
1548 unsigned Dst = MRI->createGenericVirtualRegister(BigTy);
1548 Register Dst = MRI->createGenericVirtualRegister(BigTy);
15491549 MIRBuilder.buildUndef(Dst);
15501550 for (unsigned i = 0; i < Regs.size(); ++i) {
1551 unsigned NewDst = MRI->createGenericVirtualRegister(BigTy);
1551 Register NewDst = MRI->createGenericVirtualRegister(BigTy);
15521552 MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
15531553 Dst = NewDst;
15541554 }
15551555 return Dst;
15561556 }
15571557
1558 void IRTranslator::unpackRegs(const Value &V, unsigned Src,
1558 void IRTranslator::unpackRegs(const Value &V, Register Src,
15591559 MachineIRBuilder &MIRBuilder) {
15601560 ArrayRef Regs = getOrCreateVRegs(V);
15611561 ArrayRef Offsets = *VMap.getOffsets(V);
15941594 for (auto &Arg: CI.arg_operands()) {
15951595 if (CLI->supportSwiftError() && isSwiftError(Arg)) {
15961596 LLT Ty = getLLTForType(*Arg->getType(), *DL);
1597 unsigned InVReg = MRI->createGenericVirtualRegister(Ty);
1597 Register InVReg = MRI->createGenericVirtualRegister(Ty);
15981598 MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(
15991599 &CI, &MIRBuilder.getMBB(), Arg));
16001600 Args.push_back(InVReg);
16861686 MCSymbol *BeginSymbol = Context.createTempSymbol();
16871687 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
16881688
1689 unsigned Res = 0;
1689 Register Res;
16901690 if (!I.getType()->isVoidTy())
16911691 Res = MRI->createGenericVirtualRegister(getLLTForType(*I.getType(), *DL));
16921692 SmallVector Args;
16941694 for (auto &Arg : I.arg_operands()) {
16951695 if (CLI->supportSwiftError() && isSwiftError(Arg)) {
16961696 LLT Ty = getLLTForType(*Arg->getType(), *DL);
1697 unsigned InVReg = MRI->createGenericVirtualRegister(Ty);
1697 Register InVReg = MRI->createGenericVirtualRegister(Ty);
16981698 MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(
16991699 &I, &MIRBuilder.getMBB(), Arg));
17001700 Args.push_back(InVReg);
17611761 .addSym(MF->addLandingPad(&MBB));
17621762
17631763 LLT Ty = getLLTForType(*LP.getType(), *DL);
1764 unsigned Undef = MRI->createGenericVirtualRegister(Ty);
1764 Register Undef = MRI->createGenericVirtualRegister(Ty);
17651765 MIRBuilder.buildUndef(Undef);
17661766
17671767 SmallVector Tys;
17701770 assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
17711771
17721772 // Mark exception register as live in.
1773 unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1773 Register ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
17741774 if (!ExceptionReg)
17751775 return false;
17761776
17781778 ArrayRef ResRegs = getOrCreateVRegs(LP);
17791779 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
17801780
1781 unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1781 Register SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
17821782 if (!SelectorReg)
17831783 return false;
17841784
17851785 MBB.addLiveIn(SelectorReg);
1786 unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1786 Register PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
17871787 MIRBuilder.buildCopy(PtrVReg, SelectorReg);
17881788 MIRBuilder.buildCast(ResRegs[1], PtrVReg);
17891789
17981798 return true;
17991799
18001800 if (AI.isStaticAlloca()) {
1801 unsigned Res = getOrCreateVReg(AI);
1801 Register Res = getOrCreateVReg(AI);
18021802 int FI = getOrCreateFrameIndex(AI);
18031803 MIRBuilder.buildFrameIndex(Res, FI);
18041804 return true;
18131813 unsigned Align =
18141814 std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
18151815
1816 unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1816 Register NumElts = getOrCreateVReg(*AI.getArraySize());
18171817
18181818 Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
18191819 LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
18201820 if (MRI->getType(NumElts) != IntPtrTy) {
1821 unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1821 Register ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
18221822 MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
18231823 NumElts = ExtElts;
18241824 }
18251825
1826 unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1827 unsigned TySize =
1826 Register AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1827 Register TySize =
18281828 getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
18291829 MIRBuilder.buildMul(AllocSize, NumElts, TySize);
18301830
18311831 LLT PtrTy = getLLTForType(*AI.getType(), *DL);
18321832 auto &TLI = *MF->getSubtarget().getTargetLowering();
1833 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1834
1835 unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1833 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
1834
1835 Register SPTmp = MRI->createGenericVirtualRegister(PtrTy);
18361836 MIRBuilder.buildCopy(SPTmp, SPReg);
18371837
1838 unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1838 Register AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
18391839 MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
18401840
18411841 // Handle alignment. We have to realign if the allocation granule was smaller
18481848 // Round the size of the allocation up to the stack alignment size
18491849 // by add SA-1 to the size. This doesn't overflow because we're computing
18501850 // an address inside an alloca.
1851 unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1851 Register AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
18521852 MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
18531853 AllocTmp = AlignedAlloc;
18541854 }
18781878 // If it is a <1 x Ty> vector, use the scalar as it is
18791879 // not a legal vector type in LLT.
18801880 if (U.getType()->getVectorNumElements() == 1) {
1881 unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1881 Register Elt = getOrCreateVReg(*U.getOperand(1));
18821882 auto &Regs = *VMap.getVRegs(U);
18831883 if (Regs.empty()) {
18841884 Regs.push_back(Elt);
18891889 return true;
18901890 }
18911891
1892 unsigned Res = getOrCreateVReg(U);
1893 unsigned Val = getOrCreateVReg(*U.getOperand(0));
1894 unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1895 unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1892 Register Res = getOrCreateVReg(U);
1893 Register Val = getOrCreateVReg(*U.getOperand(0));
1894 Register Elt = getOrCreateVReg(*U.getOperand(1));
1895 Register Idx = getOrCreateVReg(*U.getOperand(2));
18961896 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
18971897 return true;
18981898 }
19021902 // If it is a <1 x Ty> vector, use the scalar as it is
19031903 // not a legal vector type in LLT.
19041904 if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1905 unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1905 Register Elt = getOrCreateVReg(*U.getOperand(0));
19061906 auto &Regs = *VMap.getVRegs(U);
19071907 if (Regs.empty()) {
19081908 Regs.push_back(Elt);
19121912 }
19131913 return true;
19141914 }
1915 unsigned Res = getOrCreateVReg(U);
1916 unsigned Val = getOrCreateVReg(*U.getOperand(0));
1915 Register Res = getOrCreateVReg(U);
1916 Register Val = getOrCreateVReg(*U.getOperand(0));
19171917 const auto &TLI = *MF->getSubtarget().getTargetLowering();
19181918 unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
1919 unsigned Idx = 0;
1919 Register Idx;
19201920 if (auto *CI = dyn_cast(U.getOperand(1))) {
19211921 if (CI->getBitWidth() != PreferredVecIdxWidth) {
19221922 APInt NewIdx = CI->getValue().sextOrTrunc(PreferredVecIdxWidth);
19721972 Type *ValType = ResType->Type::getStructElementType(0);
19731973
19741974 auto Res = getOrCreateVRegs(I);
1975 unsigned OldValRes = Res[0];
1976 unsigned SuccessRes = Res[1];
1977 unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1978 unsigned Cmp = getOrCreateVReg(*I.getCompareOperand());
1979 unsigned NewVal = getOrCreateVReg(*I.getNewValOperand());
1975 Register OldValRes = Res[0];
1976 Register SuccessRes = Res[1];
1977 Register Addr = getOrCreateVReg(*I.getPointerOperand());
1978 Register Cmp = getOrCreateVReg(*I.getCompareOperand());
1979 Register NewVal = getOrCreateVReg(*I.getNewValOperand());
19801980
19811981 MIRBuilder.buildAtomicCmpXchgWithSuccess(
19821982 OldValRes, SuccessRes, Addr, Cmp, NewVal,
19981998
19991999 Type *ResType = I.getType();
20002000
2001 unsigned Res = getOrCreateVReg(I);
2002 unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
2003 unsigned Val = getOrCreateVReg(*I.getValOperand());
2001 Register Res = getOrCreateVReg(I);
2002 Register Addr = getOrCreateVReg(*I.getPointerOperand());
2003 Register Val = getOrCreateVReg(*I.getValOperand());
20042004
20052005 unsigned Opcode = 0;
20062006 switch (I.getOperation()) {
21122112 }
21132113 }
21142114
2115 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
2115 bool IRTranslator::translate(const Constant &C, Register Reg) {
21162116 if (auto CI = dyn_cast(&C))
21172117 EntryBuilder->buildConstant(Reg, *CI);
21182118 else if (auto CF = dyn_cast(&C))
21252125 unsigned NullSize = DL->getTypeSizeInBits(C.getType());
21262126 auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
21272127 auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
2128 unsigned ZeroReg = getOrCreateVReg(*ZeroVal);
2128 Register ZeroReg = getOrCreateVReg(*ZeroVal);
21292129 EntryBuilder->buildCast(Reg, ZeroReg);
21302130 } else if (auto GV = dyn_cast(&C))
21312131 EntryBuilder->buildGlobalValue(Reg, GV);
525525 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
526526 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
527527
528 unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
528 Register CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
529529 MIRBuilder.buildConstant(CarryIn, 0);
530530
531531 for (int i = 0; i < NumParts; ++i) {
532 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
533 unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
532 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
533 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
534534
535535 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
536536 Src2Regs[i], CarryIn);
538538 DstRegs.push_back(DstReg);
539539 CarryIn = CarryOut;
540540 }
541 unsigned DstReg = MI.getOperand(0).getReg();
541 Register DstReg = MI.getOperand(0).getReg();
542542 if(MRI.getType(DstReg).isVector())
543543 MIRBuilder.buildBuildVector(DstReg, DstRegs);
544544 else
558558 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
559559 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
560560
561 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
562 unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
561 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
562 Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
563563 MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
564564 {Src1Regs[0], Src2Regs[0]});
565565 DstRegs.push_back(DstReg);
566 unsigned BorrowIn = BorrowOut;
566 Register BorrowIn = BorrowOut;
567567 for (int i = 1; i < NumParts; ++i) {
568568 DstReg = MRI.createGenericVirtualRegister(NarrowTy);
569569 BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
587587 return narrowScalarInsert(MI, TypeIdx, NarrowTy);
588588 case TargetOpcode::G_LOAD: {
589589 const auto &MMO = **MI.memoperands_begin();
590 unsigned DstReg = MI.getOperand(0).getReg();
590 Register DstReg = MI.getOperand(0).getReg();
591591 LLT DstTy = MRI.getType(DstReg);
592592 if (DstTy.isVector())
593593 return UnableToLegalize;
594594
595595 if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
596 unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
596 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
597597 auto &MMO = **MI.memoperands_begin();
598598 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
599599 MIRBuilder.buildAnyExt(DstReg, TmpReg);
606606 case TargetOpcode::G_ZEXTLOAD:
607607 case TargetOpcode::G_SEXTLOAD: {
608608 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
609 unsigned DstReg = MI.getOperand(0).getReg();
610 unsigned PtrReg = MI.getOperand(1).getReg();
611
612 unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
609 Register DstReg = MI.getOperand(0).getReg();
610 Register PtrReg = MI.getOperand(1).getReg();
611
612 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
613613 auto &MMO = **MI.memoperands_begin();
614614 if (MMO.getSizeInBits() == NarrowSize) {
615615 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
633633 case TargetOpcode::G_STORE: {
634634 const auto &MMO = **MI.memoperands_begin();
635635
636 unsigned SrcReg = MI.getOperand(0).getReg();
636 Register SrcReg = MI.getOperand(0).getReg();
637637 LLT SrcTy = MRI.getType(SrcReg);
638638 if (SrcTy.isVector())
639639 return UnableToLegalize;
645645 return UnableToLegalize;
646646
647647 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
648 unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
648 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
649649 auto &MMO = **MI.memoperands_begin();
650650 MIRBuilder.buildTrunc(TmpReg, SrcReg);
651651 MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
724724 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
725725 unsigned OpIdx, unsigned TruncOpcode) {
726726 MachineOperand &MO = MI.getOperand(OpIdx);
727 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
727 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
728728 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
729729 MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
730730 MO.setReg(DstExt);
733733 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
734734 unsigned OpIdx, unsigned ExtOpcode) {
735735 MachineOperand &MO = MI.getOperand(OpIdx);
736 unsigned DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
736 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
737737 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
738738 MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
739739 MO.setReg(DstTrunc);
742742 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
743743 unsigned OpIdx) {
744744 MachineOperand &MO = MI.getOperand(OpIdx);
745 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
745 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
746746 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
747747 MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
748748 MO.setReg(DstExt);
772772 return;
773773 }
774774
775 unsigned MoreReg = MRI.createGenericVirtualRegister(MoreTy);
776 unsigned ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
775 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
776 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
777777 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
778778 MO.setReg(MoreReg);
779779 }
793793 unsigned NumSrc = MI.getNumOperands() - 1;
794794 unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
795795
796 unsigned Src1 = MI.getOperand(1).getReg();
796 Register Src1 = MI.getOperand(1).getReg();
797797 Register ResultReg = MIRBuilder.buildZExt(DstTy, Src1)->getOperand(0).getReg();
798798
799799 for (unsigned I = 2; I != NumOps; ++I) {
10011001 return Legalized;
10021002 }
10031003
1004 unsigned SrcReg = MI.getOperand(1).getReg();
1004 Register SrcReg = MI.getOperand(1).getReg();
10051005
10061006 // First ZEXT the input.
10071007 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
10341034 }
10351035 case TargetOpcode::G_BSWAP: {
10361036 Observer.changingInstr(MI);
1037 unsigned DstReg = MI.getOperand(0).getReg();
1038
1039 unsigned ShrReg = MRI.createGenericVirtualRegister(WideTy);
1040 unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
1041 unsigned ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1037 Register DstReg = MI.getOperand(0).getReg();
1038
1039 Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1040 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1041 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
10421042 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
10431043
10441044 MI.getOperand(0).setReg(DstExt);
12981298 }
12991299 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
13001300 if (TypeIdx == 0) {
1301 unsigned VecReg = MI.getOperand(1).getReg();
1301 Register VecReg = MI.getOperand(1).getReg();
13021302 LLT VecTy = MRI.getType(VecReg);
13031303 Observer.changingInstr(MI);
13041304
13801380 return UnableToLegalize;
13811381 case TargetOpcode::G_SREM:
13821382 case TargetOpcode::G_UREM: {
1383 unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
1383 Register QuotReg = MRI.createGenericVirtualRegister(Ty);
13841384 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
13851385 .addDef(QuotReg)
13861386 .addUse(MI.getOperand(1).getReg())
13871387 .addUse(MI.getOperand(2).getReg());
13881388
1389 unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
1389 Register ProdReg = MRI.createGenericVirtualRegister(Ty);
13901390 MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
13911391 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
13921392 ProdReg);
13971397 case TargetOpcode::G_UMULO: {
13981398 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
13991399 // result.
1400 unsigned Res = MI.getOperand(0).getReg();
1401 unsigned Overflow = MI.getOperand(1).getReg();
1402 unsigned LHS = MI.getOperand(2).getReg();
1403 unsigned RHS = MI.getOperand(3).getReg();
1400 Register Res = MI.getOperand(0).getReg();
1401 Register Overflow = MI.getOperand(1).getReg();
1402 Register LHS = MI.getOperand(2).getReg();
1403 Register RHS = MI.getOperand(3).getReg();
14041404
14051405 MIRBuilder.buildMul(Res, LHS, RHS);
14061406
14081408 ? TargetOpcode::G_SMULH
14091409 : TargetOpcode::G_UMULH;
14101410
1411 unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
1411 Register HiPart = MRI.createGenericVirtualRegister(Ty);
14121412 MIRBuilder.buildInstr(Opcode)
14131413 .addDef(HiPart)
14141414 .addUse(LHS)
14151415 .addUse(RHS);
14161416
1417 unsigned Zero = MRI.createGenericVirtualRegister(Ty);
1417 Register Zero = MRI.createGenericVirtualRegister(Ty);
14181418 MIRBuilder.buildConstant(Zero, 0);
14191419
14201420 // For *signed* multiply, overflow is detected by checking:
14211421 // (hi != (lo >> bitwidth-1))
14221422 if (Opcode == TargetOpcode::G_SMULH) {
1423 unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
1424 unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1423 Register Shifted = MRI.createGenericVirtualRegister(Ty);
1424 Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
14251425 MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
14261426 MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
14271427 .addDef(Shifted)
14391439 // represent them.
14401440 if (Ty.isVector())
14411441 return UnableToLegalize;
1442 unsigned Res = MI.getOperand(0).getReg();
1442 Register Res = MI.getOperand(0).getReg();
14431443 Type *ZeroTy;
14441444 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
14451445 switch (Ty.getSizeInBits()) {
14611461 ConstantFP &ZeroForNegation =
14621462 *cast(ConstantFP::getZeroValueForNegation(ZeroTy));
14631463 auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1464 unsigned SubByReg = MI.getOperand(1).getReg();
1465 unsigned ZeroReg = Zero->getOperand(0).getReg();
1464 Register SubByReg = MI.getOperand(1).getReg();
1465 Register ZeroReg = Zero->getOperand(0).getReg();
14661466 MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
14671467 MI.getFlags());
14681468 MI.eraseFromParent();
14741474 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
14751475 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
14761476 return UnableToLegalize;
1477 unsigned Res = MI.getOperand(0).getReg();
1478 unsigned LHS = MI.getOperand(1).getReg();
1479 unsigned RHS = MI.getOperand(2).getReg();
1480 unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1477 Register Res = MI.getOperand(0).getReg();
1478 Register LHS = MI.getOperand(1).getReg();
1479 Register RHS = MI.getOperand(2).getReg();
1480 Register Neg = MRI.createGenericVirtualRegister(Ty);
14811481 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
14821482 MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
14831483 MI.eraseFromParent();
14841484 return Legalized;
14851485 }
14861486 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1487 unsigned OldValRes = MI.getOperand(0).getReg();
1488 unsigned SuccessRes = MI.getOperand(1).getReg();
1489 unsigned Addr = MI.getOperand(2).getReg();
1490 unsigned CmpVal = MI.getOperand(3).getReg();
1491 unsigned NewVal = MI.getOperand(4).getReg();
1487 Register OldValRes = MI.getOperand(0).getReg();
1488 Register SuccessRes = MI.getOperand(1).getReg();
1489 Register Addr = MI.getOperand(2).getReg();
1490 Register CmpVal = MI.getOperand(3).getReg();
1491 Register NewVal = MI.getOperand(4).getReg();
14921492 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
14931493 **MI.memoperands_begin());
14941494 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
14991499 case TargetOpcode::G_SEXTLOAD:
15001500 case TargetOpcode::G_ZEXTLOAD: {
15011501 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1502 unsigned DstReg = MI.getOperand(0).getReg();
1503 unsigned PtrReg = MI.getOperand(1).getReg();
1502 Register DstReg = MI.getOperand(0).getReg();
1503 Register PtrReg = MI.getOperand(1).getReg();
15041504 LLT DstTy = MRI.getType(DstReg);
15051505 auto &MMO = **MI.memoperands_begin();
15061506
15151515 }
15161516
15171517 if (DstTy.isScalar()) {
1518 unsigned TmpReg =
1518 Register TmpReg =
15191519 MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
15201520 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
15211521 switch (MI.getOpcode()) {
15441544 case TargetOpcode::G_CTPOP:
15451545 return lowerBitCount(MI, TypeIdx, Ty);
15461546 case G_UADDO: {
1547 unsigned Res = MI.getOperand(0).getReg();
1548 unsigned CarryOut = MI.getOperand(1).getReg();
1549 unsigned LHS = MI.getOperand(2).getReg();
1550 unsigned RHS = MI.getOperand(3).getReg();
1547 Register Res = MI.getOperand(0).getReg();
1548 Register CarryOut = MI.getOperand(1).getReg();
1549 Register LHS = MI.getOperand(2).getReg();
1550 Register RHS = MI.getOperand(3).getReg();
15511551
15521552 MIRBuilder.buildAdd(Res, LHS, RHS);
15531553 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
15561556 return Legalized;
15571557 }
15581558 case G_UADDE: {
1559 unsigned Res = MI.getOperand(0).getReg();
1560 unsigned CarryOut = MI.getOperand(1).getReg();
1561 unsigned LHS = MI.getOperand(2).getReg();
1562 unsigned RHS = MI.getOperand(3).getReg();
1563 unsigned CarryIn = MI.getOperand(4).getReg();
1564
1565 unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1566 unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1559 Register Res = MI.getOperand(0).getReg();
1560 Register CarryOut = MI.getOperand(1).getReg();
1561 Register LHS = MI.getOperand(2).getReg();
1562 Register RHS = MI.getOperand(3).getReg();
1563 Register CarryIn = MI.getOperand(4).getReg();
1564
1565 Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1566 Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
15671567
15681568 MIRBuilder.buildAdd(TmpRes, LHS, RHS);
15691569 MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
15741574 return Legalized;
15751575 }
15761576 case G_USUBO: {
1577 unsigned Res = MI.getOperand(0).getReg();
1578 unsigned BorrowOut = MI.getOperand(1).getReg();
1579 unsigned LHS = MI.getOperand(2).getReg();
1580 unsigned RHS = MI.getOperand(3).getReg();
1577 Register Res = MI.getOperand(0).getReg();
1578 Register BorrowOut = MI.getOperand(1).getReg();
1579 Register LHS = MI.getOperand(2).getReg();
1580 Register RHS = MI.getOperand(3).getReg();
15811581
15821582 MIRBuilder.buildSub(Res, LHS, RHS);
15831583 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
15861586 return Legalized;
15871587 }
15881588 case G_USUBE: {
1589 unsigned Res = MI.getOperand(0).getReg();
1590 unsigned BorrowOut = MI.getOperand(1).getReg();
1591 unsigned LHS = MI.getOperand(2).getReg();
1592 unsigned RHS = MI.getOperand(3).getReg();
1593 unsigned BorrowIn = MI.getOperand(4).getReg();
1594
1595 unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1596 unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1597 unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1598 unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1589 Register Res = MI.getOperand(0).getReg();
1590 Register BorrowOut = MI.getOperand(1).getReg();
1591 Register LHS = MI.getOperand(2).getReg();
1592 Register RHS = MI.getOperand(3).getReg();
1593 Register BorrowIn = MI.getOperand(4).getReg();
1594
1595 Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1596 Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1597 Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1598 Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
15991599
16001600 MIRBuilder.buildSub(TmpRes, LHS, RHS);
16011601 MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
16191619 SmallVector DstRegs;
16201620
16211621 unsigned NarrowSize = NarrowTy.getSizeInBits();
1622 unsigned DstReg = MI.getOperand(0).getReg();
1622 Register DstReg = MI.getOperand(0).getReg();
16231623 unsigned Size = MRI.getType(DstReg).getSizeInBits();
16241624 int NumParts = Size / NarrowSize;
16251625 // FIXME: Don't know how to handle the situation where the small vectors
16281628 return UnableToLegalize;
16291629
16301630 for (int i = 0; i < NumParts; ++i) {
1631 unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1631 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
16321632 MIRBuilder.buildUndef(TmpReg);
16331633 DstRegs.push_back(TmpReg);
16341634 }
16631663 return UnableToLegalize;
16641664
16651665 if (BitsForNumParts != Size) {
1666 unsigned AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1666 Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
16671667 MIRBuilder.buildUndef(AccumDstReg);
16681668
16691669 // Handle the pieces which evenly divide into the requested type with
16711671 for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
16721672 SmallVector SrcOps;
16731673 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1674 unsigned PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1674 Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
16751675 MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
16761676 SrcOps.push_back(PartOpReg);
16771677 }
16781678
1679 unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1679 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
16801680 MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
16811681
1682 unsigned PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1682 Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
16831683 MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
16841684 AccumDstReg = PartInsertReg;
16851685 }
16871687 // Handle the remaining element sized leftover piece.
16881688 SmallVector SrcOps;
16891689 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1690 unsigned PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1690 Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
16911691 MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
16921692 BitsForNumParts);
16931693 SrcOps.push_back(PartOpReg);
16941694 }
16951695
1696 unsigned PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1696 Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
16971697 MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
16981698 MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
16991699 MI.eraseFromParent();
17121712 extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
17131713
17141714 for (int i = 0; i < NumParts; ++i) {
1715 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1715 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
17161716
17171717 if (NumOps == 1)
17181718 MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
17571757 const unsigned NewNumElts =
17581758 NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
17591759
1760 const unsigned DstReg = MI.getOperand(0).getReg();
1760 const Register DstReg = MI.getOperand(0).getReg();
17611761 LLT DstTy = MRI.getType(DstReg);
17621762 LLT LeftoverTy0;
17631763
17771777
17781778 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
17791779 LLT LeftoverTy;
1780 unsigned SrcReg = MI.getOperand(I).getReg();
1780 Register SrcReg = MI.getOperand(I).getReg();
17811781 LLT SrcTyI = MRI.getType(SrcReg);
17821782 LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
17831783 LLT LeftoverTyI;
17911791 if (I == 1) {
17921792 // For the first operand, create an instruction for each part and setup
17931793 // the result.
1794 for (unsigned PartReg : PartRegs) {
1795 unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1794 for (Register PartReg : PartRegs) {
1795 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
17961796 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
17971797 .addDef(PartDstReg)
17981798 .addUse(PartReg));
17991799 DstRegs.push_back(PartDstReg);
18001800 }
18011801
1802 for (unsigned LeftoverReg : LeftoverRegs) {
1803 unsigned PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1802 for (Register LeftoverReg : LeftoverRegs) {
1803 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
18041804 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
18051805 .addDef(PartDstReg)
18061806 .addUse(LeftoverReg));
18391839 if (TypeIdx != 0)
18401840 return UnableToLegalize;
18411841
1842 unsigned DstReg = MI.getOperand(0).getReg();
1843 unsigned SrcReg = MI.getOperand(1).getReg();
1842 Register DstReg = MI.getOperand(0).getReg();
1843 Register SrcReg = MI.getOperand(1).getReg();
18441844 LLT DstTy = MRI.getType(DstReg);
18451845 LLT SrcTy = MRI.getType(SrcReg);
18461846
18641864 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
18651865
18661866 for (unsigned I = 0; I < NumParts; ++I) {
1867 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1867 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
18681868 MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
18691869 .addDef(DstReg)
18701870 .addUse(SrcRegs[I]);
18851885 LegalizerHelper::LegalizeResult
18861886 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
18871887 LLT NarrowTy) {
1888 unsigned DstReg = MI.getOperand(0).getReg();
1889 unsigned Src0Reg = MI.getOperand(2).getReg();
1888 Register DstReg = MI.getOperand(0).getReg();
1889 Register Src0Reg = MI.getOperand(2).getReg();
18901890 LLT DstTy = MRI.getType(DstReg);
18911891 LLT SrcTy = MRI.getType(Src0Reg);
18921892
19281928 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
19291929
19301930 for (unsigned I = 0; I < NumParts; ++I) {
1931 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1931 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
19321932 DstRegs.push_back(DstReg);
19331933
19341934 if (MI.getOpcode() == TargetOpcode::G_ICMP)
20242024 LegalizerHelper::LegalizeResult
20252025 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
20262026 LLT NarrowTy) {
2027 const unsigned DstReg = MI.getOperand(0).getReg();
2027 const Register DstReg = MI.getOperand(0).getReg();
20282028 LLT PhiTy = MRI.getType(DstReg);
20292029 LLT LeftoverTy;
20302030
20652065 PartRegs.clear();
20662066 LeftoverRegs.clear();
20672067
2068 unsigned SrcReg = MI.getOperand(I).getReg();
2068 Register SrcReg = MI.getOperand(I).getReg();
20692069 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
20702070 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
20712071
22652265 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
22662266 const LLT HalfTy, const LLT AmtTy) {
22672267
2268 unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2269 unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2268 Register InL = MRI.createGenericVirtualRegister(HalfTy);
2269 Register InH = MRI.createGenericVirtualRegister(HalfTy);
22702270 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
22712271
22722272 if (Amt.isNullValue()) {
22792279 unsigned NVTBits = HalfTy.getSizeInBits();
22802280 unsigned VTBits = 2 * NVTBits;
22812281
2282 SrcOp Lo(0), Hi(0);
2282 SrcOp Lo(Register(0)), Hi(Register(0));
22832283 if (MI.getOpcode() == TargetOpcode::G_SHL) {
22842284 if (Amt.ugt(VTBits)) {
22852285 Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
23602360 return Legalized;
23612361 }
23622362
2363 unsigned DstReg = MI.getOperand(0).getReg();
2363 Register DstReg = MI.getOperand(0).getReg();
23642364 LLT DstTy = MRI.getType(DstReg);
23652365 if (DstTy.isVector())
23662366 return UnableToLegalize;
23672367
2368 unsigned Amt = MI.getOperand(2).getReg();
2368 Register Amt = MI.getOperand(2).getReg();
23692369 LLT ShiftAmtTy = MRI.getType(Amt);
23702370 const unsigned DstEltSize = DstTy.getScalarSizeInBits();
23712371 if (DstEltSize % 2 != 0)
23892389 // Handle the fully general expansion by an unknown amount.
23902390 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
23912391
2392 unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2393 unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2392 Register InL = MRI.createGenericVirtualRegister(HalfTy);
2393 Register InH = MRI.createGenericVirtualRegister(HalfTy);
23942394 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
23952395
23962396 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
25642564 unsigned DstParts = DstRegs.size();
25652565
25662566 unsigned DstIdx = 0; // Low bits of the result.
2567 unsigned FactorSum =
2567 Register FactorSum =
25682568 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
25692569 DstRegs[DstIdx] = FactorSum;
25702570
25912591 Factors.push_back(CarrySumPrevDstIdx);
25922592 }
25932593
2594 unsigned CarrySum = 0;
2594 Register CarrySum;
25952595 // Add all factors and accumulate all carries into CarrySum.
25962596 if (DstIdx != DstParts - 1) {
25972597 MachineInstrBuilder Uaddo =
26722672 SmallVector Indexes;
26732673 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
26742674
2675 unsigned OpReg = MI.getOperand(0).getReg();
2675 Register OpReg = MI.getOperand(0).getReg();
26762676 uint64_t OpStart = MI.getOperand(2).getImm();
26772677 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
26782678 for (int i = 0; i < NumParts; ++i) {
26992699 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
27002700 }
27012701
2702 unsigned SegReg = SrcRegs[i];
2702 Register SegReg = SrcRegs[i];
27032703 if (ExtractOffset != 0 || SegSize != NarrowSize) {
27042704 // A genuine extract is needed.
27052705 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
27092709 DstRegs.push_back(SegReg);
27102710 }
27112711
2712 unsigned DstReg = MI.getOperand(0).getReg();
2712 Register DstReg = MI.getOperand(0).getReg();
27132713 if(MRI.getType(DstReg).isVector())
27142714 MIRBuilder.buildBuildVector(DstReg, DstRegs);
27152715 else
27392739 SmallVector Indexes;
27402740 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
27412741
2742 unsigned OpReg = MI.getOperand(2).getReg();
2742 Register OpReg = MI.getOperand(2).getReg();
27432743 uint64_t OpStart = MI.getOperand(3).getImm();
27442744 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
27452745 for (int i = 0; i < NumParts; ++i) {
27712771 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
27722772 }
27732773
2774 unsigned SegReg = OpReg;
2774 Register SegReg = OpReg;
27752775 if (ExtractOffset != 0 || SegSize != OpSize) {
27762776 // A genuine extract is needed.
27772777 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
27782778 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
27792779 }
27802780
2781 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2781 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
27822782 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
27832783 DstRegs.push_back(DstReg);
27842784 }
27852785
27862786 assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2787 unsigned DstReg = MI.getOperand(0).getReg();
2787 Register DstReg = MI.getOperand(0).getReg();
27882788 if(MRI.getType(DstReg).isVector())
27892789 MIRBuilder.buildBuildVector(DstReg, DstRegs);
27902790 else
27962796 LegalizerHelper::LegalizeResult
27972797 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
27982798 LLT NarrowTy) {
2799 unsigned DstReg = MI.getOperand(0).getReg();
2799 Register DstReg = MI.getOperand(0).getReg();
28002800 LLT DstTy = MRI.getType(DstReg);
28012801
28022802 assert(MI.getNumOperands() == 3 && TypeIdx == 0);
28402840 if (TypeIdx != 0)
28412841 return UnableToLegalize;
28422842
2843 unsigned CondReg = MI.getOperand(1).getReg();
2843 Register CondReg = MI.getOperand(1).getReg();
28442844 LLT CondTy = MRI.getType(CondReg);
28452845 if (CondTy.isVector()) // TODO: Handle vselect
28462846 return UnableToLegalize;
28472847
2848 unsigned DstReg = MI.getOperand(0).getReg();
2848 Register DstReg = MI.getOperand(0).getReg();
28492849 LLT DstTy = MRI.getType(DstReg);
28502850
28512851 SmallVector DstRegs, DstLeftoverRegs;
28992899 return Legalized;
29002900 }
29012901 case TargetOpcode::G_CTLZ: {
2902 unsigned SrcReg = MI.getOperand(1).getReg();
2902 Register SrcReg = MI.getOperand(1).getReg();
29032903 unsigned Len = Ty.getSizeInBits();
29042904 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
29052905 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
29252925 // return Len - popcount(x);
29262926 //
29272927 // Ref: "Hacker's Delight" by Henry Warren
2928 unsigned Op = SrcReg;
2928 Register Op = SrcReg;
29292929 unsigned NewLen = PowerOf2Ceil(Len);
29302930 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
29312931 auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
29492949 return Legalized;
29502950 }
29512951 case TargetOpcode::G_CTTZ: {
2952 unsigned SrcReg = MI.getOperand(1).getReg();
2952 Register SrcReg = MI.getOperand(1).getReg();
29532953 unsigned Len = Ty.getSizeInBits();
29542954 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
29552955 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
29972997 // representation.
29982998 LegalizerHelper::LegalizeResult
29992999 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3000 unsigned Dst = MI.getOperand(0).getReg();
3001 unsigned Src = MI.getOperand(1).getReg();
3000 Register Dst = MI.getOperand(0).getReg();
3001 Register Src = MI.getOperand(1).getReg();
30023002 const LLT S64 = LLT::scalar(64);
30033003 const LLT S32 = LLT::scalar(32);
30043004 const LLT S1 = LLT::scalar(1);
30533053
30543054 LegalizerHelper::LegalizeResult
30553055 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3056 unsigned Dst = MI.getOperand(0).getReg();
3057 unsigned Src = MI.getOperand(1).getReg();
3056 Register Dst = MI.getOperand(0).getReg();
3057 Register Src = MI.getOperand(1).getReg();
30583058 LLT DstTy = MRI.getType(Dst);
30593059 LLT SrcTy = MRI.getType(Src);
30603060
30743074
30753075 LegalizerHelper::LegalizeResult
30763076 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3077 unsigned Dst = MI.getOperand(0).getReg();
3078 unsigned Src = MI.getOperand(1).getReg();
3077 Register Dst = MI.getOperand(0).getReg();
3078 Register Src = MI.getOperand(1).getReg();
30793079 LLT DstTy = MRI.getType(Dst);
30803080 LLT SrcTy = MRI.getType(Src);
30813081
30923092 // float r = cul2f((l + s) ^ s);
30933093 // return s ? -r : r;
30943094 // }
3095 unsigned L = Src;
3095 Register L = Src;
30963096 auto SignBit = MIRBuilder.buildConstant(S64, 63);
30973097 auto S = MIRBuilder.buildAShr(S64, L, SignBit);
30983098
2121
2222 using namespace llvm;
2323
24 unsigned SwiftErrorValueTracking::getOrCreateVReg(const MachineBasicBlock *MBB,
24 Register SwiftErrorValueTracking::getOrCreateVReg(const MachineBasicBlock *MBB,
2525 const Value *Val) {
2626 auto Key = std::make_pair(MBB, Val);
2727 auto It = VRegDefMap.find(Key);
4545 VRegDefMap[std::make_pair(MBB, Val)] = VReg;
4646 }
4747
48 unsigned SwiftErrorValueTracking::getOrCreateVRegDefAt(
48 Register SwiftErrorValueTracking::getOrCreateVRegDefAt(
4949 const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) {
5050 auto Key = PointerIntPair(I, true);
5151 auto It = VRegDefUses.find(Key);
5454
5555 auto &DL = MF->getDataLayout();
5656 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
57 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
57 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
5858 VRegDefUses[Key] = VReg;
5959 setCurrentVReg(MBB, Val, VReg);
6060 return VReg;
6161 }
6262
63 unsigned SwiftErrorValueTracking::getOrCreateVRegUseAt(
63 Register SwiftErrorValueTracking::getOrCreateVRegUseAt(
6464 const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) {
6565 auto Key = PointerIntPair(I, false);
6666 auto It = VRegDefUses.find(Key);
6767 if (It != VRegDefUses.end())
6868 return It->second;
6969
70 unsigned VReg = getOrCreateVReg(MBB, Val);
70 Register VReg = getOrCreateVReg(MBB, Val);
7171 VRegDefUses[Key] = VReg;
7272 return VReg;
7373 }
128128 // least by the 'return' of the swifterror.
129129 if (SwiftErrorArg && SwiftErrorArg == SwiftErrorVal)
130130 continue;
131 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
131 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
132132 // Assign Undef to Vreg. We construct MI directly to make sure it works
133133 // with FastISel.
134134 BuildMI(*MBB, MBB->getFirstNonPHI(), DbgLoc,
176176
177177 // Check whether we have a single vreg def from all predecessors.
178178 // Otherwise we need a phi.
179 SmallVectorunsigned>, 4> VRegs;
179 SmallVectorRegister>, 4> VRegs;
180180 SmallSet Visited;
181181 for (auto *Pred : MBB->predecessors()) {
182182 if (!Visited.insert(Pred).second)
202202 VRegs.size() >= 1 &&
203203 std::find_if(
204204 VRegs.begin(), VRegs.end(),
205 [&](const std::pairunsigned> &V)
205 [&](const std::pairRegister> &V)
206206 -> bool { return V.second != VRegs[0].second; }) !=
207207 VRegs.end();
208208
226226 assert(UpwardsUse);
227227 assert(!VRegs.empty() &&
228228 "No predecessors? Is the Calling Convention correct?");
229 unsigned DestReg = UUseVReg;
229 Register DestReg = UUseVReg;
230230 BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY),
231231 DestReg)
232232 .addReg(VRegs[0].second);
5656 CCAssignFn *AssignFn)
5757 : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
5858
59 unsigned getStackAddress(uint64_t Size, int64_t Offset,
59 Register getStackAddress(uint64_t Size, int64_t Offset,
6060 MachinePointerInfo &MPO) override {
6161 auto &MFI = MIRBuilder.getMF().getFrameInfo();
6262 int FI = MFI.CreateFixedObject(Size, Offset, true);
6363 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
64 unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
64 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
6565 MIRBuilder.buildFrameIndex(AddrReg, FI);
6666 StackUsed = std::max(StackUsed, Size + Offset);
6767 return AddrReg;
6868 }
6969
70 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
70 void assignValueToReg(Register ValVReg, Register PhysReg,
7171 CCValAssign &VA) override {
7272 markPhysRegUsed(PhysReg);
7373 switch (VA.getLocInfo()) {
8484 }
8585 }
8686
87 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
87 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
8888 MachinePointerInfo &MPO, CCValAssign &VA) override {
8989 // FIXME: Get alignment
9090 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
132132 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
133133 AssignFnVarArg(AssignFnVarArg), StackSize(0) {}
134134
135 unsigned getStackAddress(uint64_t Size, int64_t Offset,
135 Register getStackAddress(uint64_t Size, int64_t Offset,
136136 MachinePointerInfo &MPO) override {
137137 LLT p0 = LLT::pointer(0, 64);
138138 LLT s64 = LLT::scalar(64);
139 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
140 MIRBuilder.buildCopy(SPReg, AArch64::SP);
141
142 unsigned OffsetReg = MRI.createGenericVirtualRegister(s64);
139 Register SPReg = MRI.createGenericVirtualRegister(p0);
140 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
141
142 Register OffsetReg = MRI.createGenericVirtualRegister(s64);
143143 MIRBuilder.buildConstant(OffsetReg, Offset);
144144
145 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
145 Register AddrReg = MRI.createGenericVirtualRegister(p0);
146146 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
147147
148148 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
149149 return AddrReg;
150150 }
151151
152 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
152 void assignValueToReg(Register ValVReg, Register PhysReg,
153153 CCValAssign &VA) override {
154154 MIB.addUse(PhysReg, RegState::Implicit);
155 unsigned ExtReg = extendRegister(ValVReg, VA);
155 Register ExtReg = extendRegister(ValVReg, VA);
156156 MIRBuilder.buildCopy(PhysReg, ExtReg);
157157 }
158158
159 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
159 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
160160 MachinePointerInfo &MPO, CCValAssign &VA) override {
161161 if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
162162 Size = VA.getLocVT().getSizeInBits() / 8;
262262 return false;
263263 }
264264
265 unsigned CurVReg = VRegs[i];
265 Register CurVReg = VRegs[i];
266266 ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
267267 setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
268268
366366 setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
367367 bool Split = false;
368368 LLT Ty = MRI.getType(VRegs[i]);
369 unsigned Dst = VRegs[i];
369 Register Dst = VRegs[i];
370370
371371 splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
372372 [&](unsigned Reg, uint64_t Offset) {
435435 SmallVector SplitArgs;
436436 for (auto &OrigArg : OrigArgs) {
437437 splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,
438 [&](unsigned Reg, uint64_t Offset) {
438 [&](Register Reg, uint64_t Offset) {
439439 MIRBuilder.buildExtract(Reg, OrigArg.Reg, Offset);
440440 });
441441 // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
511511
512512 if (SwiftErrorVReg) {
513513 MIB.addDef(AArch64::X21, RegState::Implicit);
514 MIRBuilder.buildCopy(SwiftErrorVReg, AArch64::X21);
514 MIRBuilder.buildCopy(SwiftErrorVReg, Register(AArch64::X21));
515515 }
516516
517517 CallSeqStart.addImm(Handler.StackSize).addImm(0);
7373 // returned via 'Dst'.
7474 MachineInstr *emitScalarToVector(unsigned EltSize,
7575 const TargetRegisterClass *DstRC,
76 unsigned Scalar,
76 Register Scalar,
7777 MachineIRBuilder &MIRBuilder) const;
7878
7979 /// Emit a lane insert into \p DstReg, or a new vector register if None is
8282 /// The lane inserted into is defined by \p LaneIdx. The vector source
8383 /// register is given by \p SrcReg. The register containing the element is
8484 /// given by \p EltReg.
85 MachineInstr *emitLaneInsert(Optional DstReg, unsigned SrcReg,
86 unsigned EltReg, unsigned LaneIdx,
85 MachineInstr *emitLaneInsert(Optional DstReg, Register SrcReg,
86 Register EltReg, unsigned LaneIdx,
8787 const RegisterBank &RB,
8888 MachineIRBuilder &MIRBuilder) const;
8989 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
112112 MachineIRBuilder &MIRBuilder) const;
113113
114114 // Emit a vector concat operation.
115 MachineInstr *emitVectorConcat(Optional Dst, unsigned Op1,
116 unsigned Op2,
115 MachineInstr *emitVectorConcat(Optional Dst, Register Op1,
116 Register Op2,
117117 MachineIRBuilder &MIRBuilder) const;
118 MachineInstr *emitExtractVectorElt(Optional<unsigned> DstReg,
118 MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
119119 const RegisterBank &DstRB, LLT ScalarTy,
120 unsigned VecReg, unsigned LaneIdx,
120 Register VecReg, unsigned LaneIdx,
121121 MachineIRBuilder &MIRBuilder) const;
122122
123123 /// Helper function for selecting G_FCONSTANT. If the G_FCONSTANT can be
127127 MachineRegisterInfo &MRI) const;
128128
129129 /// Emit a CSet for a compare.
130 MachineInstr *emitCSetForICMP(unsigned DefReg, unsigned Pred,
130 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
131131 MachineIRBuilder &MIRBuilder) const;
132132
133133 ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
860860 bool AArch64InstructionSelector::selectCompareBranch(
861861 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
862862
863 const unsigned CondReg = I.getOperand(0).getReg();
863 const Register CondReg = I.getOperand(0).getReg();
864864 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
865865 MachineInstr *CCMI = MRI.getVRegDef(CondReg);
866866 if (CCMI->getOpcode() == TargetOpcode::G_TRUNC)
868868 if (CCMI->getOpcode() != TargetOpcode::G_ICMP)
869869 return false;
870870
871 unsigned LHS = CCMI->getOperand(2).getReg();
872 unsigned RHS = CCMI->getOperand(3).getReg();
871 Register LHS = CCMI->getOperand(2).getReg();
872 Register RHS = CCMI->getOperand(3).getReg();
873873 if (!getConstantVRegVal(RHS, MRI))
874874 std::swap(RHS, LHS);
875875
906906 bool AArch64InstructionSelector::selectVectorSHL(
907907 MachineInstr &I, MachineRegisterInfo &MRI) const {
908908 assert(I.getOpcode() == TargetOpcode::G_SHL);
909 unsigned DstReg = I.getOperand(0).getReg();
909 Register DstReg = I.getOperand(0).getReg();
910910 const LLT Ty = MRI.getType(DstReg);
911 unsigned Src1Reg = I.getOperand(1).getReg();
912 unsigned Src2Reg = I.getOperand(2).getReg();
911 Register Src1Reg = I.getOperand(1).getReg();
912 Register Src2Reg = I.getOperand(2).getReg();
913913
914914 if (!Ty.isVector())
915915 return false;
934934 bool AArch64InstructionSelector::selectVectorASHR(
935935 MachineInstr &I, MachineRegisterInfo &MRI) const {
936936 assert(I.getOpcode() == TargetOpcode::G_ASHR);
937 unsigned DstReg = I.getOperand(0).getReg();
937 Register DstReg = I.getOperand(0).getReg();
938938 const LLT Ty = MRI.getType(DstReg);
939 unsigned Src1Reg = I.getOperand(1).getReg();
940 unsigned Src2Reg = I.getOperand(2).getReg();
939 Register Src1Reg = I.getOperand(1).getReg();
940 Register Src2Reg = I.getOperand(2).getReg();
941941
942942 if (!Ty.isVector())
943943 return false;
979979 bool AArch64InstructionSelector::selectVaStartDarwin(
980980 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
981981 AArch64FunctionInfo *FuncInfo = MF.getInfo();
982 unsigned ListReg = I.getOperand(0).getReg();
983
984 unsigned ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
982 Register ListReg = I.getOperand(0).getReg();
983
984 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
985985
986986 auto MIB =
987987 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri))
10351035 constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
10361036 return DstReg;
10371037 };
1038 unsigned DstReg = BuildMovK(MovZ.getReg(0),
1038 Register DstReg = BuildMovK(MovZ.getReg(0),
10391039 AArch64II::MO_G1 | AArch64II::MO_NC, 16, 0);
10401040 DstReg = BuildMovK(DstReg, AArch64II::MO_G2 | AArch64II::MO_NC, 32, 0);
10411041 BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
10601060 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
10611061
10621062 if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) {
1063 const unsigned DefReg = I.getOperand(0).getReg();
1063 const Register DefReg = I.getOperand(0).getReg();
10641064 const LLT DefTy = MRI.getType(DefReg);
10651065
10661066 const TargetRegisterClass *DefRC = nullptr;
11211121 return false;
11221122 }
11231123
1124 const unsigned CondReg = I.getOperand(0).getReg();
1124 const Register CondReg = I.getOperand(0).getReg();
11251125 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
11261126
11271127 // Speculation tracking/SLH assumes that optimized TB(N)Z/CB(N)Z
11661166
11671167 case TargetOpcode::G_BSWAP: {
11681168 // Handle vector types for G_BSWAP directly.
1169 unsigned DstReg = I.getOperand(0).getReg();
1169 Register DstReg = I.getOperand(0).getReg();
11701170 LLT DstTy = MRI.getType(DstReg);
11711171
11721172 // We should only get vector types here; everything else is handled by the
12111211 const LLT s64 = LLT::scalar(64);
12121212 const LLT p0 = LLT::pointer(0, 64);
12131213
1214 const unsigned DefReg = I.getOperand(0).getReg();
1214 const Register DefReg = I.getOperand(0).getReg();
12151215 const LLT DefTy = MRI.getType(DefReg);
12161216 const unsigned DefSize = DefTy.getSizeInBits();
12171217 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
12691269 return true;
12701270
12711271 // Nope. Emit a copy and use a normal mov instead.
1272 const unsigned DefGPRReg = MRI.createVirtualRegister(&GPRRC);
1272 const Register DefGPRReg = MRI.createVirtualRegister(&GPRRC);
12731273 MachineOperand &RegOp = I.getOperand(0);
12741274 RegOp.setReg(DefGPRReg);
12751275 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator()));
13161316 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
13171317 }
13181318
1319 unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
1319 Register DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
13201320 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator()));
13211321 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
13221322 .addReg(DstReg, 0, AArch64::sub_32);
13481348 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
13491349 }
13501350
1351 unsigned SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
1351 Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
13521352 BuildMI(MBB, I.getIterator(), I.getDebugLoc(),
13531353 TII.get(AArch64::SUBREG_TO_REG))
13541354 .addDef(SrcReg)
14261426 }
14271427 unsigned MemSizeInBits = MemOp.getSize() * 8;
14281428
1429 const unsigned PtrReg = I.getOperand(1).getReg();
1429 const Register PtrReg = I.getOperand(1).getReg();
14301430 #ifndef NDEBUG
14311431 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
14321432 // Sanity-check the pointer register.
14361436 "Load/Store pointer operand isn't a pointer");
14371437 #endif
14381438
1439 const unsigned ValReg = I.getOperand(0).getReg();
1439 const Register ValReg = I.getOperand(0).getReg();
14401440 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
14411441
14421442 const unsigned NewOpc =
14871487 return false;
14881488 // If we have a ZEXTLOAD then change the load's type to be a narrower reg
14891489 //and zero_extend with SUBREG_TO_REG.
1490 unsigned LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1491 unsigned DstReg = I.getOperand(0).getReg();
1490 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1491 Register DstReg = I.getOperand(0).getReg();
14921492 I.getOperand(0).setReg(LdReg);
14931493
14941494 MIB.setInsertPt(MIB.getMBB(), std::next(I.getIterator()));
15091509 if (unsupportedBinOp(I, RBI, MRI, TRI))
15101510 return false;
15111511
1512 const unsigned DefReg = I.getOperand(0).getReg();
1512 const Register DefReg = I.getOperand(0).getReg();
15131513 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
15141514
15151515 if (RB.getID() != AArch64::GPRRegBankID) {
15541554
15551555 const unsigned OpSize = Ty.getSizeInBits();
15561556
1557 const unsigned DefReg = I.getOperand(0).getReg();
1557 const Register DefReg = I.getOperand(0).getReg();
15581558 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
15591559
15601560 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);
15991599 // this case, we want to increment when carry is set.
16001600 auto CsetMI = MIRBuilder
16011601 .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
1602 {AArch64::WZR, AArch64::WZR})
1602 {Register(AArch64::WZR), Register(AArch64::WZR)})
16031603 .addImm(getInvertedCondCode(AArch64CC::HS));
16041604 constrainSelectedInstRegOperands(*CsetMI, TII, TRI, RBI);
16051605 I.eraseFromParent();
16221622 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
16231623 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
16241624
1625 const unsigned DstReg = I.getOperand(0).getReg();
1626 const unsigned SrcReg = I.getOperand(1).getReg();
1625 const Register DstReg = I.getOperand(0).getReg();
1626 const Register SrcReg = I.getOperand(1).getReg();
16271627
16281628 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
16291629 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
16801680 }
16811681
16821682 case TargetOpcode::G_ANYEXT: {
1683 const unsigned DstReg = I.getOperand(0).getReg();
1684 const unsigned SrcReg = I.getOperand(1).getReg();
1683 const Register DstReg = I.getOperand(0).getReg();
1684 const Register SrcReg = I.getOperand(1).getReg();
16851685
16861686 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
16871687 if (RBDst.getID() != AArch64::GPRRegBankID) {
17121712 // At this point G_ANYEXT is just like a plain COPY, but we need
17131713 // to explicitly form the 64-bit value if any.
17141714 if (DstSize > 32) {
1715 unsigned ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
1715 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
17161716 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
17171717 .addDef(ExtSrc)
17181718 .addImm(0)
17291729 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
17301730 SrcTy = MRI.getType(I.getOperand(1).getReg());
17311731 const bool isSigned = Opcode == TargetOpcode::G_SEXT;
1732 const unsigned DefReg = I.getOperand(0).getReg();
1733 const unsigned SrcReg = I.getOperand(1).getReg();
1732 const Register DefReg = I.getOperand(0).getReg();
1733 const Register SrcReg = I.getOperand(1).getReg();
17341734 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
17351735
17361736 if (RB.getID() != AArch64::GPRRegBankID) {
17481748 return false;
17491749 }
17501750
1751 const unsigned SrcXReg =
1751 const Register SrcXReg =
17521752 MRI.createVirtualRegister(&AArch64::GPR64RegClass);
17531753 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
17541754 .addDef(SrcXReg)
18161816 return false;
18171817 }
18181818
1819 const unsigned CondReg = I.getOperand(1).getReg();
1820 const unsigned TReg = I.getOperand(2).getReg();
1821 const unsigned FReg = I.getOperand(3).getReg();
1819 const Register CondReg = I.getOperand(1).getReg();
1820 const Register TReg = I.getOperand(2).getReg();
1821 const Register FReg = I.getOperand(3).getReg();
18221822
18231823 // If we have a floating-point result, then we should use a floating point
18241824 // select instead of an integer select.
18281828 if (IsFP && tryOptSelect(I))
18291829 return true;
18301830
1831 unsigned CSelOpc = selectSelectOpc(I, MRI, RBI);
1831 Register CSelOpc = selectSelectOpc(I, MRI, RBI);
18321832 MachineInstr &TstMI =
18331833 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
18341834 .addDef(AArch64::WZR)
18581858 }
18591859
18601860 unsigned CmpOpc = 0;
1861 unsigned ZReg = 0;
1861 Register ZReg;
18621862
18631863 // Check if this compare can be represented as a cmn, and perform any
18641864 // necessary transformations to do so.
19291929 if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
19301930 CmpMI = CmpMI.addUse(I.getOperand(3).getReg());
19311931
1932 const unsigned DefReg = I.getOperand(0).getReg();
1933 unsigned Def1Reg = DefReg;
1932 const Register DefReg = I.getOperand(0).getReg();
1933 Register Def1Reg = DefReg;
19341934 if (CC2 != AArch64CC::AL)
19351935 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
19361936
19421942 .addImm(getInvertedCondCode(CC1));
19431943
19441944 if (CC2 != AArch64CC::AL) {
1945 unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1945 Register Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
19461946 MachineInstr &CSet2MI =
19471947 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
19481948 .addDef(Def2Reg)
19731973 case TargetOpcode::G_IMPLICIT_DEF: {
19741974 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
19751975 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1976 const unsigned DstReg = I.getOperand(0).getReg();
1976 const Register DstReg = I.getOperand(0).getReg();
19771977 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
19781978 const TargetRegisterClass *DstRC =
19791979 getRegClassForTypeOnBank(DstTy, DstRB, RBI);
20262026 bool AArch64InstructionSelector::selectBrJT(MachineInstr &I,
20272027 MachineRegisterInfo &MRI) const {
20282028 assert(I.getOpcode() == TargetOpcode::G_BRJT && "Expected G_BRJT");
2029 unsigned JTAddr = I.getOperand(0).getReg();
2029 Register JTAddr = I.getOperand(0).getReg();
20302030 unsigned JTI = I.getOperand(1).getIndex();
2031 unsigned Index = I.getOperand(2).getReg();
2031 Register Index = I.getOperand(2).getReg();
20322032 MachineIRBuilder MIB(I);
20332033
2034 unsigned TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2035 unsigned ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
2034 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2035 Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
20362036 MIB.buildInstr(AArch64::JumpTableDest32, {TargetReg, ScratchReg},
20372037 {JTAddr, Index})
20382038 .addJumpTableIndex(JTI);
20482048 assert(I.getOpcode() == TargetOpcode::G_JUMP_TABLE && "Expected jump table");
20492049 assert(I.getOperand(1).isJTI() && "Jump table op should have a JTI!");
20502050
2051 unsigned DstReg = I.getOperand(0).getReg();
2051 Register DstReg = I.getOperand(0).getReg();
20522052 unsigned JTI = I.getOperand(1).getIndex();
20532053 // We generate a MOVaddrJT which will get expanded to an ADRP + ADD later.
20542054 MachineIRBuilder MIB(I);
21722172
21732173 bool AArch64InstructionSelector::selectVectorICmp(
21742174 MachineInstr &I, MachineRegisterInfo &MRI) const {
2175 unsigned DstReg = I.getOperand(0).getReg();
2175 Register DstReg = I.getOperand(0).getReg();
21762176 LLT DstTy = MRI.getType(DstReg);
2177 unsigned SrcReg = I.getOperand(2).getReg();
2178 unsigned Src2Reg = I.getOperand(3).getReg();
2177 Register SrcReg = I.getOperand(2).getReg();
2178 Register Src2Reg = I.getOperand(3).getReg();
21792179 LLT SrcTy = MRI.getType(SrcReg);
21802180
21812181 unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits();
23432343 }
23442344
23452345 MachineInstr *AArch64InstructionSelector::emitScalarToVector(
2346 unsigned EltSize, const TargetRegisterClass *DstRC, unsigned Scalar,
2346 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,
23472347 MachineIRBuilder &MIRBuilder) const {
23482348 auto Undef = MIRBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstRC}, {});
23492349
23862386 return false;
23872387
23882388 auto *DstRC = &AArch64::GPR64RegClass;
2389 unsigned SubToRegDef = MRI.createVirtualRegister(DstRC);
2389 Register SubToRegDef = MRI.createVirtualRegister(DstRC);
23902390 MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
23912391 TII.get(TargetOpcode::SUBREG_TO_REG))
23922392 .addDef(SubToRegDef)
23932393 .addImm(0)
23942394 .addUse(I.getOperand(1).getReg())
23952395 .addImm(AArch64::sub_32);
2396 unsigned SubToRegDef2 = MRI.createVirtualRegister(DstRC);
2396 Register SubToRegDef2 = MRI.createVirtualRegister(DstRC);
23972397 // Need to anyext the second scalar before we can use bfm
23982398 MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
23992399 TII.get(TargetOpcode::SUBREG_TO_REG))
24412441 }
24422442
24432443 MachineInstr *AArch64InstructionSelector::emitExtractVectorElt(
2444 Optional DstReg, const RegisterBank &DstRB, LLT ScalarTy,
2445 unsigned VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
2444 Optional DstReg, const RegisterBank &DstRB, LLT ScalarTy,
2445 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
24462446 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
24472447 unsigned CopyOpc = 0;
24482448 unsigned ExtractSubReg = 0;
24692469 }
24702470
24712471 // The register that we're going to copy into.
2472 unsigned InsertReg = VecReg;
2472 Register InsertReg = VecReg;
24732473 if (!DstReg)
24742474 DstReg = MRI.createVirtualRegister(DstRC);
24752475 // If the lane index is 0, we just use a subregister COPY.
25042504 MachineInstr &I, MachineRegisterInfo &MRI) const {
25052505 assert(I.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT &&
25062506 "unexpected opcode!");
2507 unsigned DstReg = I.getOperand(0).getReg();
2507 Register DstReg = I.getOperand(0).getReg();
25082508 const LLT NarrowTy = MRI.getType(DstReg);
2509 const unsigned SrcReg = I.getOperand(1).getReg();
2509 const Register SrcReg = I.getOperand(1).getReg();
25102510 const LLT WideTy = MRI.getType(SrcReg);
25112511 (void)WideTy;
25122512 assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() &&
25432543 bool AArch64InstructionSelector::selectSplitVectorUnmerge(
25442544 MachineInstr &I, MachineRegisterInfo &MRI) const {
25452545 unsigned NumElts = I.getNumOperands() - 1;
2546 unsigned SrcReg = I.getOperand(NumElts).getReg();
2546 Register SrcReg = I.getOperand(NumElts).getReg();
25472547 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
25482548 const LLT SrcTy = MRI.getType(SrcReg);
25492549
25602560 const RegisterBank &DstRB =
25612561 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
25622562 for (unsigned OpIdx = 0; OpIdx < NumElts; ++OpIdx) {
2563 unsigned Dst = I.getOperand(OpIdx).getReg();
2563 Register Dst = I.getOperand(OpIdx).getReg();
25642564 MachineInstr *Extract =
25652565 emitExtractVectorElt(Dst, DstRB, NarrowTy, SrcReg, OpIdx, MIB);
25662566 if (!Extract)
25882588 // The last operand is the vector source register, and every other operand is
25892589 // a register to unpack into.
25902590 unsigned NumElts = I.getNumOperands() - 1;
2591 unsigned SrcReg = I.getOperand(NumElts).getReg();
2591 Register SrcReg = I.getOperand(NumElts).getReg();
25922592 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
25932593 const LLT WideTy = MRI.getType(SrcReg);
25942594 (void)WideTy;
26122612 MachineBasicBlock &MBB = *I.getParent();
26132613
26142614 // Stores the registers we'll be copying from.
2615 SmallVector<unsigned, 4> InsertRegs;
2615 SmallVector<Register, 4> InsertRegs;
26162616
26172617 // We'll use the first register twice, so we only need NumElts-1 registers.
26182618 unsigned NumInsertRegs = NumElts - 1;
26212621 // directly. Otherwise, we need to do a bit of setup with some subregister
26222622 // inserts.
26232623 if (NarrowTy.getSizeInBits() * NumElts == 128) {
2624 InsertRegs = SmallVector<unsigned, 4>(NumInsertRegs, SrcReg);
2624 InsertRegs = SmallVector<Register, 4>(NumInsertRegs, SrcReg);
26252625 } else {
26262626 // No. We have to perform subregister inserts. For each insert, create an
26272627 // implicit def and a subregister insert, and save the register we create.
26282628 for (unsigned Idx = 0; Idx < NumInsertRegs; ++Idx) {
2629 unsigned ImpDefReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
2629 Register ImpDefReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
26302630 MachineInstr &ImpDefMI =
26312631 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
26322632 ImpDefReg);
26332633
26342634 // Now, create the subregister insert from SrcReg.
2635 unsigned InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
2635 Register InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
26362636 MachineInstr &InsMI =
26372637 *BuildMI(MBB, I, I.getDebugLoc(),
26382638 TII.get(TargetOpcode::INSERT_SUBREG), InsertReg)
26522652 // create the copies.
26532653 //
26542654 // Perform the first copy separately as a subregister copy.
2655 unsigned CopyTo = I.getOperand(0).getReg();
2655 Register CopyTo = I.getOperand(0).getReg();
26562656 auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {})
26572657 .addReg(InsertRegs[0], 0, ExtractSubReg);
26582658 constrainSelectedInstRegOperands(*FirstCopy, TII, TRI, RBI);
26592659
26602660 // Now, perform the remaining copies as vector lane copies.
26612661 unsigned LaneIdx = 1;
2662 for (unsigned InsReg : InsertRegs) {
2663 unsigned CopyTo = I.getOperand(LaneIdx).getReg();
2662 for (Register InsReg : InsertRegs) {
2663 Register CopyTo = I.getOperand(LaneIdx).getReg();
26642664 MachineInstr &CopyInst =
26652665 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CopyOpc), CopyTo)
26662666 .addUse(InsReg)
26882688 MachineInstr &I, MachineRegisterInfo &MRI) const {
26892689 assert(I.getOpcode() == TargetOpcode::G_CONCAT_VECTORS &&
26902690 "Unexpected opcode");
2691 unsigned Dst = I.getOperand(0).getReg();
2692 unsigned Op1 = I.getOperand(1).getReg();
2693 unsigned Op2 = I.getOperand(2).getReg();
2691 Register Dst = I.getOperand(0).getReg();
2692 Register Op1 = I.getOperand(1).getReg();
2693 Register Op2 = I.getOperand(2).getReg();
26942694 MachineIRBuilder MIRBuilder(I);
26952695 MachineInstr *ConcatMI = emitVectorConcat(Dst, Op1, Op2, MIRBuilder);
26962696 if (!ConcatMI)
28062806 }
28072807
28082808 MachineInstr *AArch64InstructionSelector::emitVectorConcat(
2809 Optional<unsigned> Dst, unsigned Op1, unsigned Op2,
2809 Optional<Register> Dst, Register Op1, Register Op2,
28102810 MachineIRBuilder &MIRBuilder) const {
28112811 // We implement a vector concat by:
28122812 // 1. Use scalar_to_vector to insert the lower vector into the larger dest
28992899 }
29002900
29012901 MachineInstr *
2902 AArch64InstructionSelector::emitCSetForICMP(unsigned DefReg, unsigned Pred,
2902 AArch64InstructionSelector::emitCSetForICMP(Register DefReg, unsigned Pred,
29032903 MachineIRBuilder &MIRBuilder) const {
29042904 // CSINC increments the result when the predicate is false. Invert it.
29052905 const AArch64CC::CondCode InvCC = changeICMPPredToAArch64CC(
29062906 CmpInst::getInversePredicate((CmpInst::Predicate)Pred));
29072907 auto I =
29082908 MIRBuilder
2909 .buildInstr(AArch64::CSINCWr, {DefReg}, {AArch64::WZR, AArch64::WZR})
2909 .buildInstr(AArch64::CSINCWr, {DefReg}, {Register(AArch64::WZR), Register(AArch64::WZR)})
29102910 .addImm(InvCC);
29112911 constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
29122912 return &*I;
30103010 // cmn z, y
30113011
30123012 // Helper lambda to find the def.
3013 auto FindDef = [&](unsigned VReg) {
3013 auto FindDef = [&](Register VReg) {
30143014 MachineInstr *Def = MRI.getVRegDef(VReg);
30153015 while (Def) {
30163016 if (Def->getOpcode() != TargetOpcode::COPY)
30903090 (MRI.getType(I.getOperand(2).getReg()).getSizeInBits() == 32);
30913091 auto ImmFns = selectArithImmed(I.getOperand(3));
30923092 unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
3093 unsigned ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
3093 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
30943094
30953095 auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {I.getOperand(2).getReg()});
30963096
31443144 if (!UndefMI)
31453145 return false;
31463146 // Match the scalar being splatted.
3147 unsigned ScalarReg = InsMI->getOperand(2).getReg();
3147 Register ScalarReg = InsMI->getOperand(2).getReg();
31483148 const RegisterBank *ScalarRB = RBI.getRegBank(ScalarReg, MRI, TRI);
31493149 // Match the index constant 0.
31503150 int64_t Index = 0;
32053205 if (tryOptVectorShuffle(I))
32063206 return true;
32073207 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3208 unsigned Src1Reg = I.getOperand(1).getReg();
3208 Register Src1Reg = I.getOperand(1).getReg();
32093209 const LLT Src1Ty = MRI.getType(Src1Reg);
3210 unsigned Src2Reg = I.getOperand(2).getReg();
3210 Register Src2Reg = I.getOperand(2).getReg();
32113211 const LLT Src2Ty = MRI.getType(Src2Reg);
32123212
32133213 MachineBasicBlock &MBB = *I.getParent();
33013301 }
33023302
33033303 MachineInstr *AArch64InstructionSelector::emitLaneInsert(
3304 Optional<unsigned> DstReg, unsigned SrcReg, unsigned EltReg,
3304 Optional<Register> DstReg, Register SrcReg, Register EltReg,
33053305 unsigned LaneIdx, const RegisterBank &RB,
33063306 MachineIRBuilder &MIRBuilder) const {
33073307 MachineInstr *InsElt = nullptr;
33363336 assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT);
33373337
33383338 // Get information on the destination.
3339 unsigned DstReg = I.getOperand(0).getReg();
3339 Register DstReg = I.getOperand(0).getReg();
33403340 const LLT DstTy = MRI.getType(DstReg);
33413341 unsigned VecSize = DstTy.getSizeInBits();
33423342
33433343 // Get information on the element we want to insert into the destination.
3344 unsigned EltReg = I.getOperand(2).getReg();
3344 Register EltReg = I.getOperand(2).getReg();
33453345 const LLT EltTy = MRI.getType(EltReg);
33463346 unsigned EltSize = EltTy.getSizeInBits();
33473347 if (EltSize < 16 || EltSize > 64)
33493349
33503350 // Find the definition of the index. Bail out if it's not defined by a
33513351 // G_CONSTANT.
3352 unsigned IdxReg = I.getOperand(3).getReg();
3352 Register IdxReg = I.getOperand(3).getReg();
33533353 auto VRegAndVal = getConstantVRegValWithLookThrough(IdxReg, MRI);
33543354 if (!VRegAndVal)
33553355 return false;
33563356 unsigned LaneIdx = VRegAndVal->Value;
33573357
33583358 // Perform the lane insert.
3359 unsigned SrcReg = I.getOperand(1).getReg();
3359 Register SrcReg = I.getOperand(1).getReg();
33603360 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
33613361 MachineIRBuilder MIRBuilder(I);
33623362
33793379 if (VecSize < 128) {
33803380 // If we had to widen to perform the insert, then we have to demote back to
33813381 // the original size to get the result we want.
3382 unsigned DemoteVec = InsMI->getOperand(0).getReg();
3382 Register DemoteVec = InsMI->getOperand(0).getReg();
33833383 const TargetRegisterClass *RC =
33843384 getMinClassForRegBank(*RBI.getRegBank(DemoteVec, MRI, TRI), VecSize);
33853385 if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
34273427 if (!ScalarToVec)
34283428 return false;
34293429
3430 unsigned DstVec = ScalarToVec->getOperand(0).getReg();
3430 Register DstVec = ScalarToVec->getOperand(0).getReg();
34313431 unsigned DstSize = DstTy.getSizeInBits();
34323432
34333433 // Keep track of the last MI we inserted. Later on, we might be able to save
34633463 return false;
34643464 }
34653465
3466 unsigned Reg = MRI.createVirtualRegister(RC);
3467 unsigned DstReg = I.getOperand(0).getReg();
3466 Register Reg = MRI.createVirtualRegister(RC);
3467 Register DstReg = I.getOperand(0).getReg();
34683468
34693469 MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
34703470 .addReg(DstVec, 0, SubReg);
35303530 MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000);
35313531 break;
35323532 case Intrinsic::aarch64_stlxr:
3533 unsigned StatReg = I.getOperand(0).getReg();
3533 Register StatReg = I.getOperand(0).getReg();
35343534 assert(RBI.getSizeInBits(StatReg, MRI, TRI) == 32 &&
35353535 "Status register must be 32 bits!");
3536 unsigned SrcReg = I.getOperand(2).getReg();
3536 Register SrcReg = I.getOperand(2).getReg();
35373537
35383538 if (RBI.getSizeInBits(SrcReg, MRI, TRI) != 64) {
35393539 LLVM_DEBUG(dbgs() << "Only support 64-bit sources right now.\n");
35403540 return false;
35413541 }
35423542
3543 unsigned PtrReg = I.getOperand(3).getReg();
3543 Register PtrReg = I.getOperand(3).getReg();
35443544 assert(MRI.getType(PtrReg).isPointer() && "Expected pointer operand");
35453545
35463546 // Expect only one memory operand.
35723572 default:
35733573 break;
35743574 case Intrinsic::aarch64_crypto_sha1h:
3575 unsigned DstReg = I.getOperand(0).getReg();
3576 unsigned SrcReg = I.getOperand(2).getReg();
3575 Register DstReg = I.getOperand(0).getReg();
3576 Register SrcReg = I.getOperand(2).getReg();
35773577
35783578 // FIXME: Should this be an assert?
35793579 if (MRI.getType(DstReg).getSizeInBits() != 32 ||
3636
3737 MachineInstrBuilder MIB;
3838
39 unsigned getStackAddress(uint64_t Size, int64_t Offset,
39 Register getStackAddress(uint64_t Size, int64_t Offset,
4040 MachinePointerInfo &MPO) override {
4141 llvm_unreachable("not implemented");
4242 }
4343
44 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
44 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
4545 MachinePointerInfo &MPO, CCValAssign &VA) override {
4646 llvm_unreachable("not implemented");
4747 }
4848
49 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
49 void assignValueToReg(Register ValVReg, Register PhysReg,
5050 CCValAssign &VA) override {
5151 MIB.addUse(PhysReg);
5252 MIRBuilder.buildCopy(PhysReg, ValVReg);
110110 return true;
111111 }
112112
113 unsigned AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
113 Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
114114 Type *ParamTy,
115115 uint64_t Offset) const {
116116
121121 const DataLayout &DL = F.getParent()->getDataLayout();
122122 PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUAS::CONSTANT_ADDRESS);
123123 LLT PtrType = getLLTForType(*PtrTy, DL);
124 unsigned DstReg = MRI.createGenericVirtualRegister(PtrType);
125 unsigned KernArgSegmentPtr =
124 Register DstReg = MRI.createGenericVirtualRegister(PtrType);
125 Register KernArgSegmentPtr =
126126 MFI->getPreloadedReg(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
127 unsigned KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
128
129 unsigned OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
127 Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
128
129 Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
130130 MIRBuilder.buildConstant(OffsetReg, Offset);
131131
132132 MIRBuilder.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
155155 MIRBuilder.buildLoad(DstReg, PtrReg, *MMO);
156156 }
157157
158 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
158 static Register findFirstFreeSGPR(CCState &CCInfo) {
159159 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
160160 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
161161 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
214214
215215 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
216216 if (Info->hasPrivateSegmentBuffer()) {
217 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
217 Register PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
218218 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
219219 CCInfo.AllocateReg(PrivateSegmentBufferReg);
220220 }
221221
222222 if (Info->hasDispatchPtr()) {
223 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
223 Register DispatchPtrReg = Info->addDispatchPtr(*TRI);
224224 // FIXME: Need to add reg as live-in
225225 CCInfo.AllocateReg(DispatchPtrReg);
226226 }
227227
228228 if (Info->hasQueuePtr()) {
229 unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
229 Register QueuePtrReg = Info->addQueuePtr(*TRI);
230230 // FIXME: Need to add reg as live-in
231231 CCInfo.AllocateReg(QueuePtrReg);
232232 }
233233
234234 if (Info->hasKernargSegmentPtr()) {
235 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
235 Register InputPtrReg = Info->addKernargSegmentPtr(*TRI);
236236 const LLT P2 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
237 unsigned VReg = MRI.createGenericVirtualRegister(P2);
237 Register VReg = MRI.createGenericVirtualRegister(P2);
238238 MRI.addLiveIn(InputPtrReg, VReg);
239239 MIRBuilder.getMBB().addLiveIn(InputPtrReg);
240240 MIRBuilder.buildCopy(VReg, InputPtrReg);
2121 class AMDGPUTargetLowering;
2222
2323 class AMDGPUCallLowering: public CallLowering {
24 unsigned lowerParameterPtr(MachineIRBuilder &MIRBuilder, Type *ParamTy,
24 Register lowerParameterPtr(MachineIRBuilder &MIRBuilder, Type *ParamTy,
2525 uint64_t Offset) const;
2626
2727 void lowerParameter(MachineIRBuilder &MIRBuilder, Type *ParamTy,
834834 auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
835835 auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);
836836
837 unsigned PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
837 Register PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
838838
839839 // Extract low 32-bits of the pointer.
840840 MIRBuilder.buildExtract(PtrLo32, Src, 0);
841841
842 unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
842 Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
843843 MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
844844 MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
845845
855855 auto FlatNull =
856856 MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
857857
858 unsigned ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
859
860 unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
858 Register ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
859
860 Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
861861 MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
862862
863 unsigned BuildPtr = MRI.createGenericVirtualRegister(DstTy);
863 Register BuildPtr = MRI.createGenericVirtualRegister(DstTy);
864864
865865 // Coerce the type of the low half of the result so we can use merge_values.
866 unsigned SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32));
866 Register SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32));
867867 MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
868868 .addDef(SrcAsInt)
869869 .addUse(Src);
882882 MachineIRBuilder &MIRBuilder) const {
883883 MIRBuilder.setInstr(MI);
884884
885 unsigned Src = MI.getOperand(1).getReg();
885 Register Src = MI.getOperand(1).getReg();
886886 LLT Ty = MRI.getType(Src);
887887 assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
888888
912912 const LLT S1 = LLT::scalar(1);
913913 const LLT S64 = LLT::scalar(64);
914914
915 unsigned Src = MI.getOperand(1).getReg();
915 Register Src = MI.getOperand(1).getReg();
916916 assert(MRI.getType(Src) == S64);
917917
918918 // result = trunc(src)
958958 const LLT S32 = LLT::scalar(32);
959959 const LLT S64 = LLT::scalar(64);
960960
961 unsigned Src = MI.getOperand(1).getReg();
961 Register Src = MI.getOperand(1).getReg();
962962 assert(MRI.getType(Src) == S64);
963963
964964 // TODO: Should this use extract since the low half is unused?
965965 auto Unmerge = B.buildUnmerge({S32, S32}, Src);
966 unsigned Hi = Unmerge.getReg(1);
966 Register Hi = Unmerge.getReg(1);
967967
968968 // Extract the upper half, since this is where we will find the sign and
969969 // exponent.
10001000 MachineIRBuilder &B, bool Signed) const {
10011001 B.setInstr(MI);
10021002
1003 unsigned Dst = MI.getOperand(0).getReg();
1004 unsigned Src = MI.getOperand(1).getReg();
1003 Register Dst = MI.getOperand(0).getReg();
1004 Register Src = MI.getOperand(1).getReg();
10051005
10061006 const LLT S64 = LLT::scalar(64);
10071007 const LLT S32 = LLT::scalar(32);
827827 }
828828 case AMDGPU::G_SEXT:
829829 case AMDGPU::G_ZEXT: {
830 unsigned SrcReg = MI.getOperand(1).getReg();
830 Register SrcReg = MI.getOperand(1).getReg();
831831 LLT SrcTy = MRI.getType(SrcReg);
832832 if (SrcTy != LLT::scalar(1))
833833 return;
834834
835835 MachineIRBuilder B(MI);
836836 bool Signed = Opc == AMDGPU::G_SEXT;
837 unsigned DstReg = MI.getOperand(0).getReg();
837 Register DstReg = MI.getOperand(0).getReg();
838838 LLT DstTy = MRI.getType(DstReg);
839839 const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
840840 if (SrcBank->getID() == AMDGPU::SCCRegBankID ||
8989 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
9090 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
9191
92 unsigned getStackAddress(uint64_t Size, int64_t Offset,
92 Register getStackAddress(uint64_t Size, int64_t Offset,
9393 MachinePointerInfo &MPO) override {
9494 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
9595 "Unsupported size");
9696
9797 LLT p0 = LLT::pointer(0, 32);
9898 LLT s32 = LLT::scalar(32);
99 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
100 MIRBuilder.buildCopy(SPReg, ARM::SP);
101
102 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32);
99 Register SPReg = MRI.createGenericVirtualRegister(p0);
100 MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
101
102 Register OffsetReg = MRI.createGenericVirtualRegister(s32);
103103 MIRBuilder.buildConstant(OffsetReg, Offset);
104104
105 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
105 Register AddrReg = MRI.createGenericVirtualRegister(p0);
106106 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
107107
108108 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
109109 return AddrReg;
110110 }
111111
112 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
112 void assignValueToReg(Register ValVReg, Register PhysReg,
113113 CCValAssign &VA) override {
114114 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
115115 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
117117 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
118118 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
119119
120 unsigned ExtReg = extendRegister(ValVReg, VA);
120 Register ExtReg = extendRegister(ValVReg, VA);
121121 MIRBuilder.buildCopy(PhysReg, ExtReg);
122122 MIB.addUse(PhysReg, RegState::Implicit);
123123 }
124124
125 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
125 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
126126 MachinePointerInfo &MPO, CCValAssign &VA) override {
127127 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
128128 "Unsupported size");
129129
130 unsigned ExtReg = extendRegister(ValVReg, VA);
130 Register ExtReg = extendRegister(ValVReg, VA);
131131 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
132132 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
133133 /* Alignment */ 1);
297297
298298 bool isArgumentHandler() const override { return true; }
299299
300 unsigned getStackAddress(uint64_t Size, int64_t Offset,
300 Register getStackAddress(uint64_t Size, int64_t Offset,
301301 MachinePointerInfo &MPO) override {
302302 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
303303 "Unsupported size");
314314 return AddrReg;
315315 }
316316
317 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
317 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
318318 MachinePointerInfo &MPO, CCValAssign &VA) override {
319319 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
320320 "Unsupported size");
335335 }
336336 }
337337
338 void buildLoad(unsigned Val, unsigned Addr, uint64_t Size, unsigned Alignment,
338 void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
339339 MachinePointerInfo &MPO) {
340340 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
341341 MPO, MachineMemOperand::MOLoad, Size, Alignment);
342342 MIRBuilder.buildLoad(Val, Addr, *MMO);
343343 }
344344
345 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
345 void assignValueToReg(Register ValVReg, Register PhysReg,
346346 CCValAssign &VA) override {
347347 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
348348 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
422422 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
423423 auto *RetTy = Type::getInt32Ty(Ctx);
424424
425 SmallVector<unsigned, 2> Results;
425 SmallVector<Register, 2> Results;
426426 for (auto Libcall : Libcalls) {
427427 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
428428 auto Status =
9292 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
9393 const EVT &VT) override;
9494
95 unsigned getStackAddress(const CCValAssign &VA,
95 Register getStackAddress(const CCValAssign &VA,
9696 MachineMemOperand *&MMO) override;
9797
9898 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
133133 const EVT &VT) {
134134 const MipsSubtarget &STI =
135135 static_cast(MIRBuilder.getMF().getSubtarget());
136 unsigned PhysReg = VA.getLocReg();
136 Register PhysReg = VA.getLocReg();
137137 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
138138 const MipsSubtarget &STI =
139139 static_cast(MIRBuilder.getMF().getSubtarget());
172172 }
173173 }
174174
175 unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
175 Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
176176 MachineMemOperand *&MMO) {
177177 MachineFunction &MF = MIRBuilder.getMF();
178178 unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
187187 unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
188188 MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
189189
190 unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
190 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
191191 MIRBuilder.buildFrameIndex(AddrReg, FI);
192192
193193 return AddrReg;
227227 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
228228 const EVT &VT) override;
229229
230 unsigned getStackAddress(const CCValAssign &VA,
230 Register getStackAddress(const CCValAssign &VA,
231231 MachineMemOperand *&MMO) override;
232232
233233 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
236236 ArrayRef ArgLocs, unsigned ArgLocsStartIndex,
237237 Register ArgsReg, const EVT &VT) override;
238238
239 unsigned extendRegister(Register ValReg, const CCValAssign &VA);
239 Register extendRegister(Register ValReg, const CCValAssign &VA);
240240
241241 MachineInstrBuilder &MIB;
242242 };
273273 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
274274 *STI.getRegBankInfo());
275275 } else {
276 unsigned ExtReg = extendRegister(ValVReg, VA);
276 Register ExtReg = extendRegister(ValVReg, VA);
277277 MIRBuilder.buildCopy(PhysReg, ExtReg);
278278 MIB.addUse(PhysReg, RegState::Implicit);
279279 }
280280 }
281281
282 unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
282 Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
283283 MachineMemOperand *&MMO) {
284284 MachineFunction &MF = MIRBuilder.getMF();
285285 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
287287 LLT p0 = LLT::pointer(0, 32);
288288 LLT s32 = LLT::scalar(32);
289289 Register SPReg = MRI.createGenericVirtualRegister(p0);
290 MIRBuilder.buildCopy(SPReg, Mips::SP);
290 MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
291291
292292 Register OffsetReg = MRI.createGenericVirtualRegister(s32);
293293 unsigned Offset = VA.getLocMemOffset();
309309 const CCValAssign &VA) {
310310 MachineMemOperand *MMO;
311311 Register Addr = getStackAddress(VA, MMO);
312 unsigned ExtReg = extendRegister(ValVReg, VA);
312 Register ExtReg = extendRegister(ValVReg, VA);
313313 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
314314 }
315315
316 unsigned OutgoingValueHandler::extendRegister(Register ValReg,
316 Register OutgoingValueHandler::extendRegister(Register ValReg,
317317 const CCValAssign &VA) {
318318 LLT LocTy{VA.getLocVT()};
319319 switch (VA.getLocInfo()) {
529529 Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
530530 MIB.addDef(Mips::SP, RegState::Implicit);
531531 if (IsCalleeGlobalPIC) {
532 unsigned CalleeReg =
532 Register CalleeReg =
533533 MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
534534 MachineInstr *CalleeGlobalValue =
535535 MIRBuilder.buildGlobalValue(CalleeReg, Callee.getGlobal());
582582
583583 if (IsCalleeGlobalPIC) {
584584 MIRBuilder.buildCopy(
585 Mips::GP,
586 MF.getInfo()->getGlobalBaseRegForGlobalISel());
585 Register(Mips::GP),
586 MF.getInfo()->getGlobalBaseRegForGlobalISel());
587587 MIB.addDef(Mips::GP, RegState::Implicit);
588588 }
589589 MIRBuilder.insertInstr(MIB);
4444 private:
4545 bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);
4646
47 virtual unsigned getStackAddress(const CCValAssign &VA,
47 virtual Register getStackAddress(const CCValAssign &VA,
4848 MachineMemOperand *&MMO) = 0;
4949
5050 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
3737
3838 private:
3939 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
40 bool materialize32BitImm(unsigned DestReg, APInt Imm,
40 bool materialize32BitImm(Register DestReg, APInt Imm,
4141 MachineIRBuilder &B) const;
4242 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
4343
7979
8080 bool MipsInstructionSelector::selectCopy(MachineInstr &I,
8181 MachineRegisterInfo &MRI) const {
82 unsigned DstReg = I.getOperand(0).getReg();
82 Register DstReg = I.getOperand(0).getReg();
8383 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
8484 return true;
8585
103103 return true;
104104 }
105105
106 bool MipsInstructionSelector::materialize32BitImm(unsigned DestReg, APInt Imm,
106 bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
107107 MachineIRBuilder &B) const {
108108 assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
109109 // Ori zero extends immediate. Used for values with zeros in high 16 bits.
110110 if (Imm.getHiBits(16).isNullValue()) {
111 MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Mips::ZERO})
111 MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
112112 .addImm(Imm.getLoBits(16).getLimitedValue());
113113 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
114114 }
120120 }
121121 // ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
122122 if (Imm.isSignedIntN(16)) {
123 MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Mips::ZERO})
123 MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
124124 .addImm(Imm.getLoBits(16).getLimitedValue());
125125 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
126126 }
127127 // Values that cannot be materialized with single immediate instruction.
128 unsigned LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
128 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
129129 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
130130 .addImm(Imm.getHiBits(16).getLimitedValue());
131131 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
200200
201201 switch (I.getOpcode()) {
202202 case G_UMULH: {
203 unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
203 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
204204 MachineInstr *PseudoMULTu, *PseudoMove;
205205
206206 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
241241 break;
242242 }
243243 case G_PHI: {
244 const unsigned DestReg = I.getOperand(0).getReg();
244 const Register DestReg = I.getOperand(0).getReg();
245245 const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
246246 const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
247247
256256 case G_LOAD:
257257 case G_ZEXTLOAD:
258258 case G_SEXTLOAD: {
259 const unsigned DestReg = I.getOperand(0).getReg();
259 const Register DestReg = I.getOperand(0).getReg();
260260 const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
261261 const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
262262 const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
280280 case G_UREM:
281281 case G_SDIV:
282282 case G_SREM: {
283 unsigned HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
283 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
284284 bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
285285 bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
286286
327327 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
328328
329329 if (Size == 32) {
330 unsigned GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
330 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
331331 MachineIRBuilder B(I);
332332 if (!materialize32BitImm(GPRReg, APImm, B))
333333 return false;
338338 return false;
339339 }
340340 if (Size == 64) {
341 unsigned GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
342 unsigned GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
341 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
342 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
343343 MachineIRBuilder B(I);
344344 if (!materialize32BitImm(GPRRegHigh, APImm.getHiBits(32).trunc(32), B))
345345 return false;
418418 return false;
419419
420420 if (GVal->hasLocalLinkage()) {
421 unsigned LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
421 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
422422 LWGOT->getOperand(0).setReg(LWGOTDef);
423423
424424 MachineInstr *ADDiu =
431431 return false;
432432 }
433433 } else {
434 unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
434 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
435435
436436 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
437437 .addDef(LUiReg)
454454 }
455455 case G_ICMP: {
456456 struct Instr {
457 unsigned Opcode, Def, LHS, RHS;
458 Instr(unsigned Opcode, unsigned Def, unsigned LHS, unsigned RHS)
457 unsigned Opcode;
458 Register Def, LHS, RHS;
459 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
459460 : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
460461
461462 bool hasImm() const {
466467 };
467468
468469 SmallVector Instructions;
469 unsigned ICMPReg = I.getOperand(0).getReg();
470 unsigned Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
471 unsigned LHS = I.getOperand(2).getReg();
472 unsigned RHS = I.getOperand(3).getReg();
470 Register ICMPReg = I.getOperand(0).getReg();
471 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
472 Register LHS = I.getOperand(2).getReg();
473 Register RHS = I.getOperand(3).getReg();
473474 CmpInst::Predicate Cond =
474475 static_cast(I.getOperand(1).getPredicate());
475476
4343 return Mips::GPR32RegClass;
4444 }
4545
46 unsigned MipsFunctionInfo::getGlobalBaseReg() {
46 Register MipsFunctionInfo::getGlobalBaseReg() {
4747 if (!GlobalBaseReg)
4848 GlobalBaseReg =
4949 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF));
5050 return GlobalBaseReg;
5151 }
5252
53 unsigned MipsFunctionInfo::getGlobalBaseRegForGlobalISel() {
53 Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel() {
5454 if (!GlobalBaseReg) {
5555 getGlobalBaseReg();
5656 initGlobalBaseReg();
3131 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
3232
3333 bool globalBaseRegSet() const;
34 unsigned getGlobalBaseReg();
35 unsigned getGlobalBaseRegForGlobalISel();
34 Register getGlobalBaseReg();
35 Register getGlobalBaseRegForGlobalISel();
3636
3737 // Insert instructions to initialize the global base register in the
3838 // first MBB of the function.
100100 DL(MIRBuilder.getMF().getDataLayout()),
101101 STI(MIRBuilder.getMF().getSubtarget()) {}
102102
103 unsigned getStackAddress(uint64_t Size, int64_t Offset,
103 Register getStackAddress(uint64_t Size, int64_t Offset,
104104 MachinePointerInfo &MPO) override {
105105 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
106106 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
107 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
107 Register SPReg = MRI.createGenericVirtualRegister(p0);
108108 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
109109
110 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
110 Register OffsetReg = MRI.createGenericVirtualRegister(SType);
111111 MIRBuilder.buildConstant(OffsetReg, Offset);
112112
113 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
113 Register AddrReg = MRI.createGenericVirtualRegister(p0);
114114 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
115115
116116 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
117117 return AddrReg;
118118 }
119119
120 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
120 void assignValueToReg(Register ValVReg, Register PhysReg,
121121 CCValAssign &VA) override {
122122 MIB.addUse(PhysReg, RegState::Implicit);
123123
124 unsigned ExtReg;
124 Register ExtReg;
125125 // If we are copying the value to a physical register with the
126126 // size larger than the size of the value itself - build AnyExt
127127 // to the size of the register first and only then do the copy.
142142 MIRBuilder.buildCopy(PhysReg, ExtReg);
143143 }
144144
145 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
145 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
146146 MachinePointerInfo &MPO, CCValAssign &VA) override {
147 unsigned ExtReg = extendRegister(ValVReg, VA);
147 Register ExtReg = extendRegister(ValVReg, VA);
148148 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
149149 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
150150 /* Alignment */ 1);
229229
230230 bool isArgumentHandler() const override { return true; }
231231
232 unsigned getStackAddress(uint64_t Size, int64_t Offset,
232 Register getStackAddress(uint64_t Size, int64_t Offset,
233233 MachinePointerInfo &MPO) override {
234234 auto &MFI = MIRBuilder.getMF().getFrameInfo();
235235 int FI = MFI.CreateFixedObject(Size, Offset, true);
241241 return AddrReg;
242242 }
243243
244 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
244 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
245245 MachinePointerInfo &MPO, CCValAssign &VA) override {
246246 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
247247 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
249249 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
250250 }
251251
252 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
252 void assignValueToReg(Register ValVReg, Register PhysReg,
253253 CCValAssign &VA) override {
254254 markPhysRegUsed(PhysReg);
255255
135135 Register getFrameRegister(const MachineFunction &MF) const override;
136136 unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
137137 unsigned getPtrSizedStackRegister(const MachineFunction &MF) const;
138 unsigned getStackRegister() const { return StackPtr; }
139 unsigned getBaseRegister() const { return BasePtr; }
138 Register getStackRegister() const { return StackPtr; }
139 Register getBaseRegister() const { return BasePtr; }
140140 /// Returns physical register used as frame pointer.
141141 /// This will always returns the frame pointer register, contrary to
142142 /// getFrameRegister() which returns the "base pointer" in situations
143143 /// involving a stack, frame and base pointer.
144 unsigned getFramePtr() const { return FramePtr; }
144 Register getFramePtr() const { return FramePtr; }
145145 // FIXME: Move to FrameInfok
146146 unsigned getSlotSize() const { return SlotSize; }
147147 };
110110 return MF;
111111 }
112112
113 static void collectCopies(SmallVectorImpl<unsigned> &Copies,
113 static void collectCopies(SmallVectorImpl<Register> &Copies,
114114 MachineFunction *MF) {
115115 for (auto &MBB : *MF)
116116 for (MachineInstr &MI : MBB) {
127127 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
128128 MachineFunction *MF =
129129 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
130 SmallVector<unsigned, 4> Copies;
130 SmallVector<Register, 4> Copies;
131131 collectCopies(Copies, MF);
132132 MachineBasicBlock *EntryMBB = &*MF->begin();
133133 MachineIRBuilder B(*MF);
148148 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
149149 MachineFunction *MF =
150150 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
151 SmallVector<unsigned, 4> Copies;
151 SmallVector<Register, 4> Copies;
152152 collectCopies(Copies, MF);
153153 MachineBasicBlock *EntryMBB = &*MF->begin();
154154 MachineIRBuilder B(*MF);
275275 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
276276 MachineFunction *MF =
277277 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
278 SmallVector<unsigned, 4> Copies;
278 SmallVector<Register, 4> Copies;
279279 collectCopies(Copies, MF);
280280 MachineBasicBlock *EntryMBB = &*MF->begin();
281281 MachineIRBuilder B(*MF);
346346 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
347347 MachineFunction *MF =
348348 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
349 SmallVector<unsigned, 4> Copies;
349 SmallVector<Register, 4> Copies;
350350 collectCopies(Copies, MF);
351351 MachineBasicBlock *EntryMBB = &*MF->begin();
352352 MachineIRBuilder B(*MF);
402402 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
403403 MachineFunction *MF =
404404 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
405 SmallVector<unsigned, 4> Copies;
405 SmallVector<Register, 4> Copies;
406406 collectCopies(Copies, MF);
407407 MachineBasicBlock *EntryMBB = &*MF->begin();
408408 MachineIRBuilder B(*MF);
449449 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
450450 MachineFunction *MF =
451451 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
452 SmallVector<unsigned, 4> Copies;
452 SmallVector<Register, 4> Copies;
453453 collectCopies(Copies, MF);
454454 MachineBasicBlock *EntryMBB = &*MF->begin();
455455 MachineIRBuilder B(*MF);
492492 auto ModuleMMIPair = createDummyModule(Context, *TM, "");
493493 MachineFunction *MF =
494494 getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
495 SmallVector<unsigned, 4> Copies;
495 SmallVector<Register, 4> Copies;
496496 collectCopies(Copies, MF);
497497 MachineBasicBlock *EntryMBB = &*MF->begin();
498498 MachineIRBuilder B(*MF);