llvm.org GIT mirror llvm / a362682
PrologEpilogInserter: Rewrite API to determine callee save regsiters. This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242165 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 5 years ago
29 changed file(s) with 247 addition(s) and 153 deletion(s). Raw diff Collapse all Expand all
646646 /// deleted during LiveDebugVariables analysis.
647647 void markUsesInDebugValueAsUndef(unsigned Reg) const;
648648
649 /// Return true if the specified register is modified in this function.
650 /// This checks that no defining machine operands exist for the register or
651 /// any of its aliases. Definitions found on functions marked noreturn are
652 /// ignored.
653 bool isPhysRegModified(unsigned PhysReg) const;
654
649655 //===--------------------------------------------------------------------===//
650656 // Physical Register Use Info
651657 //===--------------------------------------------------------------------===//
654660 /// function. Also check for clobbered aliases and registers clobbered by
655661 /// function calls with register mask operands.
656662 ///
657 /// This only works after register allocation. It is primarily used by
658 /// PrologEpilogInserter to determine which callee-saved registers need
659 /// spilling.
663 /// This only works after register allocation.
660664 bool isPhysRegUsed(unsigned Reg) const {
661665 if (UsedPhysRegMask.test(Reg))
662666 return true;
1818 #include
1919
2020 namespace llvm {
21 class BitVector;
2122 class CalleeSavedInfo;
2223 class MachineFunction;
2324 class RegScavenger;
225226 return 0;
226227 }
227228
228 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
229 /// before PrologEpilogInserter scans the physical registers used to determine
230 /// what callee saved registers should be spilled. This method is optional.
231 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
232 RegScavenger *RS = nullptr) const {
233
234 }
229 /// This method determines which of the registers reported by
230 /// TargetRegisterInfo::getCalleeSavedRegs() should actually get saved.
231 /// The default implementation checks populates the \p SavedRegs bitset with
232 /// all registers which are modified in the function, targets may override
233 /// this function to save additional registers.
234 /// This method also sets up the register scavenger ensuring there is a free
235 /// register or a frameindex available.
236 virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
237 RegScavenger *RS = nullptr) const;
235238
236239 /// processFunctionBeforeFrameFinalized - This method is called immediately
237240 /// before the specified function's frame layout (MF.getFrameInfo()) is
1212
1313 #include "llvm/CodeGen/MachineRegisterInfo.h"
1414 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/IR/Function.h"
1516 #include "llvm/Support/raw_os_ostream.h"
1617 #include "llvm/Target/TargetInstrInfo.h"
1718 #include "llvm/Target/TargetMachine.h"
440441 UseMI->getOperand(0).setReg(0U);
441442 }
442443 }
444
445 static const Function *getCalledFunction(const MachineInstr &MI) {
446 for (const MachineOperand &MO : MI.operands()) {
447 if (!MO.isGlobal())
448 continue;
449 const Function *Func = dyn_cast(MO.getGlobal());
450 if (Func != nullptr)
451 return Func;
452 }
453 return nullptr;
454 }
455
456 static bool isNoReturnDef(const MachineOperand &MO) {
457 // Anything which is not a noreturn function is a real def.
458 const MachineInstr &MI = *MO.getParent();
459 if (!MI.isCall())
460 return false;
461 const MachineBasicBlock &MBB = *MI.getParent();
462 if (!MBB.succ_empty())
463 return false;
464 const MachineFunction &MF = *MBB.getParent();
465 // We need to keep correct unwind information even if the function will
466 // not return, since the runtime may need it.
467 if (MF.getFunction()->hasFnAttribute(Attribute::UWTable))
468 return false;
469 const Function *Called = getCalledFunction(MI);
470 if (Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn)
471 || !Called->hasFnAttribute(Attribute::NoUnwind))
472 return false;
473
474 return true;
475 }
476
477 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg) const {
478 if (UsedPhysRegMask.test(PhysReg))
479 return true;
480 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
481 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
482 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
483 if (isNoReturnDef(MO))
484 continue;
485 return true;
486 }
487 }
488 return false;
489 }
8181
8282 void calculateSets(MachineFunction &Fn);
8383 void calculateCallsInformation(MachineFunction &Fn);
84 void calculateCalleeSavedRegisters(MachineFunction &Fn);
84 void assignCalleeSavedSpillSlots(MachineFunction &Fn,
85 const BitVector &SavedRegs);
8586 void insertCSRSpillsAndRestores(MachineFunction &Fn);
8687 void calculateFrameObjectOffsets(MachineFunction &Fn);
8788 void replaceFrameIndices(MachineFunction &Fn);
182183 // instructions.
183184 calculateCallsInformation(Fn);
184185
185 // Allow the target machine to make some adjustments to the function
186 // e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
187 TFI->processFunctionBeforeCalleeSavedScan(Fn, RS);
188
189 // Scan the function for modified callee saved registers and insert spill code
190 // for any callee saved registers that are modified.
191 calculateCalleeSavedRegisters(Fn);
186 // Determine which of the registers in the callee save list should be saved.
187 BitVector SavedRegs;
188 TFI->determineCalleeSaves(Fn, SavedRegs, RS);
189
190 // Insert spill code for any callee saved registers that are modified.
191 assignCalleeSavedSpillSlots(Fn, SavedRegs);
192192
193193 // Determine placement of CSR spill/restore code:
194194 // place all spills in the entry block, all restores in return blocks.
294294 }
295295 }
296296
297
298 /// calculateCalleeSavedRegisters - Scan the function for modified callee saved
299 /// registers.
300 void PEI::calculateCalleeSavedRegisters(MachineFunction &F) {
301 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
302 const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering();
303 MachineFrameInfo *MFI = F.getFrameInfo();
304
305 // Get the callee saved register list...
306 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
307
297 void PEI::assignCalleeSavedSpillSlots(MachineFunction &F,
298 const BitVector &SavedRegs) {
308299 // These are used to keep track the callee-save area. Initialize them.
309300 MinCSFrameIndex = INT_MAX;
310301 MaxCSFrameIndex = 0;
311302
312 // Early exit for targets which have no callee saved registers.
313 if (!CSRegs || CSRegs[0] == 0)
303 if (SavedRegs.empty())
314304 return;
315305
316 // In Naked functions we aren't going to save any registers.
317 if (F.getFunction()->hasFnAttribute(Attribute::Naked))
318 return;
306 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
307 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
319308
320309 std::vector CSI;
321310 for (unsigned i = 0; CSRegs[i]; ++i) {
322311 unsigned Reg = CSRegs[i];
323 // Functions which call __builtin_unwind_init get all their registers saved.
324 if (F.getRegInfo().isPhysRegUsed(Reg) || F.getMMI().callsUnwindInit()) {
325 // If the reg is modified, save it!
312 if (SavedRegs.test(Reg))
326313 CSI.push_back(CalleeSavedInfo(Reg));
327 }
328 }
329
314 }
315
316 const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering();
317 MachineFrameInfo *MFI = F.getFrameInfo();
330318 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) {
331319 // If target doesn't implement this, use generic code.
332320
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "llvm/ADT/BitVector.h"
1314 #include "llvm/Target/TargetFrameLowering.h"
1415 #include "llvm/CodeGen/MachineFrameInfo.h"
1516 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineModuleInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
1619 #include "llvm/IR/Function.h"
1720 #include "llvm/Target/TargetRegisterInfo.h"
1821 #include "llvm/Target/TargetSubtargetInfo.h"
5356 const MachineFunction &MF) const {
5457 return MF.getFrameInfo()->hasStackObjects();
5558 }
59
60 void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
61 BitVector &SavedRegs,
62 RegScavenger *RS) const {
63 // Get the callee saved register list...
64 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
65 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
66
67 // Early exit if there are no callee saved registers.
68 if (!CSRegs || CSRegs[0] == 0)
69 return;
70
71 SavedRegs.resize(TRI.getNumRegs());
72
73 // In Naked functions we aren't going to save any registers.
74 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
75 return;
76
77 // Functions which call __builtin_unwind_init get all their registers saved.
78 bool CallsUnwindInit = MF.getMMI().callsUnwindInit();
79 const MachineRegisterInfo &MRI = MF.getRegInfo();
80 for (unsigned i = 0; CSRegs[i]; ++i) {
81 unsigned Reg = CSRegs[i];
82 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
83 SavedRegs.set(Reg);
84 }
85 }
876876 return true;
877877 }
878878
879 void AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(
880 MachineFunction &MF, RegScavenger *RS) const {
879 void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
880 BitVector &SavedRegs,
881 RegScavenger *RS) const {
882 // All calls are tail calls in GHC calling conv, and functions have no
883 // prologue/epilogue.
884 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
885 return;
886
887 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
881888 const AArch64RegisterInfo *RegInfo = static_cast(
882889 MF.getSubtarget().getRegisterInfo());
883890 AArch64FunctionInfo *AFI = MF.getInfo();
884 MachineRegisterInfo *MRI = &MF.getRegInfo();
885891 SmallVector UnspilledCSGPRs;
886892 SmallVector UnspilledCSFPRs;
887893
888894 // The frame record needs to be created by saving the appropriate registers
889895 if (hasFP(MF)) {
890 MRI->setPhysRegUsed(AArch64::FP);
891 MRI->setPhysRegUsed(AArch64::LR);
896 SavedRegs.set(AArch64::FP);
897 SavedRegs.set(AArch64::LR);
892898 }
893899
894900 // Spill the BasePtr if it's used. Do this first thing so that the
895901 // getCalleeSavedRegs() below will get the right answer.
896902 if (RegInfo->hasBasePointer(MF))
897 MRI->setPhysRegUsed(RegInfo->getBaseRegister());
903 SavedRegs.set(RegInfo->getBaseRegister());
898904
899905 if (RegInfo->needsStackRealignment(MF) && !RegInfo->hasBasePointer(MF))
900 MRI->setPhysRegUsed(AArch64::X9);
906 SavedRegs.set(AArch64::X9);
901907
902908 // If any callee-saved registers are used, the frame cannot be eliminated.
903909 unsigned NumGPRSpilled = 0;
919925 AArch64::FPR64RegClass.contains(EvenReg)) &&
920926 "Register class mismatch!");
921927
922 const bool OddRegUsed = MRI->isPhysRegUsed(OddReg);
923 const bool EvenRegUsed = MRI->isPhysRegUsed(EvenReg);
928 const bool OddRegUsed = SavedRegs.test(OddReg);
929 const bool EvenRegUsed = SavedRegs.test(EvenReg);
924930
925931 // Early exit if none of the registers in the register pair is actually
926932 // used.
941947 if (OddRegUsed ^ EvenRegUsed) {
942948 // Find out which register is the additional spill.
943949 Reg = OddRegUsed ? EvenReg : OddReg;
944 MRI->setPhysRegUsed(Reg);
950 SavedRegs.set(Reg);
945951 }
946952
947953 DEBUG(dbgs() << ' ' << PrintReg(OddReg, RegInfo));
9961002 UnspilledCSGPRs.pop_back();
9971003 DEBUG(dbgs() << "Spilling " << PrintReg(Reg, RegInfo)
9981004 << " to get a scratch register.\n");
999 MRI->setPhysRegUsed(Reg);
1005 SavedRegs.set(Reg);
10001006 ExtraCSSpill = true;
10011007 ++Count;
10021008 }
5858 bool hasFP(const MachineFunction &MF) const override;
5959 bool hasReservedCallFrame(const MachineFunction &MF) const override;
6060
61 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
62 RegScavenger *RS) const override;
61 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
62 RegScavenger *RS) const override;
6363 };
6464
6565 } // End llvm namespace
799799 // This is bad, if an interrupt is taken after the mov, sp is in an
800800 // inconsistent state.
801801 // Use the first callee-saved register as a scratch register.
802 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
802 assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&
803803 "No scratch register to restore SP from FP!");
804804 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
805805 ARMCC::AL, 0, TII);
14691469 // callee-saved vector registers after realigning the stack. The vst1 and vld1
14701470 // instructions take alignment hints that can improve performance.
14711471 //
1472 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1472 static void
1473 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
14731474 MF.getInfo()->setNumAlignedDPRCS2Regs(0);
14741475 if (!SpillAlignedNEONRegs)
14751476 return;
14961497 // callee-saved registers in order, but it can happen that there are holes in
14971498 // the range. Registers above the hole will be spilled to the standard DPRCS
14981499 // area.
1499 MachineRegisterInfo &MRI = MF.getRegInfo();
15001500 unsigned NumSpills = 0;
15011501 for (; NumSpills < 8; ++NumSpills)
1502 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1502 if (!SavedRegs.test(ARM::D8 + NumSpills))
15031503 break;
15041504
15051505 // Don't do this for just one d-register. It's not worth it.
15101510 MF.getInfo()->setNumAlignedDPRCS2Regs(NumSpills);
15111511
15121512 // A scratch register is required for the vst1 / vld1 instructions.
1513 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1514 }
1515
1516 void
1517 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1518 RegScavenger *RS) const {
1513 SavedRegs.set(ARM::R4);
1514 }
1515
1516 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1517 BitVector &SavedRegs,
1518 RegScavenger *RS) const {
1519 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
15191520 // This tells PEI to spill the FP as if it is any other callee-save register
15201521 // to take advantage the eliminateFrameIndex machinery. This also ensures it
15211522 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
15421543 // FIXME: It will be better just to find spare register here.
15431544 if (AFI->isThumb2Function() &&
15441545 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1545 MRI.setPhysRegUsed(ARM::R4);
1546 SavedRegs.set(ARM::R4);
15461547
15471548 if (AFI->isThumb1OnlyFunction()) {
15481549 // Spill LR if Thumb1 function uses variable length argument lists.
15491550 if (AFI->getArgRegsSaveSize() > 0)
1550 MRI.setPhysRegUsed(ARM::LR);
1551 SavedRegs.set(ARM::LR);
15511552
15521553 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
15531554 // for sure what the stack size will be, but for this, an estimate is good
15571558 // FIXME: It will be better just to find spare register here.
15581559 unsigned StackSize = MFI->estimateStackSize(MF);
15591560 if (MFI->hasVarSizedObjects() || StackSize > 508)
1560 MRI.setPhysRegUsed(ARM::R4);
1561 SavedRegs.set(ARM::R4);
15611562 }
15621563
15631564 // See if we can spill vector registers to aligned stack.
1564 checkNumAlignedDPRCS2Regs(MF);
1565 checkNumAlignedDPRCS2Regs(MF, SavedRegs);
15651566
15661567 // Spill the BasePtr if it's used.
15671568 if (RegInfo->hasBasePointer(MF))
1568 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1569 SavedRegs.set(RegInfo->getBaseRegister());
15691570
15701571 // Don't spill FP if the frame can be eliminated. This is determined
1571 // by scanning the callee-save registers to see if any is used.
1572 // by scanning the callee-save registers to see if any is modified.
15721573 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
15731574 for (unsigned i = 0; CSRegs[i]; ++i) {
15741575 unsigned Reg = CSRegs[i];
15751576 bool Spilled = false;
1576 if (MRI.isPhysRegUsed(Reg)) {
1577 if (SavedRegs.test(Reg)) {
15771578 Spilled = true;
15781579 CanEliminateFrame = false;
15791580 }
16671668 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
16681669 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
16691670 if (!LRSpilled && CS1Spilled) {
1670 MRI.setPhysRegUsed(ARM::LR);
1671 SavedRegs.set(ARM::LR);
16711672 NumGPRSpills++;
16721673 SmallVectorImpl::iterator LRPos;
16731674 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
16801681 }
16811682
16821683 if (hasFP(MF)) {
1683 MRI.setPhysRegUsed(FramePtr);
1684 SavedRegs.set(FramePtr);
16841685 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
16851686 FramePtr);
16861687 if (FPPos != UnspilledCS1GPRs.end())
16991700 // Don't spill high register if the function is thumb
17001701 if (!AFI->isThumbFunction() ||
17011702 isARMLowRegister(Reg) || Reg == ARM::LR) {
1702 MRI.setPhysRegUsed(Reg);
1703 SavedRegs.set(Reg);
17031704 if (!MRI.isReserved(Reg))
17041705 ExtraCSSpill = true;
17051706 break;
17071708 }
17081709 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
17091710 unsigned Reg = UnspilledCS2GPRs.front();
1710 MRI.setPhysRegUsed(Reg);
1711 SavedRegs.set(Reg);
17111712 if (!MRI.isReserved(Reg))
17121713 ExtraCSSpill = true;
17131714 }
17461747 }
17471748 if (Extras.size() && NumExtras == 0) {
17481749 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1749 MRI.setPhysRegUsed(Extras[i]);
1750 SavedRegs.set(Extras[i]);
17501751 }
17511752 } else if (!AFI->isThumb1OnlyFunction()) {
17521753 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
17601761 }
17611762
17621763 if (ForceLRSpill) {
1763 MRI.setPhysRegUsed(ARM::LR);
1764 SavedRegs.set(ARM::LR);
17641765 AFI->setLRIsSpilledForFarJump(true);
17651766 }
17661767 }
5353 unsigned &FrameReg, int SPAdj) const;
5454 int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
5555
56 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
57 RegScavenger *RS) const override;
56 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
57 RegScavenger *RS) const override;
5858
5959 void adjustForSegmentedStacks(MachineFunction &MF,
6060 MachineBasicBlock &MBB) const override;
364364 // frame pointer stack slot, the target is ELF and the function has FP, or
365365 // the target uses var sized objects.
366366 if (NumBytes) {
367 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
367 assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&
368368 "No scratch register to restore SP from FP!");
369369 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
370370 TII, *RegInfo);
2828 void BPFFrameLowering::emitEpilogue(MachineFunction &MF,
2929 MachineBasicBlock &MBB) const {}
3030
31 void BPFFrameLowering::processFunctionBeforeCalleeSavedScan(
32 MachineFunction &MF, RegScavenger *RS) const {
33 MachineRegisterInfo &MRI = MF.getRegInfo();
34
35 MRI.setPhysRegUnused(BPF::R6);
36 MRI.setPhysRegUnused(BPF::R7);
37 MRI.setPhysRegUnused(BPF::R8);
38 MRI.setPhysRegUnused(BPF::R9);
31 void BPFFrameLowering::determineCalleeSaves(MachineFunction &MF,
32 BitVector &SavedRegs,
33 RegScavenger *RS) const {
34 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
35 SavedRegs.reset(BPF::R6);
36 SavedRegs.reset(BPF::R7);
37 SavedRegs.reset(BPF::R8);
38 SavedRegs.reset(BPF::R9);
3939 }
2727 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
2828
2929 bool hasFP(const MachineFunction &MF) const override;
30 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
31 RegScavenger *RS) const override;
30 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
31 RegScavenger *RS) const override;
3232
3333 void
3434 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
958958 }
959959
960960
961 void HexagonFrameLowering::processFunctionBeforeCalleeSavedScan(
962 MachineFunction &MF, RegScavenger* RS) const {
961 void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
962 BitVector &SavedRegs,
963 RegScavenger *RS) const {
964 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
965
963966 auto &HST = static_cast(MF.getSubtarget());
964967 auto &HRI = *HST.getRegisterInfo();
965968
968971 // If we have a function containing __builtin_eh_return we want to spill and
969972 // restore all callee saved registers. Pretend that they are used.
970973 if (HasEHReturn) {
971 MachineRegisterInfo &MRI = MF.getRegInfo();
972974 for (const MCPhysReg *CSRegs = HRI.getCalleeSavedRegs(&MF); *CSRegs;
973975 ++CSRegs)
974 if (!MRI.isPhysRegUsed(*CSRegs))
975 MRI.setPhysRegUsed(*CSRegs);
976 SavedRegs.set(*CSRegs);
976977 }
977978
978979 const TargetRegisterClass &RC = Hexagon::IntRegsRegClass;
4444 MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override;
4545 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
4646 RegScavenger *RS = nullptr) const override;
47 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
47 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
4848 RegScavenger *RS) const override;
4949
5050 bool targetHandlesStackFrameRounding() const override {
151151 return isInt<15>(MFI->getMaxCallFrameSize()) && !MFI->hasVarSizedObjects();
152152 }
153153
154 void Mips16FrameLowering::
155 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
156 RegScavenger *RS) const {
154 void Mips16FrameLowering::determineCalleeSaves(MachineFunction &MF,
155 BitVector &SavedRegs,
156 RegScavenger *RS) const {
157 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
157158 const Mips16InstrInfo &TII =
158159 *static_cast(STI.getInstrInfo());
159160 const MipsRegisterInfo &RI = TII.getRegisterInfo();
160161 const BitVector Reserved = RI.getReservedRegs(MF);
161162 bool SaveS2 = Reserved[Mips::S2];
162163 if (SaveS2)
163 MF.getRegInfo().setPhysRegUsed(Mips::S2);
164 SavedRegs.set(Mips::S2);
164165 if (hasFP(MF))
165 MF.getRegInfo().setPhysRegUsed(Mips::S0);
166 SavedRegs.set(Mips::S0);
166167 }
167168
168169 const MipsFrameLowering *
3737
3838 bool hasReservedCallFrame(const MachineFunction &MF) const override;
3939
40 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
41 RegScavenger *RS) const override;
40 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
41 RegScavenger *RS) const override;
4242 };
4343
4444 } // End llvm namespace
620620 !MFI->hasVarSizedObjects();
621621 }
622622
623 void MipsSEFrameLowering::
624 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
625 RegScavenger *RS) const {
626 MachineRegisterInfo &MRI = MF.getRegInfo();
623 /// Mark \p Reg and all registers aliasing it in the bitset.
624 void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs, unsigned Reg) {
625 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
626 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
627 SavedRegs.set(*AI);
628 }
629
630 void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
631 BitVector &SavedRegs,
632 RegScavenger *RS) const {
633 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
627634 MipsFunctionInfo *MipsFI = MF.getInfo();
628635 MipsABIInfo ABI = STI.getABI();
629636 unsigned FP = ABI.GetFramePtr();
631638
632639 // Mark $fp as used if function has dedicated frame pointer.
633640 if (hasFP(MF))
634 MRI.setPhysRegUsed(FP);
641 setAliasRegs(MF, SavedRegs, FP);
635642 // Mark $s7 as used if function has dedicated base pointer.
636643 if (hasBP(MF))
637 MRI.setPhysRegUsed(BP);
644 setAliasRegs(MF, SavedRegs, BP);
638645
639646 // Create spill slots for eh data registers if function calls eh_return.
640647 if (MipsFI->callsEhReturn())
3333
3434 bool hasReservedCallFrame(const MachineFunction &MF) const override;
3535
36 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
37 RegScavenger *RS) const override;
36 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
37 RegScavenger *RS) const override;
3838 unsigned ehDataReg(unsigned I) const;
3939 };
4040
11571157 }
11581158 }
11591159
1160 void
1161 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1162 RegScavenger *) const {
1160 void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
1161 BitVector &SavedRegs,
1162 RegScavenger *RS) const {
1163 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1164
11631165 const PPCRegisterInfo *RegInfo =
11641166 static_cast(Subtarget.getRegisterInfo());
11651167
11671169 PPCFunctionInfo *FI = MF.getInfo();
11681170 unsigned LR = RegInfo->getRARegister();
11691171 FI->setMustSaveLR(MustSaveLR(MF, LR));
1170 MachineRegisterInfo &MRI = MF.getRegInfo();
1171 MRI.setPhysRegUnused(LR);
1172 SavedRegs.reset(LR);
11721173
11731174 // Save R31 if necessary
11741175 int FPSI = FI->getFramePointerSaveIndex();
12131214 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
12141215 // function uses CR 2, 3, or 4.
12151216 if (!isPPC64 && !isDarwinABI &&
1216 (MRI.isPhysRegUsed(PPC::CR2) ||
1217 MRI.isPhysRegUsed(PPC::CR3) ||
1218 MRI.isPhysRegUsed(PPC::CR4))) {
1217 (SavedRegs.test(PPC::CR2) ||
1218 SavedRegs.test(PPC::CR3) ||
1219 SavedRegs.test(PPC::CR4))) {
12191220 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
12201221 FI->setCRSpillFrameIndex(FrameIdx);
12211222 }
4444 bool needsFP(const MachineFunction &MF) const;
4545 void replaceFPWithRealFP(MachineFunction &MF) const;
4646
47 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
48 RegScavenger *RS = nullptr) const override;
47 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
48 RegScavenger *RS = nullptr) const override;
4949 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
5050 RegScavenger *RS = nullptr) const override;
5151 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
246246 #endif
247247 }
248248
249 void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
250 (MachineFunction &MF, RegScavenger *RS) const {
251
249 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
250 BitVector &SavedRegs,
251 RegScavenger *RS) const {
252 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
252253 if (!DisableLeafProc && isLeafProc(MF)) {
253254 SparcMachineFunctionInfo *MFI = MF.getInfo();
254255 MFI->setLeafProc(true);
3535
3636 bool hasReservedCallFrame(const MachineFunction &MF) const override;
3737 bool hasFP(const MachineFunction &MF) const override;
38 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
39 RegScavenger *RS = nullptr) const override;
38 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
39 RegScavenger *RS = nullptr) const override;
4040
4141 private:
4242 // Remap input registers to output registers for leaf procedure.
6060 return SpillOffsetTable;
6161 }
6262
63 void SystemZFrameLowering::
64 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
65 RegScavenger *RS) const {
63 void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
64 BitVector &SavedRegs,
65 RegScavenger *RS) const {
66 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
67
6668 MachineFrameInfo *MFFrame = MF.getFrameInfo();
67 MachineRegisterInfo &MRI = MF.getRegInfo();
6869 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
6970 bool HasFP = hasFP(MF);
7071 SystemZMachineFunctionInfo *MFI = MF.getInfo();
7677 // argument register R6D.
7778 if (IsVarArg)
7879 for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
79 MRI.setPhysRegUsed(SystemZ::ArgGPRs[I]);
80 SavedRegs.set(SystemZ::ArgGPRs[I]);
8081
8182 // If the function requires a frame pointer, record that the hard
8283 // frame pointer will be clobbered.
8384 if (HasFP)
84 MRI.setPhysRegUsed(SystemZ::R11D);
85 SavedRegs.set(SystemZ::R11D);
8586
8687 // If the function calls other functions, record that the return
8788 // address register will be clobbered.
8889 if (MFFrame->hasCalls())
89 MRI.setPhysRegUsed(SystemZ::R14D);
90 SavedRegs.set(SystemZ::R14D);
9091
9192 // If we are saving GPRs other than the stack pointer, we might as well
9293 // save and restore the stack pointer at the same time, via STMG and LMG.
9596 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
9697 for (unsigned I = 0; CSRegs[I]; ++I) {
9798 unsigned Reg = CSRegs[I];
98 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
99 MRI.setPhysRegUsed(SystemZ::R15D);
99 if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
100 SavedRegs.set(SystemZ::R15D);
100101 break;
101102 }
102103 }
2626 bool isFPCloseToIncomingSP() const override { return false; }
2727 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) const
2828 override;
29 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
30 RegScavenger *RS) const override;
29 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
30 RegScavenger *RS) const override;
3131 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
3232 MachineBasicBlock::iterator MBBI,
3333 const std::vector &CSI,
14241424 return true;
14251425 }
14261426
1427 void
1428 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1429 RegScavenger *RS) const {
1427 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1428 BitVector &SavedRegs,
1429 RegScavenger *RS) const {
1430 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1431
14301432 MachineFrameInfo *MFI = MF.getFrameInfo();
14311433
14321434 X86MachineFunctionInfo *X86FI = MF.getInfo();
14481450
14491451 // Spill the BasePtr if it's used.
14501452 if (TRI->hasBasePointer(MF))
1451 MF.getRegInfo().setPhysRegUsed(TRI->getBaseRegister());
1453 SavedRegs.set(TRI->getBaseRegister());
14521454 }
14531455
14541456 static bool
6767 void adjustForHiPEPrologue(MachineFunction &MF,
6868 MachineBasicBlock &PrologueMBB) const override;
6969
70 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
71 RegScavenger *RS = nullptr) const override;
70 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
71 RegScavenger *RS = nullptr) const override;
7272
7373 bool
7474 assignCalleeSavedSpillSlots(MachineFunction &MF,
524524 MBB.erase(I);
525525 }
526526
527 void XCoreFrameLowering::
528 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
529 RegScavenger *RS) const {
527 void XCoreFrameLowering::determineCalleeSaves(MachineFunction &MF,
528 BitVector &SavedRegs,
529 RegScavenger *RS) const {
530 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
531
530532 XCoreFunctionInfo *XFI = MF.getInfo();
531533
532 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
534 const MachineRegisterInfo &MRI = MF.getRegInfo();
535 bool LRUsed = MRI.isPhysRegModified(XCore::LR);
533536
534537 if (!LRUsed && !MF.getFunction()->isVarArg() &&
535538 MF.getFrameInfo()->estimateStackSize(MF))
549552 if (LRUsed) {
550553 // We will handle the LR in the prologue/epilogue
551554 // and allocate space on the stack ourselves.
552 MF.getRegInfo().setPhysRegUnused(XCore::LR);
555 SavedRegs.reset(XCore::LR);
553556 XFI->createLRSpillSlot(MF);
554557 }
555558
4646
4747 bool hasFP(const MachineFunction &MF) const override;
4848
49 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
50 RegScavenger *RS = nullptr) const override;
49 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
50 RegScavenger *RS = nullptr) const override;
5151
5252 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
5353 RegScavenger *RS = nullptr) const override;
77 define i8* @rt0(i32 %x) nounwind readnone {
88 entry:
99 ; CHECK-LABEL: rt0:
10 ; CHECK: {r7, lr}
1110 ; CHECK: mov r0, lr
1211 %0 = tail call i8* @llvm.returnaddress(i32 0)
1312 ret i8* %0
1615 define i8* @rt2() nounwind readnone {
1716 entry:
1817 ; CHECK-LABEL: rt2:
19 ; CHECK: {r7, lr}
2018 ; CHECK: ldr r[[R0:[0-9]+]], [r7]
21 ; CHECK: ldr r0, [r0]
22 ; CHECK: ldr r0, [r0, #4]
19 ; CHECK: ldr r0, [r[[R0]]]
20 ; CHECK: ldr r0, [r[[R0]], #4]
2321 %0 = tail call i8* @llvm.returnaddress(i32 2)
2422 ret i8* %0
2523 }