llvm.org GIT mirror llvm / a347f85
Starting to refactor Target to separate out code that's needed to fully describe target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
52 changed file(s) with 504 addition(s) and 273 deletion(s). Raw diff Collapse all Expand all
17241724 $(Echo) "Building $(
17251725 $(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
17261726
1727 $(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
1728 $(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
1729 $(Echo) "Building $(
1730 $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
1731
17271732 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
17281733 $(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
17291734 $(Echo) "Building $(
1730 $(Verb) $(TableGen) -gen-register-desc-header -o $(call SYSPATH, $@) $<
1735 $(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
17311736
17321737 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
17331738 $(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
17341739 $(Echo) "Building $(
1735 $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
1740 $(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
17361741
17371742 $(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
17381743 $(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir
0 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_MC_MCREGISTERINFO_H
16 #define LLVM_MC_MCREGISTERINFO_H
17
18 #include
19
20 namespace llvm {
21
22 /// TargetRegisterDesc - This record contains all of the information known about
23 /// a particular register. The Overlaps field contains a pointer to a zero
24 /// terminated array of registers that this register aliases, starting with
25 /// itself. This is needed for architectures like X86 which have AL alias AX
26 /// alias EAX. The SubRegs field is a zero terminated array of registers that
27 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
28 /// AX. The SuperRegs field is a zero terminated array of registers that are
29 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
30 /// of AX.
31 ///
32 struct TargetRegisterDesc {
33 const char *Name; // Printable name for the reg (for debugging)
34 const unsigned *Overlaps; // Overlapping registers, described above
35 const unsigned *SubRegs; // Sub-register set, described above
36 const unsigned *SuperRegs; // Super-register set, described above
37 };
38
39 /// MCRegisterInfo base class - We assume that the target defines a static
40 /// array of TargetRegisterDesc objects that represent all of the machine
41 /// registers that the target has. As such, we simply have to track a pointer
42 /// to this array so that we can turn register number into a register
43 /// descriptor.
44 ///
45 class MCRegisterInfo {
46 private:
47 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
48 unsigned NumRegs; // Number of entries in the array
49
50 public:
51 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
52 /// auto-generated routines. *DO NOT USE*.
53 void InitMCRegisterInfo(const TargetRegisterDesc *D, unsigned NR) {
54 Desc = D;
55 NumRegs = NR;
56 }
57
58 const TargetRegisterDesc &operator[](unsigned RegNo) const {
59 assert(RegNo < NumRegs &&
60 "Attempting to access record for invalid register number!");
61 return Desc[RegNo];
62 }
63
64 /// Provide a get method, equivalent to [], but more useful if we have a
65 /// pointer to this object.
66 ///
67 const TargetRegisterDesc &get(unsigned RegNo) const {
68 return operator[](RegNo);
69 }
70
71 /// getAliasSet - Return the set of registers aliased by the specified
72 /// register, or a null list of there are none. The list returned is zero
73 /// terminated.
74 ///
75 const unsigned *getAliasSet(unsigned RegNo) const {
76 // The Overlaps set always begins with Reg itself.
77 return get(RegNo).Overlaps + 1;
78 }
79
80 /// getOverlaps - Return a list of registers that overlap Reg, including
81 /// itself. This is the same as the alias set except Reg is included in the
82 /// list.
83 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
84 ///
85 const unsigned *getOverlaps(unsigned RegNo) const {
86 return get(RegNo).Overlaps;
87 }
88
89 /// getSubRegisters - Return the list of registers that are sub-registers of
90 /// the specified register, or a null list of there are none. The list
91 /// returned is zero terminated and sorted according to super-sub register
92 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
93 ///
94 const unsigned *getSubRegisters(unsigned RegNo) const {
95 return get(RegNo).SubRegs;
96 }
97
98 /// getSuperRegisters - Return the list of registers that are super-registers
99 /// of the specified register, or a null list of there are none. The list
100 /// returned is zero terminated and sorted according to super-sub register
101 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
102 ///
103 const unsigned *getSuperRegisters(unsigned RegNo) const {
104 return get(RegNo).SuperRegs;
105 }
106
107 /// getName - Return the human-readable symbolic target-specific name for the
108 /// specified physical register.
109 const char *getName(unsigned RegNo) const {
110 return get(RegNo).Name;
111 }
112
113 /// getNumRegs - Return the number of registers this target has (useful for
114 /// sizing arrays holding per register information)
115 unsigned getNumRegs() const {
116 return NumRegs;
117 }
118 };
119
120 } // End llvm namespace
121
122 #endif
1515 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
1616 #define LLVM_TARGET_TARGETREGISTERINFO_H
1717
18 #include "llvm/MC/MCRegisterInfo.h"
1819 #include "llvm/CodeGen/MachineBasicBlock.h"
1920 #include "llvm/CodeGen/ValueTypes.h"
2021 #include "llvm/ADT/ArrayRef.h"
3031 class RegScavenger;
3132 template class SmallVectorImpl;
3233 class raw_ostream;
33
34 /// TargetRegisterDesc - This record contains all of the information known about
35 /// a particular register. The Overlaps field contains a pointer to a zero
36 /// terminated array of registers that this register aliases, starting with
37 /// itself. This is needed for architectures like X86 which have AL alias AX
38 /// alias EAX. The SubRegs field is a zero terminated array of registers that
39 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
40 /// AX. The SuperRegs field is a zero terminated array of registers that are
41 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
42 /// of AX.
43 ///
44 struct TargetRegisterDesc {
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *Overlaps; // Overlapping registers, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
49 unsigned CostPerUse; // Extra cost of instructions using register.
50 bool inAllocatableClass; // Register belongs to an allocatable regclass.
51 };
5234
5335 class TargetRegisterClass {
5436 public:
273255 bool isAllocatable() const { return Allocatable; }
274256 };
275257
258 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
259 /// registers. These are used by codegen, not by MC.
260 struct TargetRegisterInfoDesc {
261 unsigned CostPerUse; // Extra cost of instructions using register.
262 bool inAllocatableClass; // Register belongs to an allocatable regclass.
263 };
276264
277265 /// TargetRegisterInfo base class - We assume that the target defines a static
278266 /// array of TargetRegisterDesc objects that represent all of the machine
280268 /// to this array so that we can turn register number into a register
281269 /// descriptor.
282270 ///
283 class TargetRegisterInfo {
271 class TargetRegisterInfo : public MCRegisterInfo {
284272 public:
285273 typedef const TargetRegisterClass * const * regclass_iterator;
286274 private:
287 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
275 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
288276 const char *const *SubRegIndexNames; // Names of subreg indexes.
289 unsigned NumRegs; // Number of entries in the array
290
291277 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
292
293278 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
294279
295280 protected:
296 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
281 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
297282 regclass_iterator RegClassBegin,
298283 regclass_iterator RegClassEnd,
299284 const char *const *subregindexnames,
378363 BitVector getAllocatableSet(const MachineFunction &MF,
379364 const TargetRegisterClass *RC = NULL) const;
380365
381 const TargetRegisterDesc &operator[](unsigned RegNo) const {
382 assert(RegNo < NumRegs &&
383 "Attempting to access record for invalid register number!");
384 return Desc[RegNo];
385 }
386
387 /// Provide a get method, equivalent to [], but more useful if we have a
388 /// pointer to this object.
389 ///
390 const TargetRegisterDesc &get(unsigned RegNo) const {
391 return operator[](RegNo);
392 }
393
394 /// getAliasSet - Return the set of registers aliased by the specified
395 /// register, or a null list of there are none. The list returned is zero
396 /// terminated.
397 ///
398 const unsigned *getAliasSet(unsigned RegNo) const {
399 // The Overlaps set always begins with Reg itself.
400 return get(RegNo).Overlaps + 1;
401 }
402
403 /// getOverlaps - Return a list of registers that overlap Reg, including
404 /// itself. This is the same as the alias set except Reg is included in the
405 /// list.
406 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
407 ///
408 const unsigned *getOverlaps(unsigned RegNo) const {
409 return get(RegNo).Overlaps;
410 }
411
412 /// getSubRegisters - Return the list of registers that are sub-registers of
413 /// the specified register, or a null list of there are none. The list
414 /// returned is zero terminated and sorted according to super-sub register
415 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
416 ///
417 const unsigned *getSubRegisters(unsigned RegNo) const {
418 return get(RegNo).SubRegs;
419 }
420
421 /// getSuperRegisters - Return the list of registers that are super-registers
422 /// of the specified register, or a null list of there are none. The list
423 /// returned is zero terminated and sorted according to super-sub register
424 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
425 ///
426 const unsigned *getSuperRegisters(unsigned RegNo) const {
427 return get(RegNo).SuperRegs;
428 }
429
430 /// getName - Return the human-readable symbolic target-specific name for the
431 /// specified physical register.
432 const char *getName(unsigned RegNo) const {
433 return get(RegNo).Name;
434 }
435
436366 /// getCostPerUse - Return the additional cost of using this register instead
437367 /// of other registers in its class.
438368 unsigned getCostPerUse(unsigned RegNo) const {
439 return get(RegNo).CostPerUse;
440 }
441
442 /// getNumRegs - Return the number of registers this target has (useful for
443 /// sizing arrays holding per register information)
444 unsigned getNumRegs() const {
445 return NumRegs;
369 return InfoDesc[RegNo].CostPerUse;
370 }
371
372 /// isInAllocatableClass - Return true if the register is in the allocation
373 /// of any register class.
374 bool isInAllocatableClass(unsigned RegNo) const {
375 return InfoDesc[RegNo].inAllocatableClass;
446376 }
447377
448378 /// getSubRegIndexName - Return the human-readable symbolic target-specific
3232 class MCContext;
3333 class MCDisassembler;
3434 class MCInstPrinter;
35 class MCRegisterInfo;
3536 class MCStreamer;
3637 class TargetAsmBackend;
3738 class TargetAsmLexer;
6364 typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
6465
6566 typedef MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T,
66 StringRef TT);
67 StringRef TT);
68 typedef MCRegisterInfo *(*RegInfoCtorFnTy)(const Target &T,
69 StringRef TT);
6770 typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
6871 const std::string &TT,
6972 const std::string &Features);
119122 /// HasJIT - Whether this target supports the JIT.
120123 bool HasJIT;
121124
125 /// AsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
126 /// registered.
122127 AsmInfoCtorFnTy AsmInfoCtorFn;
128
129 /// RegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
130 /// if registered.
131 RegInfoCtorFnTy RegInfoCtorFn;
123132
124133 /// TargetMachineCtorFn - Construction function for this target's
125134 /// TargetMachine, if registered.
228237 if (!AsmInfoCtorFn)
229238 return 0;
230239 return AsmInfoCtorFn(*this, Triple);
240 }
241
242 /// createRegInfo - Create a MCRegisterInfo implementation for the specified
243 /// target triple.
244 ///
245 /// \arg Triple - This argument is used to determine the target machine
246 /// feature set; it should always be provided. Generally this should be
247 /// either the target triple from the module, or the target triple of the
248 /// host if that does not exist.
249 MCRegisterInfo *createRegInfo(StringRef Triple) const {
250 if (!RegInfoCtorFn)
251 return 0;
252 return RegInfoCtorFn(*this, Triple);
231253 }
232254
233255 /// createTargetMachine - Create a target specific machine implementation
443465 T.AsmInfoCtorFn = Fn;
444466 }
445467
468 /// RegisterRegInfo - Register a MCRegisterInfo implementation for the
469 /// given target.
470 ///
471 /// Clients are responsible for ensuring that registration doesn't occur
472 /// while another thread is attempting to access the registry. Typically
473 /// this is done by initializing all targets at program startup.
474 ///
475 /// @param T - The target being registered.
476 /// @param Fn - A function to construct a MCRegisterInfo for the target.
477 static void RegisterRegInfo(Target &T, Target::RegInfoCtorFnTy Fn) {
478 // Ignore duplicate registration.
479 if (!T.RegInfoCtorFn)
480 T.RegInfoCtorFn = Fn;
481 }
482
446483 /// RegisterTargetMachine - Register a TargetMachine implementation for the
447484 /// given target.
448485 ///
111111 /// register, so a register allocator needs to track its liveness and
112112 /// availability.
113113 bool isAllocatable(unsigned PhysReg) const {
114 return TRI->get(PhysReg).inAllocatableClass && !isReserved(PhysReg);
114 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
115115 }
116116 };
117117 } // end namespace llvm
3838 #include "llvm/ADT/BitVector.h"
3939 #include "llvm/ADT/SmallVector.h"
4040 #include "llvm/Support/CommandLine.h"
41 #include "ARMGenRegisterDesc.inc"
42 #include "ARMGenRegisterInfo.inc"
4143
4244 using namespace llvm;
4345
5355
5456 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
5557 const ARMSubtarget &sti)
56 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
58 : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
59 ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
5760 TII(tii), STI(sti),
5861 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
5962 BasePtr(ARM::R6) {
12861289 MI.setDesc(TII.get(ARM::t2SUBri));
12871290 }
12881291 }
1289
1290 #include "ARMGenRegisterInfo.inc"
0 set(LLVM_TARGET_DEFINITIONS ARM.td)
11
2 tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(ARMGenRegisterNames.inc -gen-register-enums)
4 tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
3 tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
4 tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(ARMGenRegisterInfo.inc -gen-register-info)
56 tablegen(ARMGenInstrNames.inc -gen-instr-enums)
67 tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
78 tablegen(ARMGenCodeEmitter.inc -gen-emitter)
1111 TARGET = ARM
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
15 ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
16 ARMGenInstrInfo.inc ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
14 BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
15 ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
16 ARMGenInstrNames.inc ARMGenInstrInfo.inc \
17 ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
1718 ARMGenDAGISel.inc ARMGenSubtarget.inc \
1819 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
1920 ARMGenDecoderTables.inc ARMGenEDInfo.inc \
3232 #include "llvm/ADT/BitVector.h"
3333 #include "llvm/ADT/STLExtras.h"
3434 #include
35 #include "AlphaGenRegisterDesc.inc"
36 #include "AlphaGenRegisterInfo.inc"
3537 using namespace llvm;
3638
3739 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
38 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
40 : AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
41 Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
3942 TII(tii) {
4043 }
4144
203206 return -1;
204207 }
205208
206 #include "AlphaGenRegisterInfo.inc"
207
208209 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
209210 {
210 std::string s(RegisterDescriptors[reg].Name);
211 std::string s(AlphaRegDesc[reg].Name);
211212 return s;
212213 }
0 set(LLVM_TARGET_DEFINITIONS Alpha.td)
11
2 tablegen(AlphaGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
4 tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
3 tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
4 tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
56 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
67 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
78 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
1111 TARGET = Alpha
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
15 AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
16 AlphaGenInstrInfo.inc \
14 BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
15 AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
16 AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
1717 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
1818 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
1919
2828 #include "llvm/Type.h"
2929 #include "llvm/ADT/BitVector.h"
3030 #include "llvm/ADT/STLExtras.h"
31 #include "BlackfinGenRegisterDesc.inc"
32 #include "BlackfinGenRegisterInfo.inc"
3133 using namespace llvm;
3234
3335 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
3436 const TargetInstrInfo &tii)
35 : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
37 : BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc,
38 BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
3639 Subtarget(st),
3740 TII(tii) {}
3841
355358 llvm_unreachable("What is the dwarf register number");
356359 return -1;
357360 }
358
359 #include "BlackfinGenRegisterInfo.inc"
360
0 set(LLVM_TARGET_DEFINITIONS Blackfin.td)
11
2 tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
4 tablegen(BlackfinGenRegisterInfo.inc -gen-register-desc)
3 tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
4 tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
56 tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
67 tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
78 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
1111 TARGET = Blackfin
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterNames.inc \
15 BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
14 BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
15 BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
16 BlackfinGenInstrNames.inc \
1617 BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
1718 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
1819 BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
99 LEVEL = ../../..
1010 LIBRARYNAME = LLVMCellSPUCodeGen
1111 TARGET = SPU
12 BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterNames.inc \
12 BUILT_SOURCES = SPUGenInstrNames.inc \
1313 SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
14 SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
1415 SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
1516 SPUGenInstrInfo.inc SPUGenDAGISel.inc \
1617 SPUGenSubtarget.inc SPUGenCallingConv.inc
4141 #include "llvm/ADT/BitVector.h"
4242 #include "llvm/ADT/STLExtras.h"
4343 #include
44 #include "SPUGenRegisterDesc.inc"
45 #include "SPUGenRegisterInfo.inc"
4446
4547 using namespace llvm;
4648
184186
185187 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
186188 const TargetInstrInfo &tii) :
187 SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
189 SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
190 SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
188191 Subtarget(subtarget),
189192 TII(tii)
190193 {
370373 assert( Reg && "Register scavenger failed");
371374 return Reg;
372375 }
373
374 #include "SPUGenRegisterInfo.inc"
0 set(LLVM_TARGET_DEFINITIONS MBlaze.td)
11
2 tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
4 tablegen(MBlazeGenRegisterInfo.inc -gen-register-desc)
3 tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
4 tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
56 tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
67 tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
78 tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
3535 #include "llvm/Support/raw_ostream.h"
3636 #include "llvm/ADT/BitVector.h"
3737 #include "llvm/ADT/STLExtras.h"
38
38 #include "MBlazeGenRegisterDesc.inc"
39 #include "MBlazeGenRegisterInfo.inc"
3940 using namespace llvm;
4041
4142 MBlazeRegisterInfo::
4243 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
43 : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
44 : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
45 MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
4446 Subtarget(ST), TII(tii) {}
4547
4648 /// getRegisterNumbering - Given the enum value for some register, e.g.
358360 int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
359361 return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
360362 }
361
362 #include "MBlazeGenRegisterInfo.inc"
363
1111
1212 # Make sure that tblgen is run, first thing.
1313 BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
14 MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
15 MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
16 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
17 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
18 MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
19 MBlazeGenEDInfo.inc
14 MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
15 MBlazeGenInstrNames.inc \
16 MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
17 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
18 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
19 MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
20 MBlazeGenEDInfo.inc
2021
2122 DIRS = InstPrinter AsmParser Disassembler TargetInfo
2223
0 set(LLVM_TARGET_DEFINITIONS MSP430.td)
11
2 tablegen(MSP430GenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
4 tablegen(MSP430GenRegisterInfo.inc -gen-register-desc)
3 tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
4 tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
56 tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
67 tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
78 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
2424 #include "llvm/Target/TargetOptions.h"
2525 #include "llvm/ADT/BitVector.h"
2626 #include "llvm/Support/ErrorHandling.h"
27 #include "MSP430GenRegisterDesc.inc"
28 #include "MSP430GenRegisterInfo.inc"
2729
2830 using namespace llvm;
2931
3032 // FIXME: Provide proper call frame setup / destroy opcodes.
3133 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
3234 const TargetInstrInfo &tii)
33 : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
35 : MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc,
36 MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
3437 TM(tm), TII(tii) {
3538 StackAlign = TM.getFrameLowering()->getStackAlignment();
3639 }
249252 llvm_unreachable("Not implemented yet!");
250253 return 0;
251254 }
252
253 #include "MSP430GenRegisterInfo.inc"
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
15 MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
15 MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
16 MSP430GenInstrNames.inc \
1617 MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
1718 MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
1819 MSP430GenSubtarget.inc
0 set(LLVM_TARGET_DEFINITIONS Mips.td)
11
2 tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(MipsGenRegisterNames.inc -gen-register-enums)
4 tablegen(MipsGenRegisterInfo.inc -gen-register-desc)
3 tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
4 tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(MipsGenRegisterInfo.inc -gen-register-info)
56 tablegen(MipsGenInstrNames.inc -gen-instr-enums)
67 tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
78 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
15 MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
15 MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
16 MipsGenInstrNames.inc \
1617 MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
1718 MipsGenDAGISel.inc MipsGenCallingConv.inc \
1819 MipsGenSubtarget.inc
3434 #include "llvm/Support/raw_ostream.h"
3535 #include "llvm/ADT/BitVector.h"
3636 #include "llvm/ADT/STLExtras.h"
37 #include "MipsGenRegisterDesc.inc"
38 #include "MipsGenRegisterInfo.inc"
3739
3840 using namespace llvm;
3941
4042 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
4143 const TargetInstrInfo &tii)
42 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 : MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc,
45 Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
4346 Subtarget(ST), TII(tii) {}
4447
4548 /// getRegisterNumbering - Given the enum value for some register, e.g.
284287 int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
285288 return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
286289 }
287
288 #include "MipsGenRegisterInfo.inc"
44 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
55 tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
66 tablegen(PTXGenInstrNames.inc -gen-instr-enums)
7 tablegen(PTXGenRegisterInfo.inc -gen-register-desc)
8 tablegen(PTXGenRegisterInfo.h.inc -gen-register-desc-header)
7 tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
8 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
9 tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
910 tablegen(PTXGenRegisterNames.inc -gen-register-enums)
1011 tablegen(PTXGenSubtarget.inc -gen-subtarget)
1112
1616 PTXGenDAGISel.inc \
1717 PTXGenInstrInfo.inc \
1818 PTXGenInstrNames.inc \
19 PTXGenRegisterDesc.inc \
1920 PTXGenRegisterInfo.inc \
2021 PTXGenRegisterInfo.h.inc \
2122 PTXGenRegisterNames.inc \
1818
1919 using namespace llvm;
2020
21 #include "PTXGenRegisterDesc.inc"
2122 #include "PTXGenRegisterInfo.inc"
2223
24
25 PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
26 const TargetInstrInfo &TII)
27 : PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) {
28 }
2329
2430 void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
2531 int SPAdj,
2424
2525 struct PTXRegisterInfo : public PTXGenRegisterInfo {
2626 PTXRegisterInfo(PTXTargetMachine &TM,
27 const TargetInstrInfo &TII) {}
27 const TargetInstrInfo &TII);
2828
2929 virtual const unsigned
3030 *getCalleeSavedRegs(const MachineFunction *MF = 0) const {
44 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
55 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
66 tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
7 tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
8 tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
7 tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
8 tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
9 tablegen(PPCGenRegisterInfo.inc -gen-register-info)
910 tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
1011 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
1112 tablegen(PPCGenCallingConv.inc -gen-callingconv)
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
1515 PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
16 PPCGenRegisterDesc.inc \
1617 PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
1718 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
1819 PPCGenSubtarget.inc PPCGenCallingConv.inc \
4242 #include "llvm/ADT/BitVector.h"
4343 #include "llvm/ADT/STLExtras.h"
4444 #include
45 #include "PPCGenRegisterDesc.inc"
46 #include "PPCGenRegisterInfo.inc"
4547
4648 // FIXME (64-bit): Eventually enable by default.
4749 namespace llvm {
109111
110112 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
111113 const TargetInstrInfo &tii)
112 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
114 : PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc,
115 PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
113116 Subtarget(ST), TII(tii) {
114117 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
115118 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
709712
710713 return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
711714 }
712
713 #include "PPCGenRegisterInfo.inc"
0 set(LLVM_TARGET_DEFINITIONS Sparc.td)
11
2 tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(SparcGenRegisterNames.inc -gen-register-enums)
4 tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
3 tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
4 tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(SparcGenRegisterInfo.inc -gen-register-info)
56 tablegen(SparcGenInstrNames.inc -gen-instr-enums)
67 tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
78 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
15 SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
15 SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
16 SparcGenInstrNames.inc \
1617 SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
1718 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
1819
2222 #include "llvm/Type.h"
2323 #include "llvm/ADT/BitVector.h"
2424 #include "llvm/ADT/STLExtras.h"
25 #include "SparcGenRegisterDesc.inc"
26 #include "SparcGenRegisterInfo.inc"
2527 using namespace llvm;
2628
2729 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
2830 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
31 : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
32 SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
3033 Subtarget(st), TII(tii) {
3134 }
3235
134137 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
135138 return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
136139 }
137
138 #include "SparcGenRegisterInfo.inc"
139
0 set(LLVM_TARGET_DEFINITIONS SystemZ.td)
11
2 tablegen(SystemZGenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
4 tablegen(SystemZGenRegisterInfo.inc -gen-register-desc)
3 tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
4 tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
56 tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
67 tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
78 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
15 SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
15 SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
16 SystemZGenInstrNames.inc \
1617 SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
1718 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
1819
2424 #include "llvm/Target/TargetMachine.h"
2525 #include "llvm/Target/TargetOptions.h"
2626 #include "llvm/ADT/BitVector.h"
27 #include "SystemZGenRegisterDesc.inc"
28 #include "SystemZGenRegisterInfo.inc"
2729 using namespace llvm;
2830
2931 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
3032 const SystemZInstrInfo &tii)
31 : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
33 : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
34 SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
3235 TM(tm), TII(tii) {
3336 }
3437
152155 assert(0 && "What is the dwarf register number");
153156 return -1;
154157 }
155
156
157 #include "SystemZGenRegisterInfo.inc"
1919
2020 using namespace llvm;
2121
22 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
22 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
2323 regclass_iterator RCB, regclass_iterator RCE,
2424 const char *const *subregindexnames,
2525 int CFSO, int CFDO)
26 : Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
26 : InfoDesc(ID), SubRegIndexNames(subregindexnames),
2727 RegClassBegin(RCB), RegClassEnd(RCE) {
28 assert(isPhysicalRegister(NumRegs) &&
29 "Target has too many physical registers!");
30
3128 CallFrameSetupOpcode = CFSO;
3229 CallFrameDestroyOpcode = CFDO;
3330 }
8582
8683 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
8784 const TargetRegisterClass *RC) const {
88 BitVector Allocatable(NumRegs);
85 BitVector Allocatable(getNumRegs());
8986 if (RC) {
9087 getAllocatableSetForRC(MF, RC, Allocatable);
9188 } else {
0 set(LLVM_TARGET_DEFINITIONS X86.td)
11
2 tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
32 tablegen(X86GenRegisterNames.inc -gen-register-enums)
4 tablegen(X86GenRegisterInfo.inc -gen-register-desc)
3 tablegen(X86GenRegisterDesc.inc -gen-register-desc)
4 tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(X86GenRegisterInfo.inc -gen-register-info)
56 tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
67 tablegen(X86GenInstrNames.inc -gen-instr-enums)
78 tablegen(X86GenInstrInfo.inc -gen-instr-desc)
1111 TARGET = X86
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
15 X86GenRegisterInfo.inc X86GenInstrNames.inc \
16 X86GenInstrInfo.inc X86GenAsmWriter.inc X86GenAsmMatcher.inc \
14 BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
15 X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
16 X86GenInstrNames.inc X86GenInstrInfo.inc \
17 X86GenAsmWriter.inc X86GenAsmMatcher.inc \
1718 X86GenAsmWriter1.inc X86GenDAGISel.inc \
1819 X86GenDisassemblerTables.inc X86GenFastISel.inc \
1920 X86GenCallingConv.inc X86GenSubtarget.inc \
2021 X86GenEDInfo.inc
2122
22 DIRS = InstPrinter AsmParser Disassembler TargetInfo Utils
23 DIRS = InstPrinter AsmParser Disassembler TargetInfo TargetDesc Utils
2324
2425 include $(LEVEL)/Makefile.common
0 ##===- lib/Target/X86/TargetDesc/Makefile ------------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8
9 LEVEL = ../../../..
10 LIBRARYNAME = LLVMX86Desc
11
12 # Hack: we need to include 'main' target directory to grab private headers
13 CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
14
15 include $(LEVEL)/Makefile.common
0 //===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides X86 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86TargetDesc.h"
14 #include "llvm/MC/MCRegisterInfo.h"
15 #include "X86GenRegisterDesc.inc"
16 using namespace llvm;
17
18 MCRegisterInfo *createX86MCRegisterInfo() {
19 MCRegisterInfo *X = new MCRegisterInfo();
20 InitX86MCRegisterInfo(X);
21 return X;
22 }
0 //===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides X86 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 // Defines symbolic names for X86 registers. This defines a mapping from
14 // register name to register number.
15 //
16 #include "X86GenRegisterNames.inc"
8787
8888 } // End llvm namespace
8989
90 // Defines symbolic names for X86 registers. This defines a mapping from
91 // register name to register number.
92 //
93 #include "X86GenRegisterNames.inc"
90 #include "TargetDesc/X86TargetDesc.h"
9491
9592 // Defines symbolic names for the X86 instructions.
9693 //
3838 #include "llvm/ADT/STLExtras.h"
3939 #include "llvm/Support/ErrorHandling.h"
4040 #include "llvm/Support/CommandLine.h"
41 #include "X86GenRegisterDesc.inc"
42 #include "X86GenRegisterInfo.inc"
4143 using namespace llvm;
4244
4345 cl::opt
4850
4951 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
5052 const TargetInstrInfo &tii)
51 : X86GenRegisterInfo(tm.getSubtarget().is64Bit() ?
53 : X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
54 tm.getSubtarget().is64Bit() ?
5255 X86::ADJCALLSTACKDOWN64 :
5356 X86::ADJCALLSTACKDOWN32,
5457 tm.getSubtarget().is64Bit() ?
917920 }
918921 }
919922
920 #include "X86GenRegisterInfo.inc"
921
922923 namespace {
923924 struct MSAH : public MachineFunctionPass {
924925 static char ID;
0 set(LLVM_TARGET_DEFINITIONS XCore.td)
11
2 tablegen(XCoreGenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
4 tablegen(XCoreGenRegisterInfo.inc -gen-register-desc)
2 tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
3 tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
4 tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
55 tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
66 tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
77 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
1212
1313 # Make sure that tblgen is run, first thing.
1414 BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
15 XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
15 XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
16 XCoreGenInstrNames.inc \
1617 XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
1718 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
1819 XCoreGenSubtarget.inc
3131 #include "llvm/Support/Debug.h"
3232 #include "llvm/Support/ErrorHandling.h"
3333 #include "llvm/Support/raw_ostream.h"
34
34 #include "XCoreGenRegisterDesc.inc"
35 #include "XCoreGenRegisterInfo.inc"
3536 using namespace llvm;
3637
3738 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
38 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
39 : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
40 XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
3941 TII(tii) {
4042 }
4143
327329 unsigned XCoreRegisterInfo::getRARegister() const {
328330 return XCore::LR;
329331 }
330
331 #include "XCoreGenRegisterInfo.inc"
332
7878
7979 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
8080 << " explicit " << ClassName
81 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
81 << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
82 << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
8283 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
8384 << "unsigned Flavour) const;\n"
8485 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
139140 CodeGenTarget Target(Records);
140141 CodeGenRegBank &RegBank = Target.getRegBank();
141142 RegBank.computeDerivedInfo();
142 std::map Overlaps;
143 RegBank.computeOverlaps(Overlaps);
144143
145144 EmitSourceFileHeader("Register Information Source Fragment", OS);
146145
406405 << "RegClass,\n";
407406 OS << " };\n";
408407
409 typedef std::map, LessRecord> DwarfRegNumsMapTy;
410 DwarfRegNumsMapTy DwarfRegNums;
408 // Emit extra information about registers.
409 OS << "\n static const TargetRegisterInfoDesc "
410 << Target.getName() << "RegInfoDesc[] = "
411 << "{ // Extra Descriptors\n";
412 OS << " { 0, 0 },\n";
413
411414 const std::vector &Regs = RegBank.getRegisters();
412
413 // Emit an overlap list for all registers.
414 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
415 const CodeGenRegister *Reg = Regs[i];
416 const CodeGenRegister::Set &O = Overlaps[Reg];
417 // Move Reg to the front so TRI::getAliasSet can share the list.
418 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
419 << getQualifiedName(Reg->TheDef) << ", ";
420 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
421 I != E; ++I)
422 if (*I != Reg)
423 OS << getQualifiedName((*I)->TheDef) << ", ";
424 OS << "0 };\n";
425 }
426
427 // Emit the empty sub-registers list
428 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
429 // Loop over all of the registers which have sub-registers, emitting the
430 // sub-registers list to memory.
431415 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
432416 const CodeGenRegister &Reg = *Regs[i];
433 if (Reg.getSubRegs().empty())
434 continue;
435 // getSubRegs() orders by SubRegIndex. We want a topological order.
436 SetVector SR;
437 Reg.addSubRegsPreOrder(SR);
438 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
439 for (unsigned j = 0, je = SR.size(); j != je; ++j)
440 OS << getQualifiedName(SR[j]->TheDef) << ", ";
441 OS << "0 };\n";
442 }
443
444 // Emit the empty super-registers list
445 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
446 // Loop over all of the registers which have super-registers, emitting the
447 // super-registers list to memory.
448 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
449 const CodeGenRegister &Reg = *Regs[i];
450 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
451 if (SR.empty())
452 continue;
453 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
454 for (unsigned j = 0, je = SR.size(); j != je; ++j)
455 OS << getQualifiedName(SR[j]->TheDef) << ", ";
456 OS << "0 };\n";
457 }
458
459 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
460 OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n";
461
462 // Now that register alias and sub-registers sets have been emitted, emit the
463 // register descriptors now.
464 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
465 const CodeGenRegister &Reg = *Regs[i];
466 OS << " { \"";
467 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
468 if (!Reg.getSubRegs().empty())
469 OS << Reg.getName() << "_SubRegsSet,\t";
470 else
471 OS << "Empty_SubRegsSet,\t";
472 if (!Reg.getSuperRegs().empty())
473 OS << Reg.getName() << "_SuperRegsSet,\t";
474 else
475 OS << "Empty_SuperRegsSet,\t";
476 OS << Reg.CostPerUse << ",\t"
417 OS << " { ";
418 OS << Reg.CostPerUse << ", "
477419 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
478420 }
479421 OS << " };\n"; // End of register descriptors...
422
480423
481424 // Calculate the mapping of subregister+index pairs to physical registers.
482425 // This will also create further anonymous indexes.
574517
575518 // Emit the constructor of the class...
576519 OS << ClassName << "::" << ClassName
577 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
578 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
520 << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
521 << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
522 << " : TargetRegisterInfo(ID"
579523 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
580524 << " SubRegIndexTable,\n"
581525 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
526 << " InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n"
582527 << "}\n\n";
583528
584529 // Collect all information about dwarf register numbers
530 typedef std::map, LessRecord> DwarfRegNumsMapTy;
531 DwarfRegNumsMapTy DwarfRegNums;
585532
586533 // First, just pull all provided information to the map
587534 unsigned maxLength = 0;
670617
671618 OS << "} // End llvm namespace \n";
672619 }
620
621 void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
622 CodeGenTarget Target(Records);
623 CodeGenRegBank &RegBank = Target.getRegBank();
624 RegBank.computeDerivedInfo();
625 std::map Overlaps;
626 RegBank.computeOverlaps(Overlaps);
627
628 OS << "namespace llvm {\n\n";
629
630 const std::string &TargetName = Target.getName();
631 std::string ClassName = TargetName + "GenMCRegisterInfo";
632 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
633 << " explicit " << ClassName << "(const TargetRegisterDesc *D);\n";
634 OS << "};\n";
635
636 OS << "\nnamespace {\n";
637
638 const std::vector &Regs = RegBank.getRegisters();
639
640 // Emit an overlap list for all registers.
641 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
642 const CodeGenRegister *Reg = Regs[i];
643 const CodeGenRegister::Set &O = Overlaps[Reg];
644 // Move Reg to the front so TRI::getAliasSet can share the list.
645 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
646 << getQualifiedName(Reg->TheDef) << ", ";
647 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
648 I != E; ++I)
649 if (*I != Reg)
650 OS << getQualifiedName((*I)->TheDef) << ", ";
651 OS << "0 };\n";
652 }
653
654 // Emit the empty sub-registers list
655 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
656 // Loop over all of the registers which have sub-registers, emitting the
657 // sub-registers list to memory.
658 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
659 const CodeGenRegister &Reg = *Regs[i];
660 if (Reg.getSubRegs().empty())
661 continue;
662 // getSubRegs() orders by SubRegIndex. We want a topological order.
663 SetVector SR;
664 Reg.addSubRegsPreOrder(SR);
665 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
666 for (unsigned j = 0, je = SR.size(); j != je; ++j)
667 OS << getQualifiedName(SR[j]->TheDef) << ", ";
668 OS << "0 };\n";
669 }
670
671 // Emit the empty super-registers list
672 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
673 // Loop over all of the registers which have super-registers, emitting the
674 // super-registers list to memory.
675 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
676 const CodeGenRegister &Reg = *Regs[i];
677 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
678 if (SR.empty())
679 continue;
680 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
681 for (unsigned j = 0, je = SR.size(); j != je; ++j)
682 OS << getQualifiedName(SR[j]->TheDef) << ", ";
683 OS << "0 };\n";
684 }
685
686 OS << "\n const TargetRegisterDesc " << TargetName
687 << "RegDesc[] = { // Descriptors\n";
688 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
689
690 // Now that register alias and sub-registers sets have been emitted, emit the
691 // register descriptors now.
692 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
693 const CodeGenRegister &Reg = *Regs[i];
694 OS << " { \"";
695 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
696 if (!Reg.getSubRegs().empty())
697 OS << Reg.getName() << "_SubRegsSet,\t";
698 else
699 OS << "Empty_SubRegsSet,\t";
700 if (!Reg.getSuperRegs().empty())
701 OS << Reg.getName() << "_SuperRegsSet";
702 else
703 OS << "Empty_SuperRegsSet";
704 OS << " },\n";
705 }
706 OS << " };\n"; // End of register descriptors...
707
708 OS << "}\n\n"; // End of anonymous namespace...
709
710 // MCRegisterInfo initialization routine.
711 OS << "void " << "Init" << TargetName
712 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
713 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
714 << Regs.size()+1 << ");\n}\n\n";
715
716 OS << "} // End llvm namespace \n";
717 }
3232
3333 // runEnums - Print out enum values for all of the registers.
3434 void runEnums(raw_ostream &o);
35
36 // runDesc - Print out register descriptions.
37 void runDesc(raw_ostream &o);
3538 };
3639
3740 } // End llvm namespace
5353 enum ActionType {
5454 PrintRecords,
5555 GenEmitter,
56 GenRegisterEnums, GenRegister, GenRegisterHeader,
56 GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
5757 GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
5858 GenARMDecoder,
5959 GenDisassembler,
9494 "Generate machine code emitter"),
9595 clEnumValN(GenRegisterEnums, "gen-register-enums",
9696 "Generate enum values for registers"),
97 clEnumValN(GenRegister, "gen-register-desc",
98 "Generate a register info description"),
99 clEnumValN(GenRegisterHeader, "gen-register-desc-header",
100 "Generate a register info description header"),
97 clEnumValN(GenRegisterDesc, "gen-register-desc",
98 "Generate register descriptions"),
99 clEnumValN(GenRegisterInfo, "gen-register-info",
100 "Generate registers & reg-classes info"),
101 clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
102 "Generate registers & reg-classes info header"),
101103 clEnumValN(GenInstrEnums, "gen-instr-enums",
102104 "Generate enum values for instructions"),
103105 clEnumValN(GenInstrs, "gen-instr-desc",
260262 case GenEmitter:
261263 CodeEmitterGen(Records).run(Out.os());
262264 break;
263
264265 case GenRegisterEnums:
265266 RegisterInfoEmitter(Records).runEnums(Out.os());
266267 break;
267 case GenRegister:
268 case GenRegisterDesc:
269 RegisterInfoEmitter(Records).runDesc(Out.os());
270 break;
271 case GenRegisterInfo:
268272 RegisterInfoEmitter(Records).run(Out.os());
269273 break;
270 case GenRegisterHeader:
274 case GenRegisterInfoHeader:
271275 RegisterInfoEmitter(Records).runHeader(Out.os());
272276 break;
273277 case GenInstrEnums: