llvm.org GIT mirror llvm / a32cfd2
ARM: correctly decode VFP instructions following unpredictable t2IT When the condition code for an IT instruction is "AL" we get strange "15" predicates on subsequent instructions. These are dealt with for most instructions by treating them as "ARMCC::AL", but VFP takes a different path which didn't have this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335594 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 2 years ago
2 changed file(s) with 8 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
658658 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
659659 unsigned CC;
660660 CC = ITBlock.getITCC();
661 if (CC == 0xF)
662 CC = ARMCC::AL;
661663 if (ITBlock.instrInITBlock())
662664 ITBlock.advanceITState();
663665
None # RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep und
0 # RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | FileCheck %s
11 # rdar://10841671
22
33 0xe3 0xbf
1010 # above sequence of junk bytes and not allowing the disassembler to abort on
1111 # printing the final instruction in this list.
1212 #
13 # ittte al
14 # vldr d19, [pc, #388]
15 # vsub.f64 d17, d17, d16
16 # vadd.f64 d18, d18, d19
17 # vldr d16, [pc, #384]
13 # CHECK: ittte al
14 # CHECK: vldr d19, [pc, #388]
15 # CHECK: vsub.f64 d17, d17, d16
16 # CHECK: vadd.f64 d18, d18, d19
17 # CHECK: vldr d16, [pc, #384]