llvm.org GIT mirror llvm / a2f4bb9
Update the X86 assembler for .intel_syntax to accept the << and >> bitwise operators. rdar://15975725 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200896 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 6 years ago
2 changed file(s) with 68 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
3636 static const char OpPrecedence[] = {
3737 0, // IC_OR
3838 1, // IC_AND
39 2, // IC_PLUS
40 2, // IC_MINUS
41 3, // IC_MULTIPLY
42 3, // IC_DIVIDE
43 4, // IC_RPAREN
44 5, // IC_LPAREN
39 2, // IC_LSHIFT
40 2, // IC_RSHIFT
41 3, // IC_PLUS
42 3, // IC_MINUS
43 4, // IC_MULTIPLY
44 4, // IC_DIVIDE
45 5, // IC_RPAREN
46 6, // IC_LPAREN
4547 0, // IC_IMM
4648 0 // IC_REGISTER
4749 };
6062 enum InfixCalculatorTok {
6163 IC_OR = 0,
6264 IC_AND,
65 IC_LSHIFT,
66 IC_RSHIFT,
6367 IC_PLUS,
6468 IC_MINUS,
6569 IC_MULTIPLY,
197201 Val = Op1.second & Op2.second;
198202 OperandStack.push_back(std::make_pair(IC_IMM, Val));
199203 break;
204 case IC_LSHIFT:
205 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
206 "Left shift operation with an immediate and a register!");
207 Val = Op1.second << Op2.second;
208 OperandStack.push_back(std::make_pair(IC_IMM, Val));
209 break;
210 case IC_RSHIFT:
211 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
212 "Right shift operation with an immediate and a register!");
213 Val = Op1.second >> Op2.second;
214 OperandStack.push_back(std::make_pair(IC_IMM, Val));
215 break;
200216 }
201217 }
202218 }
208224 enum IntelExprState {
209225 IES_OR,
210226 IES_AND,
227 IES_LSHIFT,
228 IES_RSHIFT,
211229 IES_PLUS,
212230 IES_MINUS,
213231 IES_MULTIPLY,
280298 case IES_REGISTER:
281299 State = IES_AND;
282300 IC.pushOperator(IC_AND);
301 break;
302 }
303 PrevState = CurrState;
304 }
305 void onLShift() {
306 IntelExprState CurrState = State;
307 switch (State) {
308 default:
309 State = IES_ERROR;
310 break;
311 case IES_INTEGER:
312 case IES_RPAREN:
313 case IES_REGISTER:
314 State = IES_LSHIFT;
315 IC.pushOperator(IC_LSHIFT);
316 break;
317 }
318 PrevState = CurrState;
319 }
320 void onRShift() {
321 IntelExprState CurrState = State;
322 switch (State) {
323 default:
324 State = IES_ERROR;
325 break;
326 case IES_INTEGER:
327 case IES_RPAREN:
328 case IES_REGISTER:
329 State = IES_RSHIFT;
330 IC.pushOperator(IC_RSHIFT);
283331 break;
284332 }
285333 PrevState = CurrState;
400448 case IES_MINUS:
401449 case IES_OR:
402450 case IES_AND:
451 case IES_LSHIFT:
452 case IES_RSHIFT:
403453 case IES_DIVIDE:
404454 case IES_MULTIPLY:
405455 case IES_LPAREN:
417467 IC.popOperator();
418468 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
419469 PrevState == IES_OR || PrevState == IES_AND ||
470 PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
420471 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
421472 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
422473 CurrState == IES_MINUS) {
505556 case IES_MINUS:
506557 case IES_OR:
507558 case IES_AND:
559 case IES_LSHIFT:
560 case IES_RSHIFT:
508561 case IES_MULTIPLY:
509562 case IES_DIVIDE:
510563 case IES_LPAREN:
511564 // FIXME: We don't handle this type of unary minus, yet.
512565 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
513566 PrevState == IES_OR || PrevState == IES_AND ||
567 PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
514568 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
515569 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
516570 CurrState == IES_MINUS) {
15461600 case AsmToken::Slash: SM.onDivide(); break;
15471601 case AsmToken::Pipe: SM.onOr(); break;
15481602 case AsmToken::Amp: SM.onAnd(); break;
1603 case AsmToken::LessLess:
1604 SM.onLShift(); break;
1605 case AsmToken::GreaterGreater:
1606 SM.onRShift(); break;
15491607 case AsmToken::LBrac: SM.onLBrac(); break;
15501608 case AsmToken::RBrac: SM.onRBrac(); break;
15511609 case AsmToken::LParen: SM.onLParen(); break;
1515 and ecx, ((1)|2)
1616 // CHECK: andl $1, %ecx
1717 and ecx, 1&2+3
18 // CHECK: addl $4938, %eax
19 add eax, 9876 >> 1
20 // CHECK: addl $19752, %eax
21 add eax, 9876 << 1