llvm.org GIT mirror llvm / a2b6e41
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 9 years ago
16 changed file(s) with 319 addition(s) and 110 deletion(s). Raw diff Collapse all Expand all
9393 case ARMCC::GT: return "gt";
9494 case ARMCC::LE: return "le";
9595 case ARMCC::AL: return "al";
96 }
97 }
98
99 namespace ARM_PROC {
100 enum IMod {
101 IE = 2,
102 ID = 3
103 };
104
105 enum IFlags {
106 F = 1,
107 I = 2,
108 A = 4
109 };
110
111 inline static const char *IFlagsToString(unsigned val) {
112 switch (val) {
113 default: llvm_unreachable("Unknown iflags operand");
114 case F: return "f";
115 case I: return "i";
116 case A: return "a";
117 }
118 }
119
120 inline static const char *IModToString(unsigned val) {
121 switch (val) {
122 default: llvm_unreachable("Unknown imod operand");
123 case IE: return "ie";
124 case ID: return "id";
125 }
96126 }
97127 }
98128
152152 let Name = "MemBarrierOpt";
153153 let SuperClasses = [];
154154 let ParserMethod = "tryParseMemBarrierOptOperand";
155 }
156
157 def ProcIFlagsOperand : AsmOperandClass {
158 let Name = "ProcIFlags";
159 let SuperClasses = [];
160 let ParserMethod = "tryParseProcIFlagsOperand";
161 }
162
163 // ARM imod and iflag operands, used only by the CPS instruction.
164 def imod_op : Operand {
165 let PrintMethod = "printCPSIMod";
166 }
167
168 def iflags_op : Operand {
169 let PrintMethod = "printCPSIFlag";
170 let ParserMatchClass = ProcIFlagsOperand;
155171 }
156172
157173 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
11011101 let Inst{7-4} = 0b0111;
11021102 }
11031103
1104 // Change Processor State is a system instruction -- for disassembly only.
1105 // The singleton $opt operand contains the following information:
1106 // opt{4-0} = mode from Inst{4-0}
1107 // opt{5} = changemode from Inst{17}
1108 // opt{8-6} = AIF from Inst{8-6}
1109 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1110 // FIXME: Integrated assembler will need these split out.
1111 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1112 [/* For disassembly only; pattern left blank */]>,
1113 Requires<[IsARM]> {
1104 // Change Processor State is a system instruction -- for disassembly and
1105 // parsing only.
1106 // FIXME: Since the asm parser has currently no clean way to handle optional
1107 // operands, create 3 versions of the same instruction. Once there's a clean
1108 // framework to represent optional operands, change this behavior.
1109 class CPS
1110 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1111 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1112 bits<2> imod;
1113 bits<3> iflags;
1114 bits<5> mode;
1115 bit M;
1116
11141117 let Inst{31-28} = 0b1111;
11151118 let Inst{27-20} = 0b00010000;
1116 let Inst{16} = 0;
1117 let Inst{5} = 0;
1118 }
1119 let Inst{19-18} = imod;
1120 let Inst{17} = M; // Enabled if mode is set;
1121 let Inst{16} = 0;
1122 let Inst{8-6} = iflags;
1123 let Inst{5} = 0;
1124 let Inst{4-0} = mode;
1125 }
1126
1127 let M = 1 in
1128 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1129 "$imod\t$iflags, $mode">;
1130 let mode = 0, M = 0 in
1131 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1132
1133 let imod = 0, iflags = 0, M = 1 in
1134 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
11191135
11201136 // Preload signals the memory system of possible future data/instruction access.
11211137 // These are for disassembly only.
265265 }
266266
267267 // Change Processor State is a system instruction -- for disassembly only.
268 // The singleton $opt operand contains the following information:
269 //
270 // opt{4-0} = mode ==> don't care
271 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
272 // opt{8-6} = AIF from Inst{2-0}
273 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
274 //
275 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
276 // CPS which has more options.
277 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
278 [/* For disassembly only; pattern left blank */]>,
268 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
269 NoItinerary, "cps$imod $iflags",
270 [/* For disassembly only; pattern left blank */]>,
279271 T1Misc<0b0110011> {
280272 // A8.6.38 & B6.1.1
281 let Inst{3} = 0;
282 // FIXME: Finish encoding.
273 bit imod;
274 bits<3> iflags;
275
276 let Inst{4} = imod;
277 let Inst{3} = 0;
278 let Inst{2-0} = iflags;
283279 }
284280
285281 // For both thumb1 and thumb2.
31263126 let Inst{19-16} = func;
31273127 }
31283128
3129 // Change Processor State is a system instruction -- for disassembly only.
3130 // The singleton $opt operand contains the following information:
3131 // opt{4-0} = mode from Inst{4-0}
3132 // opt{5} = changemode from Inst{17}
3133 // opt{8-6} = AIF from Inst{8-6}
3134 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3135 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
3136 [/* For disassembly only; pattern left blank */]> {
3129 // Change Processor State is a system instruction -- for disassembly and
3130 // parsing only.
3131 // FIXME: Since the asm parser has currently no clean way to handle optional
3132 // operands, create 3 versions of the same instruction. Once there's a clean
3133 // framework to represent optional operands, change this behavior.
3134 class t2CPS : T2XI<(outs), iops, NoItinerary,
3135 !strconcat("cps", asm_op),
3136 [/* For disassembly only; pattern left blank */]> {
3137 bits<2> imod;
3138 bits<3> iflags;
3139 bits<5> mode;
3140 bit M;
3141
31373142 let Inst{31-27} = 0b11110;
3138 let Inst{26} = 0;
3143 let Inst{26} = 0;
31393144 let Inst{25-20} = 0b111010;
3145 let Inst{19-16} = 0b1111;
31403146 let Inst{15-14} = 0b10;
3141 let Inst{12} = 0;
3142
3143 bits<11> opt;
3144
3145 // mode number
3146 let Inst{4-0} = opt{4-0};
3147
3148 // M flag
3149 let Inst{8} = opt{5};
3150
3151 // F flag
3152 let Inst{5} = opt{6};
3153
3154 // I flag
3155 let Inst{6} = opt{7};
3156
3157 // A flag
3158 let Inst{7} = opt{8};
3159
3160 // imod flag
3161 let Inst{10-9} = opt{10-9};
3162 }
3147 let Inst{12} = 0;
3148 let Inst{10-9} = imod;
3149 let Inst{8} = M;
3150 let Inst{7-5} = iflags;
3151 let Inst{4-0} = mode;
3152 }
3153
3154 let M = 1 in
3155 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3156 "$imod.w\t$iflags, $mode">;
3157 let mode = 0, M = 0 in
3158 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3159 "$imod.w\t$iflags">;
3160 let imod = 0, iflags = 0, M = 1 in
3161 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
31633162
31643163 // A6.3.4 Branches and miscellaneous control
31653164 // Table A6-14 Change Processor State, and hint instructions
9797 SmallVectorImpl&);
9898 OperandMatchResultTy tryParseMemBarrierOptOperand(
9999 SmallVectorImpl &);
100 OperandMatchResultTy tryParseProcIFlagsOperand(
101 SmallVectorImpl &);
100102
101103 public:
102104 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
125127 Immediate,
126128 MemBarrierOpt,
127129 Memory,
130 ProcIFlags,
128131 Register,
129132 RegisterList,
130133 DPRRegisterList,
147150 struct {
148151 unsigned Val;
149152 } Cop;
153
154 struct {
155 ARM_PROC::IFlags Val;
156 } IFlags;
150157
151158 struct {
152159 const char *Data;
214221 case Memory:
215222 Mem = o.Mem;
216223 break;
224 case ProcIFlags:
225 IFlags = o.IFlags;
217226 }
218227 }
219228
256265 ARM_MB::MemBOpt getMemBarrierOpt() const {
257266 assert(Kind == MemBarrierOpt && "Invalid access!");
258267 return MBOpt.Val;
268 }
269
270 ARM_PROC::IFlags getProcIFlags() const {
271 assert(Kind == ProcIFlags && "Invalid access!");
272 return IFlags.Val;
259273 }
260274
261275 /// @name Memory Operand Accessors
332346 uint64_t Value = CE->getValue();
333347 return ((Value & 0x3) == 0 && Value <= 124);
334348 }
349 bool isProcIFlags() const { return Kind == ProcIFlags; }
335350
336351 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
337352 // Add as immediates when possible. Null MCExpr = 0.
430445 const MCConstantExpr *CE = dyn_cast(getMemOffset());
431446 assert(CE && "Non-constant mode offset operand!");
432447 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
448 }
449
450 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
451 assert(N == 1 && "Invalid number of operands!");
452 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
433453 }
434454
435455 virtual void dump(raw_ostream &OS) const;
551571 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
552572 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
553573 Op->MBOpt.Val = Opt;
574 Op->StartLoc = S;
575 Op->EndLoc = S;
576 return Op;
577 }
578
579 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
580 ARMOperand *Op = new ARMOperand(ProcIFlags);
581 Op->IFlags.Val = IFlags;
554582 Op->StartLoc = S;
555583 Op->EndLoc = S;
556584 return Op;
603631 OS << " (writeback)";
604632 OS << ">";
605633 break;
634 case ProcIFlags: {
635 OS << "
636 unsigned IFlags = getProcIFlags();
637 for (int i=2; i >= 0; --i)
638 if (IFlags & (1 << i))
639 OS << ARM_PROC::IFlagsToString(1 << i);
640 OS << ">";
641 break;
642 }
606643 case Register:
607644 OS << "";
608645 break;
881918
882919 Parser.Lex(); // Eat identifier token.
883920 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
921 return MatchOperand_Success;
922 }
923
924 /// ParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
925 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
926 tryParseProcIFlagsOperand(SmallVectorImpl &Operands) {
927 SMLoc S = Parser.getTok().getLoc();
928 const AsmToken &Tok = Parser.getTok();
929 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
930 StringRef IFlagsStr = Tok.getString();
931
932 unsigned IFlags = 0;
933 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
934 unsigned Flag = StringSwitch(IFlagsStr.substr(i, 1))
935 .Case("a", ARM_PROC::A)
936 .Case("i", ARM_PROC::I)
937 .Case("f", ARM_PROC::F)
938 .Default(~0U);
939
940 // If some specific iflag is already set, it means that some letter is
941 // present more than once, this is not acceptable.
942 if (Flag == ~0U || (IFlags & Flag))
943 return MatchOperand_NoMatch;
944
945 IFlags |= Flag;
946 }
947
948 Parser.Lex(); // Eat identifier token.
949 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
884950 return MatchOperand_Success;
885951 }
886952
12531319 /// setting letters to form a canonical mnemonic and flags.
12541320 //
12551321 // FIXME: Would be nice to autogen this.
1256 static StringRef SplitMnemonicAndCC(StringRef Mnemonic,
1257 unsigned &PredicationCode,
1258 bool &CarrySetting) {
1322 static StringRef SplitMnemonic(StringRef Mnemonic,
1323 unsigned &PredicationCode,
1324 bool &CarrySetting,
1325 unsigned &ProcessorIMod) {
12591326 PredicationCode = ARMCC::AL;
12601327 CarrySetting = false;
1328 ProcessorIMod = 0;
12611329
12621330 // Ignore some mnemonics we know aren't predicated forms.
12631331 //
13111379 CarrySetting = true;
13121380 }
13131381
1382 // The "cps" instruction can have a interrupt mode operand which is glued into
1383 // the mnemonic. Check if this is the case, split it and parse the imod op
1384 if (Mnemonic.startswith("cps")) {
1385 // Split out any imod code.
1386 unsigned IMod =
1387 StringSwitch(Mnemonic.substr(Mnemonic.size()-2, 2))
1388 .Case("ie", ARM_PROC::IE)
1389 .Case("id", ARM_PROC::ID)
1390 .Default(~0U);
1391 if (IMod != ~0U) {
1392 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
1393 ProcessorIMod = IMod;
1394 }
1395 }
1396
13141397 return Mnemonic;
13151398 }
13161399
13411424 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
13421425 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
13431426 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
1344 Mnemonic == "clrex") {
1427 Mnemonic == "clrex" || Mnemonic.startswith("cps")) {
13451428 CanAcceptPredicationCode = false;
13461429 } else {
13471430 CanAcceptPredicationCode = true;
13621445
13631446 // Split out the predication code and carry setting flag from the mnemonic.
13641447 unsigned PredicationCode;
1448 unsigned ProcessorIMod;
13651449 bool CarrySetting;
1366 Head = SplitMnemonicAndCC(Head, PredicationCode, CarrySetting);
1450 Head = SplitMnemonic(Head, PredicationCode, CarrySetting,
1451 ProcessorIMod);
13671452
13681453 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
13691454
14031488 // FIXME: Issue a nice error.
14041489 }
14051490
1491 // Add the processor imod operand, if necessary.
1492 if (ProcessorIMod) {
1493 Operands.push_back(ARMOperand::CreateImm(
1494 MCConstantExpr::Create(ProcessorIMod, getContext()),
1495 NameLoc, NameLoc));
1496 } else {
1497 // This mnemonic can't ever accept a imod, but the user wrote
1498 // one (or misspelled another mnemonic).
1499
1500 // FIXME: Issue a nice error.
1501 }
1502
14061503 // Add the remaining tokens in the mnemonic.
14071504 while (Next != StringRef::npos) {
14081505 Start = Next;
14091506 Next = Name.find('.', Start + 1);
1410 Head = Name.slice(Start, Next);
1411
1412 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
1507 StringRef ExtraToken = Name.slice(Start, Next);
1508
1509 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
14131510 }
14141511
14151512 // Read the remaining operands.
29412941 return true;
29422942 }
29432943
2944 // CPS has a singleton $opt operand that contains the following information:
2945 // opt{4-0} = mode from Inst{4-0}
2946 // opt{5} = changemode from Inst{17}
2947 // opt{8-6} = AIF from Inst{8-6}
2948 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2949 if (Opcode == ARM::CPS) {
2950 unsigned Option = slice(insn, 4, 0) | slice(insn, 17, 17) << 5 |
2951 slice(insn, 8, 6) << 6 | slice(insn, 19, 18) << 9;
2952 MI.addOperand(MCOperand::CreateImm(Option));
2944 // FIXME: To enable correct asm parsing and disasm of CPS we need 3 different
2945 // opcodes which match the same real instruction. This is needed since there's
2946 // no current handling of optional arguments. Fix here when a better handling
2947 // of optional arguments is implemented.
2948 if (Opcode == ARM::CPS3p) {
2949 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
2950 MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
2951 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
2952 NumOpsAdded = 3;
2953 return true;
2954 }
2955 if (Opcode == ARM::CPS2p) {
2956 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
2957 MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
2958 NumOpsAdded = 2;
2959 return true;
2960 }
2961 if (Opcode == ARM::CPS1p) {
2962 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
29532963 NumOpsAdded = 1;
29542964 return true;
29552965 }
827827 }
828828
829829 // CPS has a singleton $opt operand that contains the following information:
830 // opt{4-0} = don't care
831 // opt{5} = 0 (false)
832 // opt{8-6} = AIF from Inst{2-0}
833 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
830 // The first op would be 0b10 as enable and 0b11 as disable in regular ARM,
831 // but in Thumb it's is 0 as enable and 1 as disable. So map it to ARM's
832 // default one. The second get the AIF flags from Inst{2-0}.
834833 if (Opcode == ARM::tCPS) {
835 unsigned Option = slice(insn, 2, 0) << 6 | slice(insn, 4, 4) << 9 | 1 << 10;
836 MI.addOperand(MCOperand::CreateImm(Option));
837 NumOpsAdded = 1;
834 MI.addOperand(MCOperand::CreateImm(2 + slice(insn, 4, 4)));
835 MI.addOperand(MCOperand::CreateImm(slice(insn, 2, 0)));
836 NumOpsAdded = 2;
838837 return true;
839838 }
840839
16581657 break;
16591658 }
16601659
1661 // CPS has a singleton $opt operand that contains the following information:
1662 // opt{4-0} = mode from Inst{4-0}
1663 // opt{5} = changemode from Inst{8}
1664 // opt{8-6} = AIF from Inst{7-5}
1665 // opt{10-9} = imod from Inst{10-9} with 0b10 as enable and 0b11 as disable
1666 if (Opcode == ARM::t2CPS) {
1667 unsigned Option = slice(insn, 4, 0) | slice(insn, 8, 8) << 5 |
1668 slice(insn, 7, 5) << 6 | slice(insn, 10, 9) << 9;
1669 MI.addOperand(MCOperand::CreateImm(Option));
1660 // FIXME: To enable correct asm parsing and disasm of CPS we need 3 different
1661 // opcodes which match the same real instruction. This is needed since there's
1662 // no current handling of optional arguments. Fix here when a better handling
1663 // of optional arguments is implemented.
1664 if (Opcode == ARM::t2CPS3p) {
1665 MI.addOperand(MCOperand::CreateImm(slice(insn, 10, 9))); // imod
1666 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 5))); // iflags
1667 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
1668 NumOpsAdded = 3;
1669 return true;
1670 }
1671 if (Opcode == ARM::t2CPS2p) {
1672 MI.addOperand(MCOperand::CreateImm(slice(insn, 10, 9))); // imod
1673 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 5))); // iflags
1674 NumOpsAdded = 2;
1675 return true;
1676 }
1677 if (Opcode == ARM::t2CPS1p) {
1678 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
16701679 NumOpsAdded = 1;
16711680 return true;
16721681 }
378378 O << "le";
379379 }
380380
381 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
382 raw_ostream &O) {
381 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
382 raw_ostream &O) {
383383 const MCOperand &Op = MI->getOperand(OpNum);
384 unsigned option = Op.getImm();
385 unsigned mode = option & 31;
386 bool changemode = option >> 5 & 1;
387 unsigned AIF = option >> 6 & 7;
388 unsigned imod = option >> 9 & 3;
389 if (imod == 2)
390 O << "ie";
391 else if (imod == 3)
392 O << "id";
393 O << '\t';
394 if (imod > 1) {
395 if (AIF & 4) O << 'a';
396 if (AIF & 2) O << 'i';
397 if (AIF & 1) O << 'f';
398 if (AIF > 0 && changemode) O << ", ";
399 }
400 if (changemode)
401 O << '#' << mode;
384 O << ARM_PROC::IModToString(Op.getImm());
385 }
386
387 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
388 raw_ostream &O) {
389 const MCOperand &Op = MI->getOperand(OpNum);
390 unsigned IFlags = Op.getImm();
391 for (int i=2; i >= 0; --i)
392 if (IFlags & (1 << i))
393 O << ARM_PROC::IFlagsToString(1 << i);
402394 }
403395
404396 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
8484 raw_ostream &O);
8585
8686 void printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
87 void printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O);
88 void printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O);
8789 void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
8890 void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
8991 void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
236236 @ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5]
237237 dsb oshst
238238
239 @ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1]
240 cpsie aif
241
242 @ CHECK: cps #15 @ encoding: [0x0f,0x00,0x02,0xf1]
243 cps #15
244
245 @ CHECK: cpsie if, #10 @ encoding: [0xca,0x00,0x0a,0xf1]
246 cpsie if, #10
247
6464
6565 @ CHECK: wfi @ encoding: [0x30,0xbf]
6666 wfi
67
68 @ CHECK: cpsie aif @ encoding: [0x67,0xb6]
69 cpsie aif
251251 @ CHECK: dsb oshst @ encoding: [0xbf,0xf3,0x42,0x8f]
252252 dsb oshst
253253
254 @ CHECK: cpsie.w aif @ encoding: [0xaf,0xf3,0xe0,0x84]
255 cpsie.w aif
256 @ CHECK: cps #15 @ encoding: [0xaf,0xf3,0x0f,0x81]
257 cps #15
258 @ CHECK: cpsie.w if, #10 @ encoding: [0xaf,0xf3,0x6a,0x85]
259 cpsie.w if, #10
260
117117
118118 # CHECK: setend le
119119 0x00 0x00 0x01 0xf1
120
121 # CHECK: cpsie aif
122 0xc0 0x01 0x08 0xf1
123
124 # CHECK: cps #15
125 0x0f 0x00 0x02 0xf1
126
127 # CHECK: cpsie if, #10
128 0xca 0x00 0x0a 0xf1
102102 # IT block end
103103 # CHECK: rsbs r1, r2, #0
104104 0x51 0x42
105
106 # CHECK: cpsid.w f
107 0xaf 0xf3 0x20 0x86
108
109 # CHECK: cps #15
110 0xaf 0xf3 0x0f 0x81
111
112 # CHECK: cpsie.w if, #10
113 0xaf 0xf3 0x6a 0x85
114
115 # CHECK: cpsie aif
116 0x67 0xb6
575575 IMM("nohash_imm");
576576 IMM("p_imm");
577577 IMM("c_imm");
578 IMM("imod_op");
579 IMM("iflags_op");
578580 IMM("cpinst_operand");
579581 IMM("setend_op");
580582 IMM("cps_opt");