llvm.org GIT mirror llvm / a284cbf
For PR1207: Revert patches that caused the problem. Evan, please investigate and reapply when you've discovered the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8 Reid Spencer 13 years ago
23 changed file(s) with 106 addition(s) and 335 deletion(s). Raw diff Collapse all Expand all
117117 return I->second;
118118 }
119119
120 bool hasInterval(unsigned reg) const {
121 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
122 return I != r2iMap_.end();
123 }
124
125120 /// getMBBStartIdx - Return the base index of the first instruction in the
126121 /// specified MachineBasicBlock.
127122 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
193188 /// copies that cannot yet be coallesced into the "TryAgain" list.
194189 void CopyCoallesceInMBB(MachineBasicBlock *MBB,
195190 std::vector &TryAgain);
196
197191 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
198192 /// which are the src/dst of the copy instruction CopyMI. This returns true
199193 /// if the copy was successfully coallesced away, or if it is never possible
238232 LiveInterval &interval,
239233 unsigned SrcReg);
240234
241 /// handleLiveInRegister - Create interval for a livein register.
242 void handleLiveInRegister(MachineBasicBlock* mbb, LiveInterval &interval);
243
244235 /// Return true if the two specified registers belong to different
245236 /// register classes. The registers may be either phys or virt regs.
246237 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
249240 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
250241 MachineInstr *CopyMI);
251242
252 /// hasRegisterUse - Returns true if there is any use of the specific
253 /// reg between indexes Start and End.
254 bool hasRegisterUse(unsigned Reg, unsigned Start, unsigned End);
243 bool overlapsAliases(const LiveInterval *lhs,
244 const LiveInterval *rhs) const;
255245
256246 static LiveInterval createInterval(unsigned Reg);
257
258 void removeInterval(unsigned Reg) {
259 r2iMap_.erase(Reg);
260 }
261247
262248 LiveInterval &getOrCreateInterval(unsigned reg) {
263249 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
3535 namespace llvm {
3636
3737 class MRegisterInfo;
38 class BitVector;
3938
4039 class LiveVariables : public MachineFunctionPass {
4140 public:
108107 ///
109108 std::vector VirtRegInfo;
110109
111 /// ReservedRegisters - This vector keeps track of which registers
112 /// are reserved register which are not allocatable by the target machine.
113 /// We can not track liveness for values that are in this set.
114 ///
115 BitVector ReservedRegisters;
110 /// AllocatablePhysicalRegisters - This vector keeps track of which registers
111 /// are actually register allocatable by the target machine. We can not track
112 /// liveness for values that are not in this set.
113 ///
114 BitVector AllocatablePhysicalRegisters;
116115
117116 private: // Intermediate data structures
118117 const MRegisterInfo *RegInfo;
137137 /// is an error to add the same register to the same set more than once.
138138 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
139139
140 /// removeLiveIn - Remove the specified register from the live in set.
141 ///
142 void removeLiveIn(unsigned Reg);
143
144140 // Iteration support for live in sets. These sets are kept in sorted
145141 // order by their register number.
146 typedef std::vector::iterator livein_iterator;
147 typedef std::vector::const_iterator const_livein_iterator;
148 livein_iterator livein_begin() { return LiveIns.begin(); }
149 const_livein_iterator livein_begin() const { return LiveIns.begin(); }
150 livein_iterator livein_end() { return LiveIns.end(); }
151 const_livein_iterator livein_end() const { return LiveIns.end(); }
142 typedef std::vector::const_iterator livein_iterator;
143 livein_iterator livein_begin() const { return LiveIns.begin(); }
144 livein_iterator livein_end() const { return LiveIns.end(); }
152145 bool livein_empty() const { return LiveIns.empty(); }
153146
154147 // Code Layout methods.
392392 /// the specific register or NULL if it is not found.
393393 MachineOperand *findRegisterUseOperand(unsigned Reg);
394394
395 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
396 /// the specific register or NULL if it is not found.
397 MachineOperand *findRegisterDefOperand(unsigned Reg);
398
399395 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
400396 ///
401397 void copyKillDeadInfo(const MachineInstr *MI);
283283 return false;
284284 }
285285
286 /// regsOverlap - Returns true if the two registers are equal or alias
287 /// each other. The registers may be virtual register.
288 bool regsOverlap(unsigned regA, unsigned regB) const {
289 if (regA == regB)
290 return true;
291
292 if (isVirtualRegister(regA) || isVirtualRegister(regB))
293 return false;
294 return areAliases(regA, regB);
295 }
296
297286 /// getCalleeSavedRegs - Return a null-terminated list of all of the
298287 /// callee saved registers on this target. The register should be in the
299288 /// order of desired callee-save stack frame offset. The first register is
304293 /// register classes to spill each callee saved register with. The order and
305294 /// length of this list match the getCalleeSaveRegs() list.
306295 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
307
308 /// getReservedRegs - Returns a bitset indexed by physical register number
309 /// indicating if a register is a special register that has particular uses and
310 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
311 /// register scavenger to determine what registers are free.
312 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
313296
314297 //===--------------------------------------------------------------------===//
315298 // Register Class Information
9797 // Set the MBB2IdxMap entry for this MBB.
9898 MBB2IdxMap[MBB->getNumber()] = MIIndex;
9999
100 // If this BB has any live ins, insert a dummy instruction at the
101 // beginning of the function that we will pretend "defines" the values. This
102 // is to make the interval analysis simpler by providing a number.
103 if (MBB->livein_begin() != MBB->livein_end()) {
104 unsigned FirstLiveIn = *MBB->livein_begin();
105
106 // Find a reg class that contains this live in.
107 const TargetRegisterClass *RC = 0;
108 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
109 RCE = mri_->regclass_end(); RCI != RCE; ++RCI)
110 if ((*RCI)->contains(FirstLiveIn)) {
111 RC = *RCI;
112 break;
113 }
114
115 MachineInstr *OldFirstMI = MBB->begin();
116 mri_->copyRegToReg(*MBB, MBB->begin(),
117 FirstLiveIn, FirstLiveIn, RC);
118 assert(OldFirstMI != MBB->begin() &&
119 "copyRetToReg didn't insert anything!");
120 }
121
100122 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
101123 I != E; ++I) {
102124 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
138160 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
139161 (RegRep = rep(srcReg)) == rep(dstReg)) {
140162 // remove from def list
141 LiveInterval &RegInt = getOrCreateInterval(RegRep);
142 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
143 // If def of this move instruction is dead, remove its live range from
144 // the dstination register's live interval.
145 if (MO->isDead()) {
146 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
147 RegInt.removeRange(*RegInt.FindLiveRangeContaining(MoveIdx));
148 if (RegInt.empty())
149 removeInterval(RegRep);
150 }
163 getOrCreateInterval(RegRep);
151164 RemoveMachineInstrFromMaps(mii);
152165 mii = mbbi->erase(mii);
153166 ++numPeep;
171184 }
172185 }
173186
187
174188 for (iterator I = begin(), E = end(); I != E; ++I) {
175189 LiveInterval &LI = I->second;
176190 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
655669 }
656670 }
657671
658 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
659 LiveInterval &interval) {
660 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
661
662 // Look for kills, if it reaches a def before it's killed, then it shouldn't
663 // be considered a livein.
664 MachineBasicBlock::iterator mi = MBB->begin();
665 unsigned baseIndex = 0;
666 unsigned start = 0;
667 unsigned end = start;
668 while (mi != MBB->end()) {
669 if (lv_->KillsRegister(mi, interval.reg)) {
670 DOUT << " killed";
671 end = getUseIndex(baseIndex) + 1;
672 goto exit;
673 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
674 // Another instruction redefines the register before it is ever read.
675 // Then the register is essentially dead at the instruction that defines
676 // it. Hence its interval is:
677 // [defSlot(def), defSlot(def)+1)
678 DOUT << " dead";
679 end = getDefIndex(start) + 1;
680 goto exit;
681 }
682
683 baseIndex += InstrSlots::NUM;
684 ++mi;
685 }
686
687 exit:
688 assert(start < end && "did not find end of interval?");
689
690 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
691 interval.addRange(LR);
692 DOUT << " +" << LR << '\n';
693 }
694
695672 /// computeIntervals - computes the live intervals for virtual
696673 /// registers. for some ordering of the machine instructions [1,N] a
697674 /// live interval is an interval [i, j) where 1 <= i <= j < N for
710687 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
711688
712689 if (MBB->livein_begin() != MBB->livein_end()) {
713 // Create intervals for live-ins to this BB first.
714 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
690 // Process live-ins to this BB first.
691 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
715692 LE = MBB->livein_end(); LI != LE; ++LI) {
716 handleLiveInRegister(MBB, getOrCreateInterval(*LI));
693 handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
694 getOrCreateInterval(*LI), 0);
717695 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
718 handleLiveInRegister(MBB, getOrCreateInterval(*AS));
719 }
696 handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
697 getOrCreateInterval(*AS), 0);
698 }
699 ++MI;
700 MIIndex += InstrSlots::NUM;
720701 }
721702
722703 for (; MI != miEnd; ++MI) {
833814 return true;
834815 }
835816
817
836818 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
837819 /// which are the src/dst of the copy instruction CopyMI. This returns true
838820 /// if the copy was successfully coallesced away, or if it is never possible
842824 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
843825 unsigned SrcReg, unsigned DstReg) {
844826 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
845
827
846828 // Get representative registers.
847 unsigned repSrcReg = rep(SrcReg);
848 unsigned repDstReg = rep(DstReg);
829 SrcReg = rep(SrcReg);
830 DstReg = rep(DstReg);
849831
850832 // If they are already joined we continue.
851 if (repSrcReg == repDstReg) {
833 if (SrcReg == DstReg) {
852834 DOUT << "\tCopy already coallesced.\n";
853835 return true; // Not coallescable.
854836 }
855837
856838 // If they are both physical registers, we cannot join them.
857 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
858 MRegisterInfo::isPhysicalRegister(repDstReg)) {
839 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
840 MRegisterInfo::isPhysicalRegister(DstReg)) {
859841 DOUT << "\tCan not coallesce physregs.\n";
860842 return true; // Not coallescable.
861843 }
862844
863845 // We only join virtual registers with allocatable physical registers.
864 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
865 !allocatableRegs_[repSrcReg]) {
846 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
866847 DOUT << "\tSrc reg is unallocatable physreg.\n";
867848 return true; // Not coallescable.
868849 }
869 if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
870 !allocatableRegs_[repDstReg]) {
850 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
871851 DOUT << "\tDst reg is unallocatable physreg.\n";
872852 return true; // Not coallescable.
873853 }
874854
875855 // If they are not of the same register class, we cannot join them.
876 if (differingRegisterClasses(repSrcReg, repDstReg)) {
856 if (differingRegisterClasses(SrcReg, DstReg)) {
877857 DOUT << "\tSrc/Dest are different register classes.\n";
878858 return true; // Not coallescable.
879859 }
880860
881 LiveInterval &SrcInt = getInterval(repSrcReg);
882 LiveInterval &DestInt = getInterval(repDstReg);
883 assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
861 LiveInterval &SrcInt = getInterval(SrcReg);
862 LiveInterval &DestInt = getInterval(DstReg);
863 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
884864 "Register mapping is horribly broken!");
885865
886866 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
887867 DOUT << " and "; DestInt.print(DOUT, mri_);
888868 DOUT << ": ";
889
890 // Check if it is necessary to propagate "isDead" property before intervals
891 // are joined.
892 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
893 bool isDead = mopd->isDead();
894 unsigned SrcStart = 0;
895 unsigned SrcEnd = 0;
896 if (isDead) {
897 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
898 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
899 SrcStart = SrcLR->start;
900 SrcEnd = SrcLR->end;
901 if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
902 isDead = false;
903 }
904
869
905870 // Okay, attempt to join these two intervals. On failure, this returns false.
906871 // Otherwise, if one of the intervals being joined is a physreg, this method
907872 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
908873 // been modified, so we can use this information below to update aliases.
909 if (JoinIntervals(DestInt, SrcInt)) {
910 if (isDead) {
911 // Result of the copy is dead. Propagate this property.
912 if (SrcStart == 0) {
913 // Live-in to the function but dead. Remove it from MBB live-in set.
914 // JoinIntervals may end up swapping the two intervals.
915 LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
916 LiveInInt.removeRange(SrcStart, SrcEnd);
917 MachineBasicBlock *MBB = CopyMI->getParent();
918 MBB->removeLiveIn(SrcReg);
919 } else {
920 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
921 if (SrcMI) {
922 // FIXME: SrcMI == NULL means the register is livein to a non-entry
923 // MBB. Remove the range from its live interval?
924 MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
925 if (mops)
926 // FIXME: mops == NULL means SrcMI defines a subregister?
927 mops->setIsDead();
928 }
929 }
930 }
931 } else {
874 if (!JoinIntervals(DestInt, SrcInt)) {
932875 // Coallescing failed.
933876
934877 // If we can eliminate the copy without merging the live ranges, do so now.
940883 return false;
941884 }
942885
943 bool Swapped = repSrcReg == DestInt.reg;
886 bool Swapped = SrcReg == DestInt.reg;
944887 if (Swapped)
945 std::swap(repSrcReg, repDstReg);
946 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
888 std::swap(SrcReg, DstReg);
889 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
947890 "LiveInterval::join didn't work right!");
948891
949892 // If we're about to merge live ranges into a physical register live range,
950893 // we have to update any aliased register's live ranges to indicate that they
951894 // have clobbered values for this range.
952 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
953 for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
895 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
896 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
954897 getInterval(*AS).MergeInClobberRanges(SrcInt);
955898 }
956899
960903 // If the intervals were swapped by Join, swap them back so that the register
961904 // mapping (in the r2i map) is correct.
962905 if (Swapped) SrcInt.swap(DestInt);
963 removeInterval(repSrcReg);
964 r2rMap_[repSrcReg] = repDstReg;
906 r2iMap_.erase(SrcReg);
907 r2rMap_[SrcReg] = DstReg;
965908
966909 // Finally, delete the copy instruction.
967910 RemoveMachineInstrFromMaps(CopyMI);
14451388 return !RegClass->contains(RegB);
14461389 }
14471390
1448 /// hasRegisterUse - Returns true if there is any use of the specific
1449 /// reg between indexes Start and End.
1450 bool
1451 LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
1452 for (unsigned Index = Start+InstrSlots::NUM; Index != End;
1453 Index += InstrSlots::NUM) {
1454 // Skip deleted instructions
1455 while (Index != End && !getInstructionFromIndex(Index))
1456 Index += InstrSlots::NUM;
1457 if (Index >= End) break;
1458
1459 MachineInstr *MI = getInstructionFromIndex(Index);
1460 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1461 MachineOperand &MO = MI->getOperand(i);
1462 if (MO.isReg() && MO.isUse() && MO.getReg() &&
1463 mri_->regsOverlap(rep(MO.getReg()), Reg))
1464 return true;
1465 }
1466 }
1467
1468 return false;
1469 }
1470
14711391 LiveInterval LiveIntervals::createInterval(unsigned reg) {
14721392 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
14731393 HUGE_VALF : 0.0F;
7070 return VirtRegInfo[RegIdx];
7171 }
7272
73 /// registerOverlap - Returns true if register 1 is equal to register 2
74 /// or if register 1 is equal to any of alias of register 2.
75 static bool registerOverlap(unsigned Reg1, unsigned Reg2,
76 const MRegisterInfo *RegInfo) {
77 bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
78 bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
79 if (isVirt1 != isVirt2)
80 return false;
81 if (Reg1 == Reg2)
82 return true;
83 else if (isVirt1)
84 return false;
85 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg2);
86 unsigned Alias = *AliasSet; ++AliasSet) {
87 if (Reg1 == Alias)
88 return true;
89 }
90 return false;
91 }
92
7393 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
7494 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
7595 MachineOperand &MO = MI->getOperand(i);
7696 if (MO.isReg() && MO.isKill()) {
77 if (RegInfo->regsOverlap(Reg, MO.getReg()))
97 if (registerOverlap(Reg, MO.getReg(), RegInfo))
7898 return true;
7999 }
80100 }
85105 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
86106 MachineOperand &MO = MI->getOperand(i);
87107 if (MO.isReg() && MO.isDead())
88 if (RegInfo->regsOverlap(Reg, MO.getReg()))
108 if (registerOverlap(Reg, MO.getReg(), RegInfo))
89109 return true;
90110 }
91111 return false;
95115 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
96116 MachineOperand &MO = MI->getOperand(i);
97117 if (MO.isReg() && MO.isDef()) {
98 if (RegInfo->regsOverlap(Reg, MO.getReg()))
118 if (registerOverlap(Reg, MO.getReg(), RegInfo))
99119 return true;
100120 }
101121 }
219239 RegInfo = MF.getTarget().getRegisterInfo();
220240 assert(RegInfo && "Target doesn't have register information?");
221241
222 ReservedRegisters = RegInfo->getReservedRegs(MF);
242 AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
223243
224244 // PhysRegInfo - Keep track of which instruction was the last use of a
225245 // physical register. This is a purely local property, because all physical
246266 E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
247267 MachineBasicBlock *MBB = *DFI;
248268
249 // Mark live-in registers as live-in.
250 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
269 // Mark live-in registers as live-in.
270 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
251271 EE = MBB->livein_end(); II != EE; ++II) {
252272 assert(MRegisterInfo::isPhysicalRegister(*II) &&
253273 "Cannot have a live-in virtual register!");
274294 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
275295 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
276296 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
277 !ReservedRegisters[MO.getReg()]) {
297 AllocatablePhysicalRegisters[MO.getReg()]) {
278298 HandlePhysRegUse(MO.getReg(), MI);
279299 }
280300 }
292312 // Defaults to dead
293313 VRInfo.Kills.push_back(MI);
294314 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
295 !ReservedRegisters[MO.getReg()]) {
315 AllocatablePhysicalRegisters[MO.getReg()]) {
296316 HandlePhysRegDef(MO.getReg(), MI);
297317 }
298318 }
117117 const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo();
118118 if (livein_begin() != livein_end()) {
119119 OS << "Live Ins:";
120 for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
120 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
121121 OutputReg(OS, *I, MRI);
122122 OS << "\n";
123123 }
141141 OS << " " << *SI;
142142 OS << "\n";
143143 }
144 }
145
146 void MachineBasicBlock::removeLiveIn(unsigned Reg) {
147 livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
148 assert(I != livein_end() && "Not a live in!");
149 LiveIns.erase(I);
150144 }
151145
152146 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
179179 return NULL;
180180 }
181181
182 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
183 /// the specific register or NULL if it is not found.
184 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
185 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
186 MachineOperand &MO = getOperand(i);
187 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
188 return &MO;
189 }
190 return NULL;
191 }
192
193182 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
194183 ///
195184 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
291291 }
292292
293293 // A brute force way of adding live-ins to every BB.
294 MachineFunction::iterator MBB = mf_->begin();
295 ++MBB; // Skip entry MBB.
296 for (MachineFunction::iterator E = mf_->end(); MBB != E; ++MBB) {
294 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
295 MBB != E; ++MBB) {
297296 unsigned StartIdx = li_->getMBBStartIdx(MBB->getNumber());
298297 for (IntervalPtrs::iterator i = fixed_.begin(), e = fixed_.end();
299298 i != e; ++i)
2727 #include "llvm/Target/TargetFrameInfo.h"
2828 #include "llvm/Target/TargetMachine.h"
2929 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/BitVector.h"
3130 #include "llvm/ADT/SmallVector.h"
3231 #include "llvm/ADT/STLExtras.h"
3332 #include
295294 0
296295 };
297296 return CalleeSavedRegClasses;
298 }
299
300 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
301 BitVector Reserved(getNumRegs());
302 Reserved.set(ARM::SP);
303 if (STI.isTargetDarwin() || hasFP(MF))
304 Reserved.set(FramePtr);
305 // Some targets reserve R9.
306 if (STI.isR9Reserved())
307 Reserved.set(ARM::R9);
308 // At PEI time, if LR is used, it will be spilled upon entry.
309 if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
310 Reserved.set(ARM::LR);
311 return Reserved;
312297 }
313298
314299 /// hasFP - Return true if the specified function should have a dedicated frame
6666
6767 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
6868
69 BitVector getReservedRegs(const MachineFunction &MF) const;
70
7169 bool hasFP(const MachineFunction &MF) const;
7270
7371 void eliminateCallFramePseudoInstr(MachineFunction &MF,
2727 #include "llvm/Target/TargetInstrInfo.h"
2828 #include "llvm/Support/CommandLine.h"
2929 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/BitVector.h"
3130 #include "llvm/ADT/STLExtras.h"
3231 #include
3332 using namespace llvm;
178177 return CalleeSavedRegClasses;
179178 }
180179
181 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
182 BitVector Reserved(getNumRegs());
183 Reserved.set(Alpha::R15);
184 Reserved.set(Alpha::R30);
185 Reserved.set(Alpha::R31);
186 return Reserved;
187 }
188
189180 //===----------------------------------------------------------------------===//
190181 // Stack Frame Processing methods
191182 //===----------------------------------------------------------------------===//
4848
4949 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5050
51 BitVector getReservedRegs(const MachineFunction &MF) const;
52
5351 bool hasFP(const MachineFunction &MF) const;
5452
5553 void eliminateCallFramePseudoInstr(MachineFunction &MF,
2727 #include "llvm/Target/TargetOptions.h"
2828 #include "llvm/Target/TargetInstrInfo.h"
2929 #include "llvm/Support/CommandLine.h"
30 #include "llvm/ADT/BitVector.h"
3130 #include "llvm/ADT/STLExtras.h"
3231 using namespace llvm;
3332
104103 &IA64::GRRegClass, 0
105104 };
106105 return CalleeSavedRegClasses;
107 }
108
109 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
110 BitVector Reserved(getNumRegs());
111 Reserved.set(IA64::r0);
112 Reserved.set(IA64::r1);
113 Reserved.set(IA64::r2);
114 Reserved.set(IA64::r5);
115 Reserved.set(IA64::r12);
116 Reserved.set(IA64::r13);
117 Reserved.set(IA64::r22);
118 Reserved.set(IA64::rp);
119 return Reserved;
120106 }
121107
122108 //===----------------------------------------------------------------------===//
4747
4848 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
4949
50 BitVector getReservedRegs(const MachineFunction &MF) const;
51
5250 bool hasFP(const MachineFunction &MF) const;
5351
5452 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4040 const TargetRegisterClass *RC = *I;
4141 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4242 E = RC->allocation_order_end(MF); I != E; ++I)
43 Allocatable.set(*I);
43 Allocatable[*I] = true;
4444 }
4545 return Allocatable;
4646 }
3333 #include "llvm/Support/CommandLine.h"
3434 #include "llvm/Support/Debug.h"
3535 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/BitVector.h"
3736 #include "llvm/ADT/STLExtras.h"
3837 #include
3938 using namespace llvm;
338337 Darwin32_CalleeSavedRegClasses;
339338 }
340339
341 // needsFP - Return true if the specified function should have a dedicated frame
342 // pointer register. This is true if the function has variable sized allocas or
343 // if frame pointer elimination is disabled.
344 //
345 static bool needsFP(const MachineFunction &MF) {
346 const MachineFrameInfo *MFI = MF.getFrameInfo();
347 return NoFramePointerElim || MFI->hasVarSizedObjects();
348 }
349
350 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
351 BitVector Reserved(getNumRegs());
352 Reserved.set(PPC::R0);
353 Reserved.set(PPC::R1);
354 Reserved.set(PPC::LR);
355 // In Linux, r2 is reserved for the OS.
356 if (!Subtarget.isDarwin())
357 Reserved.set(PPC::R2);
358 // On PPC64, r13 is the thread pointer. Never allocate this register.
359 // Note that this is overconservative, as it also prevents allocation of
360 // R31 when the FP is not needed.
361 if (Subtarget.isPPC64()) {
362 Reserved.set(PPC::R13);
363 Reserved.set(PPC::R31);
364 }
365 if (needsFP(MF))
366 Reserved.set(PPC::R31);
367 return Reserved;
368 }
369
370340 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
371341 /// copy instructions, turning them into load/store instructions.
372342 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
426396 //===----------------------------------------------------------------------===//
427397 // Stack Frame Processing methods
428398 //===----------------------------------------------------------------------===//
399
400 // needsFP - Return true if the specified function should have a dedicated frame
401 // pointer register. This is true if the function has variable sized allocas or
402 // if frame pointer elimination is disabled.
403 //
404 static bool needsFP(const MachineFunction &MF) {
405 const MachineFrameInfo *MFI = MF.getFrameInfo();
406 return NoFramePointerElim || MFI->hasVarSizedObjects();
407 }
429408
430409 // hasFP - Return true if the specified function actually has a dedicated frame
431410 // pointer register. This is true if the function needs a frame pointer and has
5757
5858 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5959
60 BitVector getReservedRegs(const MachineFunction &MF) const;
61
6260 /// targetHandlesStackFrameRounding - Returns true if the target is
6361 /// responsible for rounding up the stack frame (probably at emitPrologue
6462 /// time).
1919 #include "llvm/CodeGen/MachineLocation.h"
2020 #include "llvm/Target/TargetInstrInfo.h"
2121 #include "llvm/Type.h"
22 #include "llvm/ADT/BitVector.h"
2322 #include "llvm/ADT/STLExtras.h"
2423 using namespace llvm;
2524
116115 return CalleeSavedRegs;
117116 }
118117
119 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
120 BitVector Reserved(getNumRegs());
121 Reserved.set(SP::G2);
122 Reserved.set(SP::G3);
123 Reserved.set(SP::G4);
124 Reserved.set(SP::O6);
125 Reserved.set(SP::I6);
126 Reserved.set(SP::I7);
127 Reserved.set(SP::G0);
128 Reserved.set(SP::G5);
129 Reserved.set(SP::G6);
130 Reserved.set(SP::G7);
131 return Reserved;
132 }
133
134
135118 const TargetRegisterClass* const*
136119 SparcRegisterInfo::getCalleeSavedRegClasses() const {
137120 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
5151
5252 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5353
54 BitVector getReservedRegs(const MachineFunction &MF) const;
55
5654 bool hasFP(const MachineFunction &MF) const;
5755
5856 void eliminateCallFramePseudoInstr(MachineFunction &MF,
3030 #include "llvm/Target/TargetMachine.h"
3131 #include "llvm/Target/TargetOptions.h"
3232 #include "llvm/Support/CommandLine.h"
33 #include "llvm/ADT/BitVector.h"
3433 #include "llvm/ADT/STLExtras.h"
3534 using namespace llvm;
3635
883882 return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
884883 }
885884
886 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
887 BitVector Reserved(getNumRegs());
888 Reserved.set(X86::RSP);
889 Reserved.set(X86::ESP);
890 Reserved.set(X86::SP);
891 Reserved.set(X86::SPL);
892 if (hasFP(MF)) {
893 Reserved.set(X86::RBP);
894 Reserved.set(X86::EBP);
895 Reserved.set(X86::BP);
896 Reserved.set(X86::BPL);
897 }
898 return Reserved;
899 }
900
901885 //===----------------------------------------------------------------------===//
902886 // Stack Frame Processing methods
903887 //===----------------------------------------------------------------------===//
7777 /// length of this list match the getCalleeSavedRegs() list.
7878 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
7979
80 /// getReservedRegs - Returns a bitset indexed by physical register number
81 /// indicating if a register is a special register that has particular uses and
82 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
83 /// register scavenger to determine what registers are free.
84 BitVector getReservedRegs(const MachineFunction &MF) const;
85
8680 bool hasFP(const MachineFunction &MF) const;
8781
8882 void eliminateCallFramePseudoInstr(MachineFunction &MF,