llvm.org GIT mirror llvm / a24986d
Replace a big gob of old coalescer logic with the new CoalescerPair class. CoalescerPair can determine if a copy can be coalesced, and which register gets merged away. The old logic in SimpleRegisterCoalescing had evolved into something a bit too convoluted. This second attempt fixes some crashes that only occurred Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106769 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
5 changed file(s) with 236 addition(s) and 749 deletion(s). Raw diff Collapse all Expand all
132132 bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
133133 unsigned reg);
134134
135 /// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except
136 /// it checks for sub-register reference and it can check use as well.
137 bool conflictsWithSubPhysRegRef(LiveInterval &li, unsigned Reg,
138 bool CheckUse,
135 /// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
136 /// it checks for alias uses and defs.
137 bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
139138 SmallPtrSet &JoinedCopies);
140139
141140 // Interval creation
217217 return false;
218218 }
219219
220 /// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except
221 /// it checks for sub-register reference and it can check use as well.
222 bool LiveIntervals::conflictsWithSubPhysRegRef(LiveInterval &li,
223 unsigned Reg, bool CheckUse,
220 bool LiveIntervals::conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
224221 SmallPtrSet &JoinedCopies) {
225222 for (LiveInterval::Ranges::const_iterator
226223 I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
238235 MachineOperand& MO = MI->getOperand(i);
239236 if (!MO.isReg())
240237 continue;
241 if (MO.isUse() && !CheckUse)
238 unsigned PhysReg = MO.getReg();
239 if (PhysReg == 0 || PhysReg == Reg ||
240 TargetRegisterInfo::isVirtualRegister(PhysReg))
242241 continue;
243 unsigned PhysReg = MO.getReg();
244 if (PhysReg == 0 || TargetRegisterInfo::isVirtualRegister(PhysReg))
245 continue;
246 if (tri_->isSubRegister(Reg, PhysReg))
242 if (tri_->regsOverlap(Reg, PhysReg))
247243 return true;
248244 }
249245 }
662662 ValNo->isUnused() || ValNo->hasPHIKill())
663663 return false;
664664 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
665 assert(DefMI && "Defining instruction disappeared");
665666 const TargetInstrDesc &TID = DefMI->getDesc();
666667 if (!TID.isAsCheapAsAMove())
667668 return false;
700701 return false;
701702 }
702703
703 SlotIndex DefIdx = CopyIdx.getDefIndex();
704 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
705 DLR->valno->setCopy(0);
706 // Don't forget to update sub-register intervals.
707 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
708 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
709 if (!li_->hasInterval(*SR))
710 continue;
711 const LiveRange *DLR =
712 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
713 if (DLR && DLR->valno->getCopy() == CopyMI)
714 DLR->valno->setCopy(0);
715 }
716 }
704 RemoveCopyFlag(DstReg, CopyMI);
717705
718706 // If copy kills the source register, find the last use and propagate
719707 // kill.
720708 bool checkForDeadDef = false;
721709 MachineBasicBlock *MBB = CopyMI->getParent();
722 if (SrcLR->valno->isKill(DefIdx))
710 if (SrcLR->valno->isKill(CopyIdx.getDefIndex()))
723711 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
724712 checkForDeadDef = true;
725713 }
746734 MachineOperand &MO = CopyMI->getOperand(i);
747735 if (MO.isReg() && MO.isImplicit())
748736 NewMI->addOperand(MO);
749 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
750 unsigned Reg = MO.getReg();
751 const LiveRange *DLR =
752 li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
753 if (DLR && DLR->valno->getCopy() == CopyMI)
754 DLR->valno->setCopy(0);
755 // Handle subregs as well
756 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
757 for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) {
758 if (!li_->hasInterval(*SR))
759 continue;
760 const LiveRange *DLR =
761 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
762 if (DLR && DLR->valno->getCopy() == CopyMI)
763 DLR->valno->setCopy(0);
764 }
765 }
766 }
737 if (MO.isDef())
738 RemoveCopyFlag(MO.getReg(), CopyMI);
767739 }
768740
769741 TransferImplicitOps(CopyMI, NewMI);
782754 /// being updated is not zero, make sure to set it to the correct physical
783755 /// subregister.
784756 void
785 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
786 unsigned SubIdx) {
787 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
788 if (DstIsPhys && SubIdx) {
789 // Figure out the real physical register we are updating with.
790 DstReg = tri_->getSubReg(DstReg, SubIdx);
791 SubIdx = 0;
792 }
757 SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
758 bool DstIsPhys = CP.isPhys();
759 unsigned SrcReg = CP.getSrcReg();
760 unsigned DstReg = CP.getDstReg();
761 unsigned SubIdx = CP.getSubIdx();
793762
794763 // Collect all the instructions using SrcReg.
795764 SmallPtrSet Instrs;
930899 return false;
931900 li.removeValNo(MLR->valno);
932901 return removeIntervalIfEmpty(li, li_, tri_);
902 }
903
904 void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg,
905 const MachineInstr *CopyMI) {
906 SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
907 if (li_->hasInterval(DstReg)) {
908 LiveInterval &LI = li_->getInterval(DstReg);
909 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
910 if (LR->valno->getCopy() == CopyMI)
911 LR->valno->setCopy(0);
912 }
913 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
914 return;
915 for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) {
916 if (!li_->hasInterval(*AS))
917 continue;
918 LiveInterval &LI = li_->getInterval(*AS);
919 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
920 if (LR->valno->getCopy() == CopyMI)
921 LR->valno->setCopy(0);
922 }
933923 }
934924
935925 /// PropagateDeadness - Propagate the dead marker to the instruction which
10111001
10121002 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
10131003 return removeIntervalIfEmpty(li, li_, tri_);
1014 }
1015
1016 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
1017 /// from an implicit def to another register can be coalesced away.
1018 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
1019 LiveInterval &li,
1020 LiveInterval &ImpLi) const{
1021 if (!CopyMI->killsRegister(ImpLi.reg))
1022 return false;
1023 // Make sure this is the only use.
1024 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
1025 UE = mri_->use_end(); UI != UE;) {
1026 MachineInstr *UseMI = &*UI;
1027 ++UI;
1028 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
1029 continue;
1030 return false;
1031 }
1032 return true;
10331004 }
10341005
10351006
10771048 return true;
10781049 }
10791050
1080 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1081 /// register with a physical register, check if any of the virtual register
1082 /// operand is a sub-register use or def. If so, make sure it won't result
1083 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1084 /// vr1024 = extract_subreg vr1025, 1
1085 /// ...
1086 /// vr1024 = mov8rr AH
1087 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1088 /// AH does not have a super-reg whose sub-register 1 is AH.
1089 bool
1090 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1091 unsigned VirtReg,
1092 unsigned PhysReg) {
1093 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1094 E = mri_->reg_end(); I != E; ++I) {
1095 MachineOperand &O = I.getOperand();
1096 if (O.isDebug())
1097 continue;
1098 MachineInstr *MI = &*I;
1099 if (MI == CopyMI || JoinedCopies.count(MI))
1100 continue;
1101 unsigned SubIdx = O.getSubReg();
1102 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1103 return true;
1104 if (MI->isExtractSubreg()) {
1105 SubIdx = MI->getOperand(2).getImm();
1106 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1107 return true;
1108 if (O.isDef()) {
1109 unsigned SrcReg = MI->getOperand(1).getReg();
1110 const TargetRegisterClass *RC =
1111 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1112 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1113 : mri_->getRegClass(SrcReg);
1114 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1115 return true;
1116 }
1117 }
1118 if (MI->isInsertSubreg() || MI->isSubregToReg()) {
1119 SubIdx = MI->getOperand(3).getImm();
1120 if (VirtReg == MI->getOperand(0).getReg()) {
1121 if (!tri_->getSubReg(PhysReg, SubIdx))
1122 return true;
1123 } else {
1124 unsigned DstReg = MI->getOperand(0).getReg();
1125 const TargetRegisterClass *RC =
1126 TargetRegisterInfo::isPhysicalRegister(DstReg)
1127 ? tri_->getPhysicalRegisterRegClass(DstReg)
1128 : mri_->getRegClass(DstReg);
1129 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1130 return true;
1131 }
1132 }
1133 }
1134 return false;
1135 }
1136
1137
1138 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1139 /// an extract_subreg where dst is a physical register, e.g.
1140 /// cl = EXTRACT_SUBREG reg1024, 1
1141 bool
1142 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1143 unsigned SrcReg, unsigned SubIdx,
1144 unsigned &RealDstReg) {
1145 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1146 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1147 if (!RealDstReg) {
1148 DEBUG(dbgs() << "\tIncompatible source regclass: "
1149 << "none of the super-registers of " << tri_->getName(DstReg)
1150 << " are in " << RC->getName() << ".\n");
1151 return false;
1152 }
1153
1154 LiveInterval &RHS = li_->getInterval(SrcReg);
1155 // For this type of EXTRACT_SUBREG, conservatively
1156 // check if the live interval of the source register interfere with the
1157 // actual super physical register we are trying to coalesce with.
1158 if (li_->hasInterval(RealDstReg) &&
1159 RHS.overlaps(li_->getInterval(RealDstReg))) {
1160 DEBUG({
1161 dbgs() << "\t\tInterfere with register ";
1162 li_->getInterval(RealDstReg).print(dbgs(), tri_);
1163 });
1164 return false; // Not coalescable
1165 }
1166 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1167 // Do not check DstReg or its sub-register. JoinIntervals() will take care
1168 // of that.
1169 if (*SR != DstReg &&
1170 !tri_->isSubRegister(DstReg, *SR) &&
1171 li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1172 DEBUG({
1173 dbgs() << "\t\tInterfere with sub-register ";
1174 li_->getInterval(*SR).print(dbgs(), tri_);
1175 });
1176 return false; // Not coalescable
1177 }
1178 return true;
1179 }
1180
1181 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1182 /// an insert_subreg where src is a physical register, e.g.
1183 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1184 bool
1185 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1186 unsigned SrcReg, unsigned SubIdx,
1187 unsigned &RealSrcReg) {
1188 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1189 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1190 if (!RealSrcReg) {
1191 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1192 << "none of the super-registers of " << tri_->getName(SrcReg)
1193 << " are in " << RC->getName() << ".\n");
1194 return false;
1195 }
1196
1197 LiveInterval &LHS = li_->getInterval(DstReg);
1198 if (li_->hasInterval(RealSrcReg) &&
1199 LHS.overlaps(li_->getInterval(RealSrcReg))) {
1200 DEBUG({
1201 dbgs() << "\t\tInterfere with register ";
1202 li_->getInterval(RealSrcReg).print(dbgs(), tri_);
1203 });
1204 return false; // Not coalescable
1205 }
1206 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1207 // Do not check SrcReg or its sub-register. JoinIntervals() will take care
1208 // of that.
1209 if (*SR != SrcReg &&
1210 !tri_->isSubRegister(SrcReg, *SR) &&
1211 li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1212 DEBUG({
1213 dbgs() << "\t\tInterfere with sub-register ";
1214 li_->getInterval(*SR).print(dbgs(), tri_);
1215 });
1216 return false; // Not coalescable
1217 }
1218 return true;
1219 }
1220
1221 /// getRegAllocPreference - Return register allocation preference register.
1222 ///
1223 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1224 MachineRegisterInfo *MRI,
1225 const TargetRegisterInfo *TRI) {
1226 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1227 return 0;
1228 std::pair Hint = MRI->getRegAllocationHint(Reg);
1229 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1230 }
12311051
12321052 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
12331053 /// which are the src/dst of the copy instruction CopyMI. This returns true
12431063
12441064 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
12451065
1246 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1247 bool isExtSubReg = CopyMI->isExtractSubreg();
1248 bool isInsSubReg = CopyMI->isInsertSubreg();
1249 bool isSubRegToReg = CopyMI->isSubregToReg();
1250 unsigned SubIdx = 0;
1251 if (isExtSubReg) {
1252 DstReg = CopyMI->getOperand(0).getReg();
1253 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1254 SrcReg = CopyMI->getOperand(1).getReg();
1255 SrcSubIdx = CopyMI->getOperand(2).getImm();
1256 } else if (isInsSubReg || isSubRegToReg) {
1257 DstReg = CopyMI->getOperand(0).getReg();
1258 DstSubIdx = CopyMI->getOperand(3).getImm();
1259 SrcReg = CopyMI->getOperand(2).getReg();
1260 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1261 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1262 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1263 // coalesced to a larger register so the subreg indices cancel out.
1264 DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
1265 "coalesced to another register.\n");
1266 return false; // Not coalescable.
1267 }
1268 } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1269 if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
1270 // e.g. %reg16404:1 = MOV8rr %reg16412:2
1271 Again = true;
1272 return false; // Not coalescable.
1273 }
1274 } else {
1275 llvm_unreachable("Unrecognized copy instruction!");
1276 }
1277
1278 // If they are already joined we continue.
1279 if (SrcReg == DstReg) {
1280 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1281 return false; // Not coalescable.
1282 }
1283
12841066 CoalescerPair CP(*tii_, *tri_);
12851067 if (!CP.setRegisters(CopyMI)) {
12861068 DEBUG(dbgs() << "\tNot coalescable.\n");
12871069 return false;
12881070 }
12891071
1290 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1291 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1292
1293 // If they are both physical registers, we cannot join them.
1294 if (SrcIsPhys && DstIsPhys) {
1295 DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
1072 // If they are already joined we continue.
1073 if (CP.getSrcReg() == CP.getDstReg()) {
1074 DEBUG(dbgs() << "\tCopy already coalesced.\n");
12961075 return false; // Not coalescable.
12971076 }
12981077
1299 // We only join virtual registers with allocatable physical registers.
1300 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1301 DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
1302 return false; // Not coalescable.
1303 }
1304 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1305 DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
1306 return false; // Not coalescable.
1307 }
1308
1309 // We cannot handle dual subreg indices and mismatched classes at the same
1310 // time.
1311 if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
1312 DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
1313 return false;
1314 }
1315
1316 // Check that a physical source register is compatible with dst regclass
1317 if (SrcIsPhys) {
1318 unsigned SrcSubReg = SrcSubIdx ?
1319 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1320 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1321 const TargetRegisterClass *DstSubRC = DstRC;
1322 if (DstSubIdx)
1323 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1324 assert(DstSubRC && "Illegal subregister index");
1325 if (!DstSubRC->contains(SrcSubReg)) {
1326 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1327 << "none of the super-registers of "
1328 << tri_->getName(SrcSubReg) << " are in "
1329 << DstSubRC->getName() << ".\n");
1330 return false; // Not coalescable.
1331 }
1332 }
1333
1334 // Check that a physical dst register is compatible with source regclass
1335 if (DstIsPhys) {
1336 unsigned DstSubReg = DstSubIdx ?
1337 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1338 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1339 const TargetRegisterClass *SrcSubRC = SrcRC;
1340 if (SrcSubIdx)
1341 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1342 assert(SrcSubRC && "Illegal subregister index");
1343 if (!SrcSubRC->contains(DstSubReg)) {
1344 DEBUG(dbgs() << "\tIncompatible source regclass: "
1345 << "none of the super-registers of "
1346 << tri_->getName(DstSubReg) << " are in "
1347 << SrcSubRC->getName() << ".\n");
1348 (void)DstSubReg;
1349 return false; // Not coalescable.
1350 }
1351 }
1352
1353 // Should be non-null only when coalescing to a sub-register class.
1354 bool CrossRC = false;
1355 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1356 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1357 const TargetRegisterClass *NewRC = NULL;
1358 unsigned RealDstReg = 0;
1359 unsigned RealSrcReg = 0;
1360 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1361 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1362 if (SrcIsPhys && isExtSubReg) {
1363 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1364 // coalesced with AX.
1365 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1366 if (DstSubIdx) {
1367 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1368 // coalesced to a larger register so the subreg indices cancel out.
1369 if (DstSubIdx != SubIdx) {
1370 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1371 return false; // Not coalescable.
1372 }
1373 } else
1374 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1375 SubIdx = 0;
1376 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1377 // EAX = INSERT_SUBREG EAX, r1024, 0
1378 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1379 if (SrcSubIdx) {
1380 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1381 // coalesced to a larger register so the subreg indices cancel out.
1382 if (SrcSubIdx != SubIdx) {
1383 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1384 return false; // Not coalescable.
1385 }
1386 } else
1387 DstReg = tri_->getSubReg(DstReg, SubIdx);
1388 SubIdx = 0;
1389 } else if ((DstIsPhys && isExtSubReg) ||
1390 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1391 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1392 DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
1393 << " of a super-class.\n");
1394 return false; // Not coalescable.
1078 DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg());
1079
1080 // Enforce policies.
1081 if (CP.isPhys()) {
1082 DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n");
1083 // Only coalesce to allocatable physreg.
1084 if (!allocatableRegs_[CP.getDstReg()]) {
1085 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1086 return false; // Not coalescable.
1087 }
1088 } else {
1089 DEBUG({
1090 dbgs() << " with reg%" << CP.getDstReg();
1091 if (CP.getSubIdx())
1092 dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx());
1093 dbgs() << " to " << CP.getNewRC()->getName() << "\n";
1094 });
1095
1096 // Avoid constraining virtual register regclass too much.
1097 if (CP.isCrossClass()) {
1098 if (DisableCrossClassJoin) {
1099 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1100 return false;
13951101 }
1396
1397 // FIXME: The following checks are somewhat conservative. Perhaps a better
1398 // way to implement this is to treat this as coalescing a vr with the
1399 // super physical register.
1400 if (isExtSubReg) {
1401 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1402 return false; // Not coalescable
1403 } else {
1404 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1405 return false; // Not coalescable
1406 }
1407 SubIdx = 0;
1408 } else {
1409 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1410 : CopyMI->getOperand(2).getSubReg();
1411 if (OldSubIdx) {
1412 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1413 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1414 // coalesced to a larger register so the subreg indices cancel out.
1415 // Also check if the other larger register is of the same register
1416 // class as the would be resulting register.
1417 SubIdx = 0;
1418 else {
1419 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1420 return false; // Not coalescable.
1421 }
1422 }
1423 if (SubIdx) {
1424 if (!DstIsPhys && !SrcIsPhys) {
1425 if (isInsSubReg || isSubRegToReg) {
1426 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1427 } else // extract_subreg {
1428 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1429 }
1430 if (!NewRC) {
1431 DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
1432 return false; // Not coalescable
1433 }
1434
1435 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1436 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1437 << SrcRC->getName() << "/"
1438 << DstRC->getName() << " -> "
1439 << NewRC->getName() << ".\n");
1440 Again = true; // May be possible to coalesce later.
1441 return false;
1442 }
1443 }
1444 }
1445 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1446 if (DisableCrossClassJoin)
1447 return false;
1448 CrossRC = true;
1449
1450 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1451 // with another? If it's the resulting destination register, then
1452 // the subidx must be propagated to uses (but only those defined
1453 // by the EXTRACT_SUBREG). If it's being coalesced into another
1454 // register, it should be safe because register is assumed to have
1455 // the register class of the super-register.
1456
1457 // Process moves where one of the registers have a sub-register index.
1458 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1459 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1460 SubIdx = DstMO->getSubReg();
1461 if (SubIdx) {
1462 if (SrcMO->getSubReg())
1463 // FIXME: can we handle this?
1464 return false;
1465 // This is not an insert_subreg but it looks like one.
1466 // e.g. %reg1024:4 = MOV32rr %EAX
1467 isInsSubReg = true;
1468 if (SrcIsPhys) {
1469 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1470 return false; // Not coalescable
1471 SubIdx = 0;
1472 }
1473 } else {
1474 SubIdx = SrcMO->getSubReg();
1475 if (SubIdx) {
1476 // This is not a extract_subreg but it looks like one.
1477 // e.g. %cl = MOV16rr %reg1024:1
1478 isExtSubReg = true;
1479 if (DstIsPhys) {
1480 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1481 return false; // Not coalescable
1482 SubIdx = 0;
1483 }
1484 }
1485 }
1486
1487 // Now determine the register class of the joined register.
1488 if (!SrcIsPhys && !DstIsPhys) {
1489 if (isExtSubReg) {
1490 NewRC =
1491 SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
1492 } else if (isInsSubReg) {
1493 NewRC =
1494 SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
1495 } else {
1496 NewRC = getCommonSubClass(SrcRC, DstRC);
1497 }
1498
1499 if (!NewRC) {
1500 DEBUG(dbgs() << "\tDisjoint regclasses: "
1501 << SrcRC->getName() << ", "
1502 << DstRC->getName() << ".\n");
1503 return false; // Not coalescable.
1504 }
1505
1506 // If we are joining two virtual registers and the resulting register
1507 // class is more restrictive (fewer register, smaller size). Check if it's
1508 // worth doing the merge.
1509 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1102 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1103 mri_->getRegClass(CP.getSrcReg()),
1104 mri_->getRegClass(CP.getDstReg()),
1105 CP.getNewRC())) {
15101106 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1511 << SrcRC->getName() << "/"
1512 << DstRC->getName() << " -> "
1513 << NewRC->getName() << ".\n");
1514 // Allow the coalescer to try again in case either side gets coalesced to
1515 // a physical register that's compatible with the other side. e.g.
1516 // r1024 = MOV32to32_ r1025
1517 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1107 << CP.getNewRC()->getName() << ".\n");
15181108 Again = true; // May be possible to coalesce later.
15191109 return false;
15201110 }
15211111 }
1522 }
1523
1524 // Will it create illegal extract_subreg / insert_subreg?
1525 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1526 return false;
1527 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1528 return false;
1529
1530 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1531 LiveInterval &DstInt = li_->getInterval(DstReg);
1532 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1533 "Register mapping is horribly broken!");
1534
1535 DEBUG({
1536 dbgs() << "\t\tInspecting ";
1537 if (SrcRC) dbgs() << SrcRC->getName() << ": ";
1538 SrcInt.print(dbgs(), tri_);
1539 dbgs() << "\n\t\t and ";
1540 if (DstRC) dbgs() << DstRC->getName() << ": ";
1541 DstInt.print(dbgs(), tri_);
1542 dbgs() << "\n";
1543 });
1544
1545 // Save a copy of the virtual register live interval. We'll manually
1546 // merge this into the "real" physical register live interval this is
1547 // coalesced with.
1112
1113 // When possible, let DstReg be the larger interval.
1114 if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
1115 li_->getInterval(CP.getDstReg()).ranges.size())
1116 CP.flip();
1117 }
1118
1119 // We need to be careful about coalescing a source physical register with a
1120 // virtual register. Once the coalescing is done, it cannot be broken and
1121 // these are not spillable! If the destination interval uses are far away,
1122 // think twice about coalescing them!
1123 // FIXME: Why are we skipping this test for partial copies?
1124 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1125 if (!CP.isPartial() && CP.isPhys()) {
1126 LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
1127
1128 // Don't join with physregs that have a ridiculous number of live
1129 // ranges. The data structure performance is really bad when that
1130 // happens.
1131 if (li_->hasInterval(CP.getDstReg()) &&
1132 li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1133 mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
1134 ++numAborts;
1135 DEBUG(dbgs()
1136 << "\tPhysical register live interval too complicated, abort!\n");
1137 return false;
1138 }
1139
1140 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
1141 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1142 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1143 if (Length > Threshold &&
1144 std::distance(mri_->use_nodbg_begin(CP.getSrcReg()),
1145 mri_->use_nodbg_end()) * Threshold < Length) {
1146 // Before giving up coalescing, if definition of source is defined by
1147 // trivial computation, try rematerializing it.
1148 if (!CP.isFlipped() &&
1149 ReMaterializeTrivialDef(JoinVInt, CP.getDstReg(), 0, CopyMI))
1150 return true;
1151
1152 mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
1153 ++numAborts;
1154 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1155 Again = true; // May be possible to coalesce later.
1156 return false;
1157 }
1158 }
1159
1160 // We may need the source interval after JoinIntervals has destroyed it.
15481161 OwningPtr SavedLI;
1549 if (RealDstReg)
1550 SavedLI.reset(li_->dupInterval(&SrcInt));
1551 else if (RealSrcReg)
1552 SavedLI.reset(li_->dupInterval(&DstInt));
1553
1554 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1555 // Check if it is necessary to propagate "isDead" property.
1556 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1557 bool isDead = mopd->isDead();
1558
1559 // We need to be careful about coalescing a source physical register with a
1560 // virtual register. Once the coalescing is done, it cannot be broken and
1561 // these are not spillable! If the destination interval uses are far away,
1562 // think twice about coalescing them!
1563 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1564 // If the virtual register live interval is long but it has low use
1565 // density, do not join them, instead mark the physical register as its
1566 // allocation preference.
1567 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1568 LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
1569 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1570 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1571
1572 // Don't join with physregs that have a ridiculous number of live
1573 // ranges. The data structure performance is really bad when that
1574 // happens.
1575 if (JoinPInt.ranges.size() > 1000) {
1576 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1577 ++numAborts;
1578 DEBUG(dbgs()
1579 << "\tPhysical register live interval too complicated, abort!\n");
1580 return false;
1581 }
1582
1583 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1584 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1585 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1586 if (Length > Threshold &&
1587 std::distance(mri_->use_nodbg_begin(JoinVReg),
1588 mri_->use_nodbg_end()) * Threshold < Length) {
1589 // Before giving up coalescing, if definition of source is defined by
1590 // trivial computation, try rematerializing it.
1591 if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1592 return true;
1593
1594 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1595 ++numAborts;
1596 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1597 Again = true; // May be possible to coalesce later.
1598 return false;
1599 }
1600 }
1601 }
1162 if (CP.getOrigDstReg() != CP.getDstReg())
1163 SavedLI.reset(li_->dupInterval(&li_->getInterval(CP.getSrcReg())));
16021164
16031165 // Okay, attempt to join these two intervals. On failure, this returns false.
16041166 // Otherwise, if one of the intervals being joined is a physreg, this method
16051167 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
16061168 // been modified, so we can use this information below to update aliases.
1607 bool Swapped = false;
1608 // If SrcInt is implicitly defined, it's safe to coalesce.
1609 if (SrcInt.empty()) {
1610 if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1611 // Only coalesce an empty interval (defined by implicit_def) with
1612 // another interval which has a valno defined by the CopyMI and the CopyMI
1613 // is a kill of the implicit def.
1614 DEBUG(dbgs() << "\tNot profitable!\n");
1615 return false;
1616 }
1617 } else if (!JoinIntervals(DstInt, SrcInt, Swapped, CP)) {
1169 if (!JoinIntervals(CP)) {
16181170 // Coalescing failed.
16191171
16201172 // If definition of source is defined by trivial computation, try
16211173 // rematerializing it.
1622 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1623 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1174 if (!CP.isFlipped() &&
1175 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()),
1176 CP.getDstReg(), 0, CopyMI))
16241177 return true;
16251178
16261179 // If we can eliminate the copy without merging the live ranges, do so now.
1627 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1628 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1629 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1630 JoinedCopies.insert(CopyMI);
1631 DEBUG(dbgs() << "\tTrivial!\n");
1632 return true;
1180 if (!CP.isPartial()) {
1181 LiveInterval *UseInt = &li_->getInterval(CP.getSrcReg());
1182 LiveInterval *DefInt = &li_->getInterval(CP.getDstReg());
1183 if (CP.isFlipped())
1184 std::swap(UseInt, DefInt);
1185 if (AdjustCopiesBackFrom(*UseInt, *DefInt, CopyMI) ||
1186 RemoveCopyByCommutingDef(*UseInt, *DefInt, CopyMI)) {
1187 JoinedCopies.insert(CopyMI);
1188 DEBUG(dbgs() << "\tTrivial!\n");
1189 return true;
1190 }
16331191 }
16341192
16351193 // Otherwise, we are unable to join the intervals.
16381196 return false;
16391197 }
16401198
1641 LiveInterval *ResSrcInt = &SrcInt;
1642 LiveInterval *ResDstInt = &DstInt;
1643 if (Swapped) {
1644 std::swap(SrcReg, DstReg);
1645 std::swap(ResSrcInt, ResDstInt);
1646 }
1647 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1648 "LiveInterval::join didn't work right!");
1649
1650 // If we're about to merge live ranges into a physical register live interval,
1651 // we have to update any aliased register's live ranges to indicate that they
1652 // have clobbered values for this range.
1653 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1199 if (CP.isPhys()) {
16541200 // If this is a extract_subreg where dst is a physical register, e.g.
16551201 // cl = EXTRACT_SUBREG reg1024, 1
16561202 // then create and update the actual physical register allocated to RHS.
1657 if (RealDstReg || RealSrcReg) {
1658 LiveInterval &RealInt =
1659 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1203 unsigned LargerDstReg = CP.getDstReg();
1204 if (CP.getOrigDstReg() != CP.getDstReg()) {
1205 if (tri_->isSubRegister(CP.getOrigDstReg(), LargerDstReg))
1206 LargerDstReg = CP.getOrigDstReg();
1207 LiveInterval &RealInt = li_->getOrCreateInterval(CP.getDstReg());
16601208 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
16611209 E = SavedLI->vni_end(); I != E; ++I) {
16621210 const VNInfo *ValNo = *I;
16681216 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
16691217 }
16701218 RealInt.weight += SavedLI->weight;
1671 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
16721219 }
16731220
16741221 // Update the liveintervals of sub-registers.
1675 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1676 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
1677 li_->getVNInfoAllocator());
1678 }
1679
1680 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1681 // larger super-register.
1682 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1683 !SrcIsPhys && !DstIsPhys) {
1684 if ((isExtSubReg && !Swapped) ||
1685 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1686 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1687 std::swap(SrcReg, DstReg);
1688 std::swap(ResSrcInt, ResDstInt);
1222 LiveInterval &LargerInt = li_->getInterval(LargerDstReg);
1223 for (const unsigned *AS = tri_->getSubRegisters(LargerDstReg); *AS; ++AS) {
1224 LiveInterval &SRI = li_->getOrCreateInterval(*AS);
1225 SRI.MergeInClobberRanges(*li_, LargerInt, li_->getVNInfoAllocator());
1226 DEBUG({
1227 dbgs() << "\t\tsubreg: "; SRI.print(dbgs(), tri_); dbgs() << "\n";
1228 });
16891229 }
16901230 }
16911231
16921232 // Coalescing to a virtual register that is of a sub-register class of the
16931233 // other. Make sure the resulting register is set to the right register class.
1694 if (CrossRC)
1234 if (CP.isCrossClass()) {
16951235 ++numCrossRCs;
1696
1697 // This may happen even if it's cross-rc coalescing. e.g.
1698 // %reg1026 = SUBREG_TO_REG 0, %reg1037, 4
1699 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1700 // be allocate a register from GR64_ABCD.
1701 if (NewRC)
1702 mri_->setRegClass(DstReg, NewRC);
1236 mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
1237 }
17031238
17041239 // Remember to delete the copy instruction.
17051240 JoinedCopies.insert(CopyMI);
17061241
1707 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1242 UpdateRegDefsUses(CP);
17081243
17091244 // If we have extended the live range of a physical register, make sure we
17101245 // update live-in lists as well.
1711 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1712 const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
1246 if (CP.isPhys()) {
17131247 SmallVector BlockSeq;
1714 for (LiveInterval::const_iterator I = VRegInterval.begin(),
1715 E = VRegInterval.end(); I != E; ++I ) {
1248 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1249 // ranges for this, and they are preserved.
1250 LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
1251 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1252 I != E; ++I ) {
17161253 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
17171254 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
17181255 MachineBasicBlock &block = *BlockSeq[idx];
1719 if (!block.isLiveIn(DstReg))
1720 block.addLiveIn(DstReg);
1256 if (!block.isLiveIn(CP.getDstReg()))
1257 block.addLiveIn(CP.getDstReg());
17211258 }
17221259 BlockSeq.clear();
17231260 }
17251262
17261263 // SrcReg is guarateed to be the register whose live interval that is
17271264 // being merged.
1728 li_->removeInterval(SrcReg);
1265 li_->removeInterval(CP.getSrcReg());
17291266
17301267 // Update regalloc hint.
1731 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1732
1733 // Manually deleted the live interval copy.
1734 if (SavedLI) {
1735 SavedLI->clear();
1736 SavedLI.reset();
1737 }
1738
1739 // If resulting interval has a preference that no longer fits because of subreg
1740 // coalescing, just clear the preference.
1741 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1742 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1743 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1744 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1745 if (!RC->contains(Preference))
1746 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1747 }
1268 tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
17481269
17491270 DEBUG({
1750 dbgs() << "\t\tJoined. Result = ";
1751 ResDstInt->print(dbgs(), tri_);
1752 dbgs() << "\n";
1753 });
1271 LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
1272 dbgs() << "\tJoined. Result = ";
1273 DstInt.print(dbgs(), tri_);
1274 dbgs() << "\n";
1275 });
17541276
17551277 ++numJoins;
17561278 return true;
18081330 }
18091331
18101332 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1811 /// returns false. Otherwise, if one of the intervals being joined is a
1812 /// physreg, this method always canonicalizes LHS to be it. The output
1813 /// "RHS" will not have been modified, so we can use this information
1814 /// below to update aliases.
1815 bool
1816 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
1817 bool &Swapped, CoalescerPair &CP) {
1818 // Compute the final value assignment, assuming that the live ranges can be
1819 // coalesced.
1820 SmallVector LHSValNoAssignments;
1821 SmallVector RHSValNoAssignments;
1822 DenseMap LHSValsDefinedFromRHS;
1823 DenseMap RHSValsDefinedFromLHS;
1824 SmallVector NewVNInfo;
1333 /// returns false.
1334 bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
1335 LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
1336 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
1337
1338 // FIXME: Join into CP.getDstReg instead of CP.getOrigDstReg.
1339 // When looking at
1340 // %reg2000 = EXTRACT_SUBREG %EAX, sub_16bit
1341 // we really want to join %reg2000 with %AX ( = CP.getDstReg). We are actually
1342 // joining into %EAX ( = CP.getOrigDstReg) because it is guaranteed to have an
1343 // existing live interval, and we are better equipped to handle interference.
1344 // JoinCopy cleans up the mess by taking a copy of RHS before calling here,
1345 // and merging that copy into CP.getDstReg after.
18251346
18261347 // If a live interval is a physical register, conservatively check if any
18271348 // of its sub-registers is overlapping the live interval of the virtual
18281349 // register. If so, do not coalesce.
1829 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1830 *tri_->getSubRegisters(LHS.reg)) {
1350 if (CP.isPhys() && *tri_->getSubRegisters(CP.getOrigDstReg())) {
18311351 // If it's coalescing a virtual register to a physical register, estimate
18321352 // its live interval length. This is the *cost* of scanning an entire live
18331353 // interval. If the cost is low, we'll do an exhaustive check instead.
18471367 li_->intervalIsInOneMBB(RHS) &&
18481368 li_->getApproximateInstructionCount(RHS) <= 10) {
18491369 // Perform a more exhaustive check for some common cases.
1850 if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
1370 if (li_->conflictsWithAliasRef(RHS, CP.getOrigDstReg(), JoinedCopies))
18511371 return false;
18521372 } else {
1853 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1373 for (const unsigned* SR = tri_->getAliasSet(CP.getOrigDstReg()); *SR;
1374 ++SR)
18541375 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
18551376 DEBUG({
18561377 dbgs() << "\tInterfere with sub-register ";
18591380 return false;
18601381 }
18611382 }
1862 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1863 *tri_->getSubRegisters(RHS.reg)) {
1864 if (LHS.containsOneValue() &&
1865 li_->getApproximateInstructionCount(LHS) <= 10) {
1866 // Perform a more exhaustive check for some common cases.
1867 if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
1868 return false;
1869 } else {
1870 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1871 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1872 DEBUG({
1873 dbgs() << "\tInterfere with sub-register ";
1874 li_->getInterval(*SR).print(dbgs(), tri_);
1875 });
1876 return false;
1877 }
1878 }
1879 }
1383 }
1384
1385 // Compute the final value assignment, assuming that the live ranges can be
1386 // coalesced.
1387 SmallVector LHSValNoAssignments;
1388 SmallVector RHSValNoAssignments;
1389 DenseMap LHSValsDefinedFromRHS;
1390 DenseMap RHSValsDefinedFromLHS;
1391 SmallVector NewVNInfo;
1392
1393 LiveInterval &LHS = li_->getInterval(CP.getOrigDstReg());
1394 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
18801395
18811396 // Loop over the value numbers of the LHS, seeing if any are defined from
18821397 // the RHS.
19661481 LiveInterval::const_iterator JE = RHS.end();
19671482
19681483 // Skip ahead until the first place of potential sharing.
1969 if (I->start < J->start) {
1970 I = std::upper_bound(I, IE, J->start);
1971 if (I != LHS.begin()) --I;
1972 } else if (J->start < I->start) {
1973 J = std::upper_bound(J, JE, I->start);
1974 if (J != RHS.begin()) --J;
1975 }
1976
1977 while (1) {
1484 if (I != IE && J != JE) {
1485 if (I->start < J->start) {
1486 I = std::upper_bound(I, IE, J->start);
1487 if (I != LHS.begin()) --I;
1488 } else if (J->start < I->start) {
1489 J = std::upper_bound(J, JE, I->start);
1490 if (J != RHS.begin()) --J;
1491 }
1492 }
1493
1494 while (I != IE && J != JE) {
19781495 // Determine if these two live ranges overlap.
19791496 bool Overlaps;
19801497 if (I->start < J->start) {
19961513 return false;
19971514 }
19981515
1999 if (I->end < J->end) {
1516 if (I->end < J->end)
20001517 ++I;
2001 if (I == IE) break;
2002 } else {
1518 else
20031519 ++J;
2004 if (J == JE) break;
2005 }
20061520 }
20071521
20081522 // Update kill info. Some live ranges are extended due to copy coalescing.
20271541 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
20281542 }
20291543
1544 if (LHSValNoAssignments.empty())
1545 LHSValNoAssignments.push_back(-1);
1546 if (RHSValNoAssignments.empty())
1547 RHSValNoAssignments.push_back(-1);
1548
20301549 // If we get here, we know that we can coalesce the live ranges. Ask the
20311550 // intervals to coalesce themselves now.
2032 if ((RHS.ranges.size() > LHS.ranges.size() &&
2033 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2034 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2035 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2036 mri_);
2037 Swapped = true;
2038 } else {
2039 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2040 mri_);
2041 Swapped = false;
2042 }
1551 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1552 mri_);
20431553 return true;
20441554 }
20451555
23191829 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
23201830 assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
23211831 MI->isSubregToReg()) && "Unrecognized copy instruction");
2322 DstReg = MI->getOperand(0).getReg();
2323 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
1832 SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1833 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
23241834 // Do not delete extract_subreg, insert_subreg of physical
23251835 // registers unless the definition is dead. e.g.
23261836 // %DO = INSERT_SUBREG %D0, %S0, 1
23291839 DoDelete = false;
23301840 }
23311841 if (MI->allDefsAreDead()) {
2332 LiveInterval &li = li_->getInterval(DstReg);
1842 LiveInterval &li = li_->getInterval(SrcReg);
23331843 if (!ShortenDeadCopySrcLiveRange(li, MI))
23341844 ShortenDeadCopyLiveRange(li, MI);
23351845 DoDelete = true;
23871897 if (MI->registerDefIsDead(DstReg)) {
23881898 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
23891899 ShortenDeadCopyLiveRange(RegInt, MI);
1900 } else {
1901 // If a value is killed here remove the marker.
1902 SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex();
1903 if (const LiveRange *LR = RegInt.getLiveRangeContaining(UseIdx))
1904 LR->valno->removeKill(UseIdx.getDefIndex());
23901905 }
23911906 }
23921907 li_->RemoveMachineInstrFromMaps(MI);
104104 /// possible to coalesce this interval, but it may be possible if other
105105 /// things get coalesced, then it returns true by reference in 'Again'.
106106 bool JoinCopy(CopyRec &TheCopy, bool &Again);
107
107
108108 /// JoinIntervals - Attempt to join these two intervals. On failure, this
109 /// returns false. Otherwise, if one of the intervals being joined is a
110 /// physreg, this method always canonicalizes DestInt to be it. The output
111 /// "SrcInt" will not have been modified, so we can use this information
112 /// below to update aliases.
113 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped,
114 CoalescerPair &CP);
109 /// returns false. The output "SrcInt" will not have been modified, so we can
110 /// use this information below to update aliases.
111 bool JoinIntervals(CoalescerPair &CP);
115112
116113 /// Return true if the two specified registers belong to different register
117114 /// classes. The registers may be either phys or virt regs.
148145 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
149146 unsigned DstSubIdx, MachineInstr *CopyMI);
150147
151 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
152 /// from an implicit def to another register can be coalesced away.
153 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
154 LiveInterval &li, LiveInterval &ImpLi) const;
155
156148 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
157149 /// two virtual registers from different register classes.
158150 bool isWinToJoinCrossClass(unsigned SrcReg,
161153 const TargetRegisterClass *DstRC,
162154 const TargetRegisterClass *NewRC);
163155
164 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
165 /// register with a physical register, check if any of the virtual register
166 /// operand is a sub-register use or def. If so, make sure it won't result
167 /// in an illegal extract_subreg or insert_subreg instruction.
168 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
169 unsigned VirtReg, unsigned PhysReg);
170
171 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
172 /// an extract_subreg where dst is a physical register, e.g.
173 /// cl = EXTRACT_SUBREG reg1024, 1
174 bool CanJoinExtractSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
175 unsigned SubIdx, unsigned &RealDstReg);
176
177 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
178 /// an insert_subreg where src is a physical register, e.g.
179 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
180 bool CanJoinInsertSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
181 unsigned SubIdx, unsigned &RealDstReg);
182
183156 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
184157 /// update the subregister number if it is not zero. If DstReg is a
185158 /// physical register and the existing subregister number of the def / use
186159 /// being updated is not zero, make sure to set it to the correct physical
187160 /// subregister.
188 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
161 void UpdateRegDefsUses(const CoalescerPair &CP);
189162
190163 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
191164 /// Return true if live interval is removed.
202175 /// it as well.
203176 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
204177
178 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
179 /// VNInfo copy flag for DstReg and all aliases.
180 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
181
205182 /// lastRegisterUse - Returns the last use of the specific register between
206183 /// cycles Start and End or NULL if there are no uses.
207184 MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End,
203203
204204 define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
205205 ;CHECK: test_vset_lanef32:
206 ;CHECK: vmov.f32
207 ;CHECK: vmov.f32
206 ;CHECK: vmov.f32 s3, s0
207 ;CHECK: vmov.f64 d0, d1
208208 entry:
209209 %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
210210 ret <2 x float> %0