llvm.org GIT mirror llvm / a23ecc2
ARM fix cc_out operand handling for t2SUBrr instructions. We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
3 changed file(s) with 19 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
39833983 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
39843984 def : t2InstAlias<"sub${p} $Rdn, $imm",
39853985 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3986 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
3987 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
39863988 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
39873989 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
39883990 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
39893991 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
39903992 pred:$p, cc_out:$s)>;
3991
39923993
39933994 // Alias for compares without the ".w" optional width specifier.
39943995 def : t2InstAlias<"cmn${p} $Rn, $Rm",
47694769 static_cast(Operands[4])->isReg() &&
47704770 static_cast(Operands[4])->getReg() == ARM::SP &&
47714771 static_cast(Operands[1])->getReg() == 0 &&
4772 (static_cast(Operands[5])->isReg() ||
4772 ((Mnemonic == "add" &&static_cast(Operands[5])->isReg()) ||
47734773 static_cast(Operands[5])->isImm0_1020s4()))
47744774 return true;
47754775 // For Thumb2, add/sub immediate does not have a cc_out operand for the
48534853 (Operands.size() == 5 || Operands.size() == 6) &&
48544854 static_cast(Operands[3])->isReg() &&
48554855 static_cast(Operands[3])->getReg() == ARM::SP &&
4856 static_cast(Operands[1])->getReg() == 0)
4856 static_cast(Operands[1])->getReg() == 0 &&
4857 (static_cast(Operands[4])->isImm() ||
4858 (Operands.size() == 6 &&
4859 static_cast(Operands[5])->isImm())))
48574860 return true;
48584861
48594862 return false;
26852685 sub r4, r5, r6, asr #5
26862686 sub r4, r5, r6, ror #5
26872687 sub.w r5, r2, r12, rrx
2688 sub r2, sp, ip
2689 sub sp, sp, ip
2690 sub sp, ip
2691 sub.w r2, sp, ip
2692 sub.w sp, sp, ip
2693 sub.w sp, ip
26882694
26892695 @ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04]
26902696 @ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14]
26932699 @ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14]
26942700 @ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14]
26952701 @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
2702 @ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02]
2703 @ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
2704 @ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
2705 @ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02]
2706 @ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
2707 @ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
26962708
26972709
26982710 @------------------------------------------------------------------------------