llvm.org GIT mirror llvm / a21de3b
[ARM][AsmParser] Improve debug printing of parsed asm operands In ARMOperand::print: - Print human-readable register names, instead of numbers. - Print the correct names for IT condition masks (these were in the wrong order before). - Print all parts of memory operands, not just the base register. This makes the output of llvm-mc -show-inst-operands more readable. Differential revision: https://reviews.llvm.org/D54850 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347494 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 1 year, 8 months ago
1 changed file(s) with 39 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
77 //===----------------------------------------------------------------------===//
88
99 #include "ARMFeatures.h"
10 #include "InstPrinter/ARMInstPrinter.h"
1011 #include "Utils/ARMBaseInfo.h"
1112 #include "MCTargetDesc/ARMAddressingModes.h"
1213 #include "MCTargetDesc/ARMBaseInfo.h"
32043205 } // end anonymous namespace.
32053206
32063207 void ARMOperand::print(raw_ostream &OS) const {
3208 auto RegName = [](unsigned Reg) {
3209 if (Reg)
3210 return ARMInstPrinter::getRegisterName(Reg);
3211 else
3212 return "noreg";
3213 };
3214
32073215 switch (Kind) {
32083216 case k_CondCode:
32093217 OS << "";
32103218 break;
32113219 case k_CCOut:
3212 OS << "getReg() << ">";
3220 OS << "RegName(getReg()) << ">";
32133221 break;
32143222 case k_ITCondMask: {
32153223 static const char *const MaskStr[] = {
3216 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
3217 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
3224 "(invalid)", "(teee)", "(tee)", "(teet)",
3225 "(te)", "(tete)", "(tet)", "(tett)",
3226 "(t)", "(ttee)", "(tte)", "(ttet)",
3227 "(tt)", "(ttte)", "(ttt)", "(tttt)"
32183228 };
32193229 assert((ITMask.Mask & 0xf) == ITMask.Mask);
32203230 OS << "";
32483258 OS << "";
32493259 break;
32503260 case k_Memory:
3251 OS << "
3252 << " base:" << Memory.BaseRegNum;
3261 OS << ";
3262 if (Memory.BaseRegNum)
3263 OS << " base:" << RegName(Memory.BaseRegNum);
3264 if (Memory.OffsetImm)
3265 OS << " offset-imm:" << *Memory.OffsetImm;
3266 if (Memory.OffsetRegNum)
3267 OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3268 << RegName(Memory.OffsetRegNum);
3269 if (Memory.ShiftType != ARM_AM::no_shift) {
3270 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3271 OS << " shift-imm:" << Memory.ShiftImm;
3272 }
3273 if (Memory.Alignment)
3274 OS << " alignment:" << Memory.Alignment;
32533275 OS << ">";
32543276 break;
32553277 case k_PostIndexRegister:
32563278 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3257 << PostIdxReg.RegNum;
3279 << RegName(PostIdxReg.RegNum);
32583280 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
32593281 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
32603282 << PostIdxReg.ShiftImm;
32703292 break;
32713293 }
32723294 case k_Register:
3273 OS << "getReg() << ">";
3295 OS << "RegName(getReg()) << ">";
32743296 break;
32753297 case k_ShifterImmediate:
32763298 OS << "
32773299 << " #" << ShifterImm.Imm << ">";
32783300 break;
32793301 case k_ShiftedRegister:
3280 OS << "
3281 << RegShiftedReg.SrcReg << " "
3282 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
3283 << " " << RegShiftedReg.ShiftReg << ">";
3302 OS << "
3303 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3304 << RegName(RegShiftedReg.ShiftReg) << ">";
32843305 break;
32853306 case k_ShiftedImmediate:
3286 OS << "
3287 << RegShiftedImm.SrcReg << " "
3288 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
3289 << " #" << RegShiftedImm.ShiftImm << ">";
3307 OS << "
3308 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3309 << RegShiftedImm.ShiftImm << ">";
32903310 break;
32913311 case k_RotateImmediate:
32923312 OS << "";
33103330 const SmallVectorImpl &RegList = getRegList();
33113331 for (SmallVectorImpl::const_iterator
33123332 I = RegList.begin(), E = RegList.end(); I != E; ) {
3313 OS << *I;
3333 OS << RegName(*I);
33143334 if (++I < E) OS << ", ";
33153335 }
33163336
33193339 }
33203340 case k_VectorList:
33213341 OS << "
3322 << VectorList.RegNum << ">";
3342 << RegName(VectorList.RegNum) << ">";
33233343 break;
33243344 case k_VectorListAllLanes:
33253345 OS << "
3326 << VectorList.RegNum << ">";
3346 << RegName(VectorList.RegNum) << ">";
33273347 break;
33283348 case k_VectorListIndexed:
33293349 OS << "
3330 << VectorList.Count << " * " << VectorList.RegNum << ">";
3350 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
33313351 break;
33323352 case k_Token:
33333353 OS << "'" << getToken() << "'";