llvm.org GIT mirror llvm / a1eb155
Use subregs to improve any_extend code generation when feasible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41013 91177308-0d34-0410-b5e6-96231b3b80d8 Christopher Lamb 12 years ago
3 changed file(s) with 35 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
134134
135135 N: Christopher Lamb
136136 E: christopher.lamb@gmail.com
137 D: aligned load/store support
137 D: aligned load/store support, parts of noalias and restrict support
138 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
138139
139140 N: Jim Laskey
140141 E: jlaskey@apple.com
531531
532532 //===---------------------------------------------------------------------===//
533533
534 Don't forget to find a way to squash noop truncates in the JIT environment.
535
536 //===---------------------------------------------------------------------===//
537
538 Implement anyext in the same manner as truncate that would allow them to be
539 eliminated.
540
541 //===---------------------------------------------------------------------===//
542
543 How about implementing truncate / anyext as a property of machine instruction
544 operand? i.e. Print as 32-bit super-class register / 16-bit sub-class register.
545 Do this for the cases where a truncate / anyext is guaranteed to be eliminated.
546 For IA32 that is truncate from 32 to 16 and anyext from 16 to 32.
547
548 //===---------------------------------------------------------------------===//
549
550534 For this:
551535
552536 int test(int a)
13711371
13721372 return NULL;
13731373 }
1374
1375 case ISD::ANY_EXTEND: {
1376 SDOperand N0 = Node->getOperand(0);
1377 AddToISelQueue(N0);
1378 if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) {
1379 SDOperand SRIdx;
1380 switch(N0.getValueType()) {
1381 case MVT::i32:
1382 SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
1383 break;
1384 case MVT::i16:
1385 SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
1386 break;
1387 case MVT::i8:
1388 if (Subtarget->is64Bit())
1389 SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1390 break;
1391 default: assert(0 && "Unknown any_extend!");
1392 }
1393 if (SRIdx.Val) {
1394 SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG, NVT, N0, SRIdx);
1395
1396 #ifndef NDEBUG
1397 DOUT << std::string(Indent-2, ' ') << "=> ";
1398 DEBUG(ResNode->dump(CurDAG));
1399 DOUT << "\n";
1400 Indent -= 2;
1401 #endif
1402 return ResNode;
1403 } // Otherwise let generated ISel handle it.
1404 }
1405 break;
1406 }
13741407
13751408 case ISD::SIGN_EXTEND_INREG: {
13761409 SDOperand N0 = Node->getOperand(0);