llvm.org GIT mirror llvm / a1d410d
Add an ARM RSCrr instruction for disassembly only. Partial fix for PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
2 changed file(s) with 12 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
16711671 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
16721672 Requires<[IsARM]> {
16731673 let Inst{25} = 1;
1674 }
1675 // The reg/reg form is only defined for the disassembler; for codegen it is
1676 // equivalent to SUBrr.
1677 def RSCrr : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1678 DPFrm, IIC_iALUr, "rsc", "\t$dst, $a, $b",
1679 [/* For disassembly only; pattern left blank */]> {
1680 let Inst{25} = 0;
1681 let Inst{11-4} = 0b00000000;
16741682 }
16751683 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
16761684 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
6464 # CHECK: rsbeq r0, r2, r0
6565 0x00 0x00 0x62 0x00
6666
67 # CHECK-NOT: rsceqs r0, r0, r1, lsl #0
68 # CHECK: rsceqs r0, r0, r1
69 0x01 0x00 0xf0 0x00
70
6771 # CHECK: sbcs r0, pc, #1
6872 0x01 0x00 0xdf 0xe2
6973