llvm.org GIT mirror llvm / a17768f
Create a new LiveRangeEdit class to keep track of the new registers created when splitting or spillling, and to help with rematerialization. Use LiveRangeEdit in InlineSpiller and SplitKit. This will eventually make it possible to share remat code between InlineSpiller and SplitKit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116543 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
6 changed file(s) with 210 addition(s) and 129 deletion(s). Raw diff Collapse all Expand all
2222 LiveIntervalAnalysis.cpp
2323 LiveStackAnalysis.cpp
2424 LiveVariables.cpp
25 LiveRangeEdit.cpp
2526 LocalStackSlotAllocation.cpp
2627 LowerSubregs.cpp
2728 MachineBasicBlock.cpp
1313
1414 #define DEBUG_TYPE "spiller"
1515 #include "Spiller.h"
16 #include "LiveRangeEdit.h"
1617 #include "SplitKit.h"
1718 #include "VirtRegMap.h"
1819 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
4344 SplitAnalysis splitAnalysis_;
4445
4546 // Variables that are valid during spill(), but used by multiple methods.
46 LiveInterval *li_;
47 SmallVectorImpl *newIntervals_;
47 LiveRangeEdit *edit_;
4848 const TargetRegisterClass *rc_;
4949 int stackSlot_;
50 const SmallVectorImpl *spillIs_;
5150
5251 // Values of the current interval that can potentially remat.
5352 SmallPtrSet reMattable_;
7776 SmallVectorImpl &newIntervals,
7877 SmallVectorImpl &spillIs);
7978
79 void spill(LiveRangeEdit &);
80
8081 private:
8182 bool split();
8283
83 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
84 SlotIndex UseIdx);
8584 bool reMaterializeFor(MachineBasicBlock::iterator MI);
8685 void reMaterializeAll();
8786
104103 /// split - try splitting the current interval into pieces that may allocate
105104 /// separately. Return true if successful.
106105 bool InlineSpiller::split() {
107 splitAnalysis_.analyze(li_);
106 splitAnalysis_.analyze(&edit_->getParent());
108107
109108 // Try splitting around loops.
110109 if (const MachineLoop *loop = splitAnalysis_.getBestSplitLoop()) {
111 SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
110 SplitEditor(splitAnalysis_, lis_, vrm_, *edit_)
112111 .splitAroundLoop(loop);
113112 return true;
114113 }
116115 // Try splitting into single block intervals.
117116 SplitAnalysis::BlockPtrSet blocks;
118117 if (splitAnalysis_.getMultiUseBlocks(blocks)) {
119 SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
118 SplitEditor(splitAnalysis_, lis_, vrm_, *edit_)
120119 .splitSingleBlocks(blocks);
121120 return true;
122121 }
123122
124123 // Try splitting inside a basic block.
125124 if (const MachineBasicBlock *MBB = splitAnalysis_.getBlockForInsideSplit()) {
126 SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
125 SplitEditor(splitAnalysis_, lis_, vrm_, *edit_)
127126 .splitInsideBlock(MBB);
128127 return true;
129128 }
131130 return false;
132131 }
133132
134 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
135 /// OrigIdx are also available with the same value at UseIdx.
136 bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
137 SlotIndex OrigIdx,
138 SlotIndex UseIdx) {
139 OrigIdx = OrigIdx.getUseIndex();
140 UseIdx = UseIdx.getUseIndex();
141 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
142 const MachineOperand &MO = OrigMI->getOperand(i);
143 if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
144 continue;
145 // Reserved registers are OK.
146 if (MO.isUndef() || !lis_.hasInterval(MO.getReg()))
147 continue;
148 // We don't want to move any defs.
149 if (MO.isDef())
150 return false;
151 // We cannot depend on virtual registers in spillIs_. They will be spilled.
152 for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
153 if ((*spillIs_)[si]->reg == MO.getReg())
154 return false;
155
156 LiveInterval &LI = lis_.getInterval(MO.getReg());
157 const VNInfo *OVNI = LI.getVNInfoAt(OrigIdx);
158 if (!OVNI)
159 continue;
160 if (OVNI != LI.getVNInfoAt(UseIdx))
161 return false;
162 }
163 return true;
164 }
165
166 /// reMaterializeFor - Attempt to rematerialize li_->reg before MI instead of
133 /// reMaterializeFor - Attempt to rematerialize edit_->getReg() before MI instead of
167134 /// reloading it.
168135 bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
169136 SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
170 VNInfo *OrigVNI = li_->getVNInfoAt(UseIdx);
137 VNInfo *OrigVNI = edit_->getParent().getVNInfoAt(UseIdx);
171138 if (!OrigVNI) {
172139 DEBUG(dbgs() << "\tadding flags: ");
173140 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
174141 MachineOperand &MO = MI->getOperand(i);
175 if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
142 if (MO.isReg() && MO.isUse() && MO.getReg() == edit_->getReg())
176143 MO.setIsUndef();
177144 }
178145 DEBUG(dbgs() << UseIdx << '\t' << *MI);
184151 return false;
185152 }
186153 MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
187 if (!allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx)) {
154 if (!edit_->allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx, lis_)) {
188155 usedValues_.insert(OrigVNI);
189156 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
190157 return false;
191158 }
192159
193 // If the instruction also writes li_->reg, it had better not require the same
160 // If the instruction also writes edit_->getReg(), it had better not require the same
194161 // register for uses and defs.
195162 bool Reads, Writes;
196163 SmallVector Ops;
197 tie(Reads, Writes) = MI->readsWritesVirtualRegister(li_->reg, &Ops);
164 tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit_->getReg(), &Ops);
198165 if (Writes) {
199166 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
200167 MachineOperand &MO = MI->getOperand(Ops[i]);
207174 }
208175
209176 // Alocate a new register for the remat.
210 unsigned NewVReg = mri_.createVirtualRegister(rc_);
211 vrm_.grow();
212 LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
177 LiveInterval &NewLI = edit_->create(mri_, lis_, vrm_);
213178 NewLI.markNotSpillable();
214 newIntervals_->push_back(&NewLI);
215179
216180 // Finally we can rematerialize OrigMI before MI.
217181 MachineBasicBlock &MBB = *MI->getParent();
223187 // Replace operands
224188 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
225189 MachineOperand &MO = MI->getOperand(Ops[i]);
226 if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg) {
227 MO.setReg(NewVReg);
190 if (MO.isReg() && MO.isUse() && MO.getReg() == edit_->getReg()) {
191 MO.setReg(NewLI.reg);
228192 MO.setIsKill();
229193 }
230194 }
236200 return true;
237201 }
238202
239 /// reMaterializeAll - Try to rematerialize as many uses of li_ as possible,
203 /// reMaterializeAll - Try to rematerialize as many uses as possible,
240204 /// and trim the live ranges after.
241205 void InlineSpiller::reMaterializeAll() {
242206 // Do a quick scan of the interval values to find if any are remattable.
243207 reMattable_.clear();
244208 usedValues_.clear();
245 for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
246 E = li_->vni_end(); I != E; ++I) {
209 for (LiveInterval::const_vni_iterator I = edit_->getParent().vni_begin(),
210 E = edit_->getParent().vni_end(); I != E; ++I) {
247211 VNInfo *VNI = *I;
248212 if (VNI->isUnused())
249213 continue;
257221 if (reMattable_.empty())
258222 return;
259223
260 // Try to remat before all uses of li_->reg.
224 // Try to remat before all uses of edit_->getReg().
261225 bool anyRemat = false;
262226 for (MachineRegisterInfo::use_nodbg_iterator
263 RI = mri_.use_nodbg_begin(li_->reg);
227 RI = mri_.use_nodbg_begin(edit_->getReg());
264228 MachineInstr *MI = RI.skipInstruction();)
265229 anyRemat |= reMaterializeFor(MI);
266230
286250 if (!anyRemoved)
287251 return;
288252
289 // Removing values may cause debug uses where li_ is not live.
290 for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(li_->reg);
253 // Removing values may cause debug uses where parent is not live.
254 for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(edit_->getReg());
291255 MachineInstr *MI = RI.skipInstruction();) {
292256 if (!MI->isDebugValue())
293257 continue;
294 // Try to preserve the debug value if li_ is live immediately after it.
258 // Try to preserve the debug value if parent is live immediately after it.
295259 MachineBasicBlock::iterator NextMI = MI;
296260 ++NextMI;
297261 if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
298 VNInfo *VNI = li_->getVNInfoAt(lis_.getInstructionIndex(NextMI));
262 SlotIndex Idx = lis_.getInstructionIndex(NextMI);
263 VNInfo *VNI = edit_->getParent().getVNInfoAt(Idx);
299264 if (VNI && (VNI->hasPHIKill() || usedValues_.count(VNI)))
300265 continue;
301266 }
313278 return false;
314279
315280 // We have a stack access. Is it the right register and slot?
316 if (reg != li_->reg || FI != stackSlot_)
281 if (reg != edit_->getReg() || FI != stackSlot_)
317282 return false;
318283
319284 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
384349 void InlineSpiller::spill(LiveInterval *li,
385350 SmallVectorImpl &newIntervals,
386351 SmallVectorImpl &spillIs) {
387 DEBUG(dbgs() << "Inline spilling " << *li << "\n");
388 assert(li->isSpillable() && "Attempting to spill already spilled value.");
389 assert(!li->isStackSlot() && "Trying to spill a stack slot.");
390
391 li_ = li;
392 newIntervals_ = &newIntervals;
393 rc_ = mri_.getRegClass(li->reg);
394 spillIs_ = &spillIs;
352 LiveRangeEdit edit(*li, newIntervals, spillIs);
353 spill(edit);
354 }
355
356 void InlineSpiller::spill(LiveRangeEdit &edit) {
357 edit_ = &edit;
358 DEBUG(dbgs() << "Inline spilling " << edit.getParent() << "\n");
359 assert(edit.getParent().isSpillable() &&
360 "Attempting to spill already spilled value.");
361 assert(!edit.getParent().isStackSlot() && "Trying to spill a stack slot.");
395362
396363 if (split())
397364 return;
399366 reMaterializeAll();
400367
401368 // Remat may handle everything.
402 if (li_->empty())
369 if (edit_->getParent().empty())
403370 return;
404371
405 stackSlot_ = vrm_.getStackSlot(li->reg);
372 rc_ = mri_.getRegClass(edit.getReg());
373 stackSlot_ = vrm_.getStackSlot(edit.getReg());
406374 if (stackSlot_ == VirtRegMap::NO_STACK_SLOT)
407 stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
375 stackSlot_ = vrm_.assignVirt2StackSlot(edit.getReg());
408376
409377 // Iterate over instructions using register.
410 for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
378 for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(edit.getReg());
411379 MachineInstr *MI = RI.skipInstruction();) {
412380
413381 // Debug values are not allowed to affect codegen.
435403 // Analyze instruction.
436404 bool Reads, Writes;
437405 SmallVector Ops;
438 tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
406 tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit.getReg(), &Ops);
439407
440408 // Attempt to fold memory ops.
441409 if (foldMemoryOperand(MI, Ops))
443411
444412 // Allocate interval around instruction.
445413 // FIXME: Infer regclass from instruction alone.
446 unsigned NewVReg = mri_.createVirtualRegister(rc_);
447 vrm_.grow();
448 LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
414 LiveInterval &NewLI = edit.create(mri_, lis_, vrm_);
449415 NewLI.markNotSpillable();
450416
451417 if (Reads)
455421 bool hasLiveDef = false;
456422 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
457423 MachineOperand &MO = MI->getOperand(Ops[i]);
458 MO.setReg(NewVReg);
424 MO.setReg(NewLI.reg);
459425 if (MO.isUse()) {
460426 if (!MI->isRegTiedToDefOperand(Ops[i]))
461427 MO.setIsKill();
470436 insertSpill(NewLI, MI);
471437
472438 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
473 newIntervals.push_back(&NewLI);
474 }
475 }
439 }
440 }
0 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //===----------------------------------------------------------------------===//
12
13 #include "LiveRangeEdit.h"
14 #include "VirtRegMap.h"
15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17
18 using namespace llvm;
19
20 LiveInterval &LiveRangeEdit::create(MachineRegisterInfo &mri,
21 LiveIntervals &lis,
22 VirtRegMap &vrm) {
23 const TargetRegisterClass *RC = mri.getRegClass(parent_.reg);
24 unsigned VReg = mri.createVirtualRegister(RC);
25 vrm.grow();
26 LiveInterval &li = lis.getOrCreateInterval(VReg);
27 newRegs_.push_back(&li);
28 return li;
29 }
30
31 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
32 /// OrigIdx are also available with the same value at UseIdx.
33 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
34 SlotIndex OrigIdx,
35 SlotIndex UseIdx,
36 LiveIntervals &lis) {
37 OrigIdx = OrigIdx.getUseIndex();
38 UseIdx = UseIdx.getUseIndex();
39 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
40 const MachineOperand &MO = OrigMI->getOperand(i);
41 if (!MO.isReg() || !MO.getReg() || MO.getReg() == getReg())
42 continue;
43 // Reserved registers are OK.
44 if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
45 continue;
46 // We don't want to move any defs.
47 if (MO.isDef())
48 return false;
49 // We cannot depend on virtual registers in uselessRegs_.
50 for (unsigned ui = 0, ue = uselessRegs_.size(); ui != ue; ++ui)
51 if (uselessRegs_[ui]->reg == MO.getReg())
52 return false;
53
54 LiveInterval &li = lis.getInterval(MO.getReg());
55 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
56 if (!OVNI)
57 continue;
58 if (OVNI != li.getVNInfoAt(UseIdx))
59 return false;
60 }
61 return true;
62 }
63
0 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //
12 // The parent register is never changed. Instead, a number of new virtual
13 // registers are created and added to the newRegs vector.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
18 #define LLVM_CODEGEN_LIVERANGEEDIT_H
19
20 #include "llvm/CodeGen/LiveInterval.h"
21
22 namespace llvm {
23
24 class LiveIntervals;
25 class MachineRegisterInfo;
26 class VirtRegMap;
27
28 class LiveRangeEdit {
29 LiveInterval &parent_;
30 SmallVectorImpl &newRegs_;
31 const SmallVectorImpl &uselessRegs_;
32
33 /// firstNew_ - Index of the first register added to newRegs_.
34 const unsigned firstNew_;
35
36 public:
37 /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
38 /// @param parent The register being spilled or split.
39 /// @param newRegs List to receive any new registers created. This needn't be
40 /// empty initially, any existing registers are ignored.
41 /// @param uselessRegs List of registers that can't be used when
42 /// rematerializing values because they are about to be removed.
43 LiveRangeEdit(LiveInterval &parent,
44 SmallVectorImpl &newRegs,
45 const SmallVectorImpl &uselessRegs)
46 : parent_(parent), newRegs_(newRegs), uselessRegs_(uselessRegs),
47 firstNew_(newRegs.size()) {}
48
49 LiveInterval &getParent() const { return parent_; }
50 unsigned getReg() const { return parent_.reg; }
51
52 /// Iterator for accessing the new registers added by this edit.
53 typedef SmallVectorImpl::const_iterator iterator;
54 iterator begin() const { return newRegs_.begin()+firstNew_; }
55 iterator end() const { return newRegs_.end(); }
56
57 /// create - Create a new register with the same class as parentReg_.
58 LiveInterval &create(MachineRegisterInfo&, LiveIntervals&, VirtRegMap&);
59
60 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
61 /// OrigIdx are also available with the same value at UseIdx.
62 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
63 SlotIndex UseIdx, LiveIntervals &lis);
64
65 };
66
67 }
68
69 #endif
1313
1414 #define DEBUG_TYPE "splitter"
1515 #include "SplitKit.h"
16 #include "LiveRangeEdit.h"
1617 #include "VirtRegMap.h"
1718 #include "llvm/CodeGen/CalcSpillWeights.h"
1819 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
579580
580581 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
581582 SplitEditor::SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm,
582 SmallVectorImpl &intervals)
583 LiveRangeEdit &edit)
583584 : sa_(sa), lis_(lis), vrm_(vrm),
584585 mri_(vrm.getMachineFunction().getRegInfo()),
585586 tii_(*vrm.getMachineFunction().getTarget().getInstrInfo()),
587 edit_(edit),
586588 curli_(sa_.getCurLI()),
587589 dupli_(lis_, *curli_),
588 openli_(lis_, *curli_),
589 intervals_(intervals),
590 firstInterval(intervals_.size())
590 openli_(lis_, *curli_)
591591 {
592592 assert(curli_ && "SplitEditor created from empty SplitAnalysis");
593593
598598
599599 }
600600
601 LiveInterval *SplitEditor::createInterval() {
602 unsigned Reg = mri_.createVirtualRegister(mri_.getRegClass(curli_->reg));
603 LiveInterval &Intv = lis_.getOrCreateInterval(Reg);
604 vrm_.grow();
605 vrm_.assignVirt2StackSlot(Reg, vrm_.getStackSlot(curli_->reg));
606 return &Intv;
607 }
608
609601 bool SplitEditor::intervalsLiveAt(SlotIndex Idx) const {
610 for (int i = firstInterval, e = intervals_.size(); i != e; ++i)
611 if (intervals_[i]->liveAt(Idx))
602 for (LiveRangeEdit::iterator I = edit_.begin(), E = edit_.end(); I != E; ++I)
603 if (*I != dupli_.getLI() && (*I)->liveAt(Idx))
612604 return true;
613605 return false;
614606 }
618610 assert(!openli_.getLI() && "Previous LI not closed before openIntv");
619611
620612 if (!dupli_.getLI())
621 dupli_.reset(createInterval());
622
623 openli_.reset(createInterval());
624 intervals_.push_back(openli_.getLI());
613 dupli_.reset(&edit_.create(mri_, lis_, vrm_));
614
615 openli_.reset(&edit_.create(mri_, lis_, vrm_));
625616 }
626617
627618 /// enterIntvBefore - Enter openli before the instruction at Idx. If curli is
748739 SlotIndex Idx = lis_.getInstructionIndex(MI);
749740 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
750741 LiveInterval *LI = 0;
751 for (unsigned i = firstInterval, e = intervals_.size(); i != e; ++i) {
752 LiveInterval *testli = intervals_[i];
742 for (LiveRangeEdit::iterator I = edit_.begin(), E = edit_.end(); I != E;
743 ++I) {
744 LiveInterval *testli = *I;
753745 if (testli->liveAt(Idx)) {
754746 LI = testli;
755747 break;
768760 typedef std::pair
769761 LiveInterval::const_iterator> IIPair;
770762 SmallVector Iters;
771 for (int i = firstInterval, e = intervals_.size(); i != e; ++i) {
772 LiveInterval::const_iterator I = intervals_[i]->find(Start);
773 LiveInterval::const_iterator E = intervals_[i]->end();
763 for (LiveRangeEdit::iterator LI = edit_.begin(), LE = edit_.end(); LI != LE;
764 ++LI) {
765 LiveInterval::const_iterator I = (*LI)->find(Start);
766 LiveInterval::const_iterator E = (*LI)->end();
774767 if (I != E)
775768 Iters.push_back(std::make_pair(I, E));
776769 }
867860 if (unsigned NumComp = ConEQ.Classify(dupli_.getLI())) {
868861 DEBUG(dbgs() << " Remainder has " << NumComp << " connected components: "
869862 << *dupli_.getLI() << '\n');
870 unsigned firstComp = intervals_.size();
871 intervals_.push_back(dupli_.getLI());
872863 // Did the remainder break up? Create intervals for all the components.
873864 if (NumComp > 1) {
865 SmallVector dups;
866 dups.push_back(dupli_.getLI());
874867 for (unsigned i = 1; i != NumComp; ++i)
875 intervals_.push_back(createInterval());
876 ConEQ.Distribute(&intervals_[firstComp]);
868 dups.push_back(&edit_.create(mri_, lis_, vrm_));
869 ConEQ.Distribute(&dups[0]);
877870 // Rewrite uses to the new regs.
878871 rewrite(dupli_.getLI()->reg);
879872 }
880 } else {
881 DEBUG(dbgs() << " dupli became empty?\n");
882 lis_.removeInterval(dupli_.getLI()->reg);
883 dupli_.reset(0);
884873 }
885874
886875 // Rewrite instructions.
888877
889878 // Calculate spill weight and allocation hints for new intervals.
890879 VirtRegAuxInfo vrai(vrm_.getMachineFunction(), lis_, sa_.loops_);
891 for (unsigned i = firstInterval, e = intervals_.size(); i != e; ++i) {
892 LiveInterval &li = *intervals_[i];
880 for (LiveRangeEdit::iterator I = edit_.begin(), E = edit_.end(); I != E; ++I){
881 LiveInterval &li = **I;
893882 vrai.CalculateRegClass(li.reg);
894883 vrai.CalculateWeightAndHint(li);
895884 DEBUG(dbgs() << " new interval " << mri_.getRegClass(li.reg)->getName()
1919
2020 class LiveInterval;
2121 class LiveIntervals;
22 class LiveRangeEdit;
2223 class MachineInstr;
2324 class MachineLoop;
2425 class MachineLoopInfo;
237238 MachineRegisterInfo &mri_;
238239 const TargetInstrInfo &tii_;
239240
241 /// edit_ - The current parent register and new intervals created.
242 LiveRangeEdit &edit_;
243
240244 /// curli_ - The immutable interval we are currently splitting.
241245 const LiveInterval *const curli_;
242246
248252 /// Currently open LiveInterval.
249253 LiveIntervalMap openli_;
250254
251 /// createInterval - Create a new virtual register and LiveInterval with same
252 /// register class and spill slot as curli.
253 LiveInterval *createInterval();
254
255 /// All the new intervals created for this split are added to intervals_.
256 SmallVectorImpl &intervals_;
257
258 /// The index into intervals_ of the first interval we added. There may be
259 /// others from before we got it.
260 unsigned firstInterval;
261
262255 /// intervalsLiveAt - Return true if any member of intervals_ is live at Idx.
263256 bool intervalsLiveAt(SlotIndex Idx) const;
264257
280273 public:
281274 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
282275 /// Newly created intervals will be appended to newIntervals.
283 SplitEditor(SplitAnalysis &SA, LiveIntervals&, VirtRegMap&,
284 SmallVectorImpl &newIntervals);
276 SplitEditor(SplitAnalysis &SA, LiveIntervals&, VirtRegMap&, LiveRangeEdit&);
285277
286278 /// getAnalysis - Get the corresponding analysis.
287279 SplitAnalysis &getAnalysis() { return sa_; }