llvm.org GIT mirror llvm / a1571b7
[ARM] Add earlyclobber for cross beat MVE instructions rL367544 added @earlyclobbers for the MVE VREV64 instruction. This adds the same for a number of other 32bit instructions that are similarly unpredictable if the destination equals the source (due to the cross beat nature of the instructions). This includes: VCADD.f32 VCADD.i32 VCMUL.f32 VHCADD.s32 VMULLT/B.s/u32 VQDMLADH{X}.s32 VQRDMLADH{X}.s32 VQDMLSDH{X}.s32 VQRDMLSDH{X}.s32 VQDMULLT/B.s32 with Qm and Rm No tests here as this would require intrinsics (or very interesting codegen) to manifest. The tests will follow naturally as the intrinsics are added. Differential Revision: https://reviews.llvm.org/D67462 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371838 91177308-0d34-0410-b5e6-96231b3b80d8 David Green 1 year, 17 days ago
1 changed file(s) with 39 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
27242724 (v8f16 (MVE_VSUBf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
27252725 }
27262726
2727 class MVE_VCADDlist pattern=[]>
2727 class MVE_VCADDstring cstr="", list pattern=[]>
27282728 : MVEFloatArithNeon<"vcadd", suffix, size, (outs MQPR:$Qd),
27292729 (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
2730 "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
2730 "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
27312731 bits<4> Qd;
27322732 bits<4> Qn;
27332733 bit rot;
27462746 }
27472747
27482748 def MVE_VCADDf16 : MVE_VCADD<"f16", 0b0>;
2749 def MVE_VCADDf32 : MVE_VCADD<"f32", 0b1>;
2749 def MVE_VCADDf32 : MVE_VCADD<"f32", 0b1, "@earlyclobber $Qd">;
27502750
27512751 class MVE_VABD_fp
27522752 : MVE_float<"vabd", suffix, (outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
32993299 }
33003300
33013301 class MVE_VQxDMLxDH
3302 string suffix, bits<2> size, list pattern=[]>
3302 string suffix, bits<2> size, string cstr="", list pattern=[]>
33033303 : MVE_qDest_qSrc
33043304 (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
3305 vpred_n, "$Qd = $Qd_src", pattern> {
3305 vpred_n, "$Qd = $Qd_src"#cstr, pattern> {
33063306 bits<4> Qn;
33073307
33083308 let Inst{28} = subtract;
33193319 bit round, bit subtract> {
33203320 def s8 : MVE_VQxDMLxDH;
33213321 def s16 : MVE_VQxDMLxDH;
3322 def s32 : MVE_VQxDMLxDH>;
3322 def s32 : MVE_VQxDMLxDH, ",@earlyclobber $Qd">;
33233323 }
33243324
33253325 defm MVE_VQDMLADH : MVE_VQxDMLxDH_multi<"vqdmladh", 0b0, 0b0, 0b0>;
33313331 defm MVE_VQRDMLSDH : MVE_VQxDMLxDH_multi<"vqrdmlsdh", 0b0, 0b1, 0b1>;
33323332 defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
33333333
3334 class MVE_VCMULlist pattern=[]>
3334 class MVE_VCMULstring cstr="", list pattern=[]>
33353335 : MVE_qDest_qSrc
33363336 (ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
3337 "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
3337 "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
33383338 bits<4> Qn;
33393339 bits<2> rot;
33403340
33513351 }
33523352
33533353 def MVE_VCMULf16 : MVE_VCMUL<"vcmul", "f16", 0b0>;
3354 def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1>;
3354 def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1, "@earlyclobber $Qd">;
33553355
33563356 class MVE_VMULL bits_21_20,
3357 bit T, list pattern=[]>
3357 bit T, string cstr, list pattern=[]>
33583358 : MVE_qDest_qSrc
33593359 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
3360 vpred_r, "", pattern> {
3360 vpred_r, cstr, pattern> {
33613361 bits<4> Qd;
33623362 bits<4> Qn;
33633363 bits<4> Qm;
33733373 }
33743374
33753375 multiclass MVE_VMULL_multi
3376 bit bit_28, bits<2> bits_21_20> {
3377 def bh : MVE_VMULL;
3378 def th : MVE_VMULL;
3376 bit bit_28, bits<2> bits_21_20, string cstr=""> {
3377 def bh : MVE_VMULL;
3378 def th : MVE_VMULL;
33793379 }
33803380
33813381 // For integer multiplies, bits 21:20 encode size, and bit 28 signedness.
33843384
33853385 defm MVE_VMULLs8 : MVE_VMULL_multi<"vmull", "s8", 0b0, 0b00>;
33863386 defm MVE_VMULLs16 : MVE_VMULL_multi<"vmull", "s16", 0b0, 0b01>;
3387 defm MVE_VMULLs32 : MVE_VMULL_multi<"vmull", "s32", 0b0, 0b10>;
3387 defm MVE_VMULLs32 : MVE_VMULL_multi<"vmull", "s32", 0b0, 0b10, "@earlyclobber $Qd">;
33883388 defm MVE_VMULLu8 : MVE_VMULL_multi<"vmull", "u8", 0b1, 0b00>;
33893389 defm MVE_VMULLu16 : MVE_VMULL_multi<"vmull", "u16", 0b1, 0b01>;
3390 defm MVE_VMULLu32 : MVE_VMULL_multi<"vmull", "u32", 0b1, 0b10>;
3390 defm MVE_VMULLu32 : MVE_VMULL_multi<"vmull", "u32", 0b1, 0b10, "@earlyclobber $Qd">;
33913391 defm MVE_VMULLp8 : MVE_VMULL_multi<"vmull", "p8", 0b0, 0b11>;
33923392 defm MVE_VMULLp16 : MVE_VMULL_multi<"vmull", "p16", 0b1, 0b11>;
33933393
34763476 defm MVE_VCVTf32f16 : MVE_VCVT_ff_halves<"f32.f16", 0b1>;
34773477
34783478 class MVE_VxCADD size, bit halve,
3479 list pattern=[]>
3479 string cstr="", list pattern=[]>
34803480 : MVE_qDest_qSrc
34813481 (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
3482 "$Qd, $Qn, $Qm, $rot", vpred_r, "",
3483 pattern> {
3482 "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
34843483 bits<4> Qn;
34853484 bit rot;
34863485
34963495
34973496 def MVE_VCADDi8 : MVE_VxCADD<"vcadd", "i8", 0b00, 0b1>;
34983497 def MVE_VCADDi16 : MVE_VxCADD<"vcadd", "i16", 0b01, 0b1>;
3499 def MVE_VCADDi32 : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1>;
3498 def MVE_VCADDi32 : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1, "@earlyclobber $Qd">;
35003499
35013500 def MVE_VHCADDs8 : MVE_VxCADD<"vhcadd", "s8", 0b00, 0b0>;
35023501 def MVE_VHCADDs16 : MVE_VxCADD<"vhcadd", "s16", 0b01, 0b0>;
3503 def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0>;
3502 def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0, "@earlyclobber $Qd">;
35043503
35053504 class MVE_VADCSBC
35063505 dag carryin, list pattern=[]>
35303529 def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
35313530
35323531 class MVE_VQDMULL
3533 list pattern=[]>
3532 string cstr="", list pattern=[]>
35343533 : MVE_qDest_qSrc
35353534 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
3536 vpred_r, "", pattern> {
3535 vpred_r, cstr, pattern> {
35373536 bits<4> Qn;
35383537
35393538 let Inst{28} = size;
35463545 let Inst{0} = 0b1;
35473546 }
35483547
3549 multiclass MVE_VQDMULL_halves {
3550 def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0>;
3551 def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1>;
3548 multiclass MVE_VQDMULL_halves {
3549 def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0, cstr>;
3550 def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1, cstr>;
35523551 }
35533552
35543553 defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
3555 defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1>;
3554 defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1, "@earlyclobber $Qd">;
35563555
35573556 // end of mve_qDest_qSrc
35583557
35773576 let Inst{3-0} = Rm{3-0};
35783577 }
35793578
3580 class MVE_qDest_rSrclist pattern=[]>
3579 class MVE_qDest_rSrcstring cstr="", list pattern=[]>
35813580 : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qn, rGPR:$Rm),
3582 NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, "",
3581 NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, cstr,
35833582 pattern>;
35843583
35853584 class MVE_qDestSrc_rSrc pattern=[]>
36013600 class MVE_VADDSUB_qr size,
36023601 bit bit_5, bit bit_12, bit bit_16,
36033602 bit bit_28, list pattern=[]>
3604 : MVE_qDest_rSrcpattern> {
3603 : MVE_qDest_rSrc"", pattern> {
36053604
36063605 let Inst{28} = bit_28;
36073606 let Inst{21-20} = size;
36493648 }
36503649
36513650 class MVE_VQDMULL_qr
3652 bit T, list pattern=[]>
3653 : MVE_qDest_rSrc {
3651 bit T, string cstr="", list pattern=[]>
3652 : MVE_qDest_rSrc {
36543653
36553654 let Inst{28} = size;
36563655 let Inst{21-20} = 0b11;
36603659 let Inst{5} = 0b1;
36613660 }
36623661
3663 multiclass MVE_VQDMULL_qr_halves {
3664 def bh : MVE_VQDMULL_qr<"vqdmullb", suffix, size, 0b0>;
3665 def th : MVE_VQDMULL_qr<"vqdmullt", suffix, size, 0b1>;
3662 multiclass MVE_VQDMULL_qr_halves {
3663 def bh : MVE_VQDMULL_qr<"vqdmullb", suffix, size, 0b0, cstr>;
3664 def th : MVE_VQDMULL_qr<"vqdmullt", suffix, size, 0b1, cstr>;
36663665 }
36673666
36683667 defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<"s16", 0b0>;
3669 defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<"s32", 0b1>;
3668 defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<"s32", 0b1, "@earlyclobber $Qd">;
36703669
36713670 class MVE_VxADDSUB_qr
36723671 bit bit_28, bits<2> bits_21_20, bit subtract,
36733672 list pattern=[]>
3674 : MVE_qDest_rSrcpattern> {
3673 : MVE_qDest_rSrc"", pattern> {
36753674
36763675 let Inst{28} = bit_28;
36773676 let Inst{21-20} = bits_21_20;
37493748 }
37503749
37513750 class MVE_VBRSR size, list pattern=[]>
3752 : MVE_qDest_rSrcpattern> {
3751 : MVE_qDest_rSrc"", pattern> {
37533752
37543753 let Inst{28} = 0b1;
37553754 let Inst{21-20} = size;
37653764
37663765 class MVE_VMUL_qr_int
37673766 bits<2> size, list pattern=[]>
3768 : MVE_qDest_rSrcpattern> {
3767 : MVE_qDest_rSrc"", pattern> {
37693768
37703769 let Inst{28} = 0b0;
37713770 let Inst{21-20} = size;
37903789
37913790 class MVE_VxxMUL_qr
37923791 bit bit_28, bits<2> bits_21_20, list pattern=[]>
3793 : MVE_qDest_rSrcpattern> {
3792 : MVE_qDest_rSrc"", pattern> {
37943793
37953794 let Inst{28} = bit_28;
37963795 let Inst{21-20} = bits_21_20;