llvm.org GIT mirror llvm / a139051
Temporarily revert this patch to see if it brings the buildbots back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 8 years ago
6 changed file(s) with 42 addition(s) and 93 deletion(s). Raw diff Collapse all Expand all
53905390 SDValue V1 = SVOp->getOperand(0);
53915391 SDValue V2 = SVOp->getOperand(1);
53925392 DebugLoc dl = SVOp->getDebugLoc();
5393 LLVMContext *Context = DAG.getContext();
53935394 EVT VT = Op.getValueType();
53945395 EVT InVT = V1.getValueType();
5396 EVT EltVT = VT.getVectorElementType();
5397 unsigned EltSize = EltVT.getSizeInBits();
53955398 int MaskSize = VT.getVectorNumElements();
53965399 int InSize = InVT.getVectorNumElements();
53975400
5398 if (!Subtarget->hasSSE41())
5401 // TODO: At the moment we only use AVX blends. We could also use SSE4 blends.
5402 if (!Subtarget->hasAVX())
53995403 return SDValue();
54005404
54015405 if (MaskSize != InSize)
54025406 return SDValue();
54035407
5404 int ISDNo = 0;
5405 MVT OpTy;
5406
5407 switch (VT.getSimpleVT().SimpleTy) {
5408 default: return SDValue();
5409 case MVT::v8i16:
5410 ISDNo = X86ISD::BLENDPW;
5411 OpTy = MVT::v8i16;
5412 break;
5413 case MVT::v4i32:
5414 case MVT::v4f32:
5415 ISDNo = X86ISD::BLENDPS;
5416 OpTy = MVT::v4f32;
5417 break;
5418 case MVT::v2i64:
5419 case MVT::v2f64:
5420 ISDNo = X86ISD::BLENDPD;
5421 OpTy = MVT::v2f64;
5422 break;
5423 case MVT::v8i32:
5424 case MVT::v8f32:
5425 if (!Subtarget->hasAVX())
5426 return SDValue();
5427 ISDNo = X86ISD::BLENDPS;
5428 OpTy = MVT::v8f32;
5429 break;
5430 case MVT::v4i64:
5431 case MVT::v4f64:
5432 if (!Subtarget->hasAVX())
5433 return SDValue();
5434 ISDNo = X86ISD::BLENDPD;
5435 OpTy = MVT::v4f64;
5436 break;
5437 case MVT::v16i16:
5438 if (!Subtarget->hasAVX2())
5439 return SDValue();
5440 ISDNo = X86ISD::BLENDPW;
5441 OpTy = MVT::v16i16;
5442 break;
5443 }
5444 assert(ISDNo && "Invalid Op Number");
5445
5446 unsigned MaskVals = 0;
5408 SmallVector MaskVals;
5409 ConstantInt *Zero = ConstantInt::get(*Context, APInt(EltSize, 0));
5410 ConstantInt *NegOne = ConstantInt::get(*Context, APInt(EltSize, -1));
54475411
54485412 for (int i = 0; i < MaskSize; ++i) {
54495413 int EltIdx = SVOp->getMaskElt(i);
54505414 if (EltIdx == i || EltIdx == -1)
5451 MaskVals |= (1<);
5415 MaskVals.push_back(NegOne);
54525416 else if (EltIdx == (i + MaskSize))
5453 continue; // Bit is set to zero;
5417 MaskVals.push_back(Zero);
54545418 else return SDValue();
54555419 }
54565420
5457 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5458 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5459 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5460 DAG.getConstant(MaskVals, MVT::i32));
5461 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5421 Constant *MaskC = ConstantVector::get(MaskVals);
5422 EVT MaskTy = EVT::getEVT(MaskC->getType());
5423 assert(MaskTy.getSizeInBits() == VT.getSizeInBits() && "Invalid mask size");
5424 SDValue MaskIdx = DAG.getConstantPool(MaskC, PtrTy);
5425 unsigned Alignment = cast(MaskIdx)->getAlignment();
5426 SDValue Mask = DAG.getLoad(MaskTy, dl, DAG.getEntryNode(), MaskIdx,
5427 MachinePointerInfo::getConstantPool(),
5428 false, false, false, Alignment);
5429
5430 if (Subtarget->hasAVX2() && MaskTy == MVT::v32i8)
5431 return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2);
5432
5433 if (Subtarget->hasAVX()) {
5434 switch (MaskTy.getSimpleVT().SimpleTy) {
5435 default: return SDValue();
5436 case MVT::v16i8:
5437 case MVT::v4i32:
5438 case MVT::v2i64:
5439 case MVT::v8i32:
5440 case MVT::v4i64:
5441 return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2);
5442 }
5443 }
5444
5445 return SDValue();
54625446 }
54635447
54645448 // v8i16 shuffles - Prefer shuffles in the following order:
1106511049 case X86ISD::ANDNP: return "X86ISD::ANDNP";
1106611050 case X86ISD::PSIGN: return "X86ISD::PSIGN";
1106711051 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11068 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11069 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11070 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
1107111052 case X86ISD::HADD: return "X86ISD::HADD";
1107211053 case X86ISD::HSUB: return "X86ISD::HSUB";
1107311054 case X86ISD::FHADD: return "X86ISD::FHADD";
174174 /// PSIGN - Copy integer sign.
175175 PSIGN,
176176
177 /// BLENDV - Blend where the selector is an XMM.
177 /// BLEND family of opcodes
178178 BLENDV,
179
180 /// BLENDxx - Blend where the selector is an immediate.
181 BLENDPW,
182 BLENDPS,
183 BLENDPD,
184179
185180 /// HADD - Integer horizontal add.
186181 HADD,
125125 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
126126
127127 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
128 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
129 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
130128
131129 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
132130
158156 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
159157
160158 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
161
162 def X86Blendpw : SDNode<"X86ISD::BLENDPW", SDTBlend>;
163 def X86Blendps : SDNode<"X86ISD::BLENDPS", SDTBlend>;
164 def X86Blendpd : SDNode<"X86ISD::BLENDPD", SDTBlend>;
165159
166160 //===----------------------------------------------------------------------===//
167161 // SSE Complex Patterns
67346734 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
67356735 (v4f64 VR256:$src2))),
67366736 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6737
6738 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6739 (imm:$mask))),
6740 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6741 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6742 (imm:$mask))),
6743 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
67446737 }
67456738
67466739 let Predicates = [HasAVX2] in {
67476740 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
67486741 (v32i8 VR256:$src2))),
67496742 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6750 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6751 (imm:$mask))),
6752 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
67536743 }
67546744
67556745 /// SS41I_ternary_int - SSE 4.1 ternary operator
67986788 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
67996789 (v2f64 VR128:$src2))),
68006790 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6801
6802 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6803 (imm:$mask))),
6804 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6805 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6806 (imm:$mask))),
6807 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6808 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6809 (imm:$mask))),
6810 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6811
68126791 }
68136792
68146793 let Predicates = [HasAVX] in
163163 }
164164
165165 ; CHECK: blend1
166 ; CHECK: vblendps
166 ; CHECK: vblendvps
167167 ; CHECK: ret
168168 define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
169169 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32>
171171 }
172172
173173 ; CHECK: blend2
174 ; CHECK: vblendps
174 ; CHECK: vblendvps
175175 ; CHECK: ret
176176 define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
177177 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32>
179179 }
180180
181181 ; CHECK: blend2a
182 ; CHECK: vblendps
182 ; CHECK: vblendvps
183183 ; CHECK: ret
184184 define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinline {
185185 %t = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32>
187187 }
188188
189189 ; CHECK: blend3
190 ; CHECK-NOT: vblendps
190 ; CHECK-NOT: vblendvps
191191 ; CHECK: ret
192192 define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
193193 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32>
195195 }
196196
197197 ; CHECK: blend4
198 ; CHECK: vblendpd
198 ; CHECK: vblendvpd
199199 ; CHECK: ret
200200 define <4 x i64> @blend4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
201201 %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
None ; RUN: llc < %s -o /dev/null -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2
0 ; RUN: llc < %s -o /dev/null -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
11
22 define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind {
33 entry: