llvm.org GIT mirror llvm / a116d74
Merging r227089: ------------------------------------------------------------------------ r227089 | vkalintiris | 2015-01-26 12:33:22 +0000 (Mon, 26 Jan 2015) | 15 lines [mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@231471 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 5 years ago
17 changed file(s) with 447 addition(s) and 43 deletion(s). Raw diff Collapse all Expand all
436436
437437 // bswap MipsPattern
438438 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
439
440 // Carry pattern
441 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
442 (DSUBu GPR64:$lhs, GPR64:$rhs)>;
443 let AdditionalPredicates = [NotDSP] in {
444 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
445 (DADDu GPR64:$lhs, GPR64:$rhs)>;
446 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
447 (DADDiu GPR64:$lhs, imm:$imm)>;
448 }
439449
440450 //===----------------------------------------------------------------------===//
441451 // Instruction aliases
256256 setOperationAction(ISD::LOAD, MVT::i64, Custom);
257257 setOperationAction(ISD::STORE, MVT::i64, Custom);
258258 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
259 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
260 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
261 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
259262 }
260263
261264 if (!Subtarget.isGP64bit()) {
19911994 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
19921995 SelectionDAG &DAG) const {
19931996 SDLoc DL(Op);
1997 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
1998
19941999 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
19952000 SDValue Shamt = Op.getOperand(2);
1996
1997 // if shamt < 32:
2001 // if shamt < (VT.bits):
19982002 // lo = (shl lo, shamt)
19992003 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
20002004 // else:
20022006 // hi = (shl lo, shamt[4:0])
20032007 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
20042008 DAG.getConstant(-1, MVT::i32));
2005 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2006 DAG.getConstant(1, MVT::i32));
2007 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2008 Not);
2009 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2010 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2011 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2009 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2010 DAG.getConstant(1, VT));
2011 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2012 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2013 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2014 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
20122015 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
20132016 DAG.getConstant(0x20, MVT::i32));
2014 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2015 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2016 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2017 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2018 DAG.getConstant(0, VT), ShiftLeftLo);
2019 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
20172020
20182021 SDValue Ops[2] = {Lo, Hi};
20192022 return DAG.getMergeValues(Ops, DL);
20242027 SDLoc DL(Op);
20252028 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
20262029 SDValue Shamt = Op.getOperand(2);
2027
2028 // if shamt < 32:
2030 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2031
2032 // if shamt < (VT.bits):
20292033 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
20302034 // if isSRA:
20312035 // hi = (sra hi, shamt)
20402044 // hi = 0
20412045 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
20422046 DAG.getConstant(-1, MVT::i32));
2043 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2044 DAG.getConstant(1, MVT::i32));
2045 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2046 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2047 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2048 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2049 Hi, Shamt);
2047 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2048 DAG.getConstant(1, VT));
2049 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2050 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2051 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2052 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2053 DL, VT, Hi, Shamt);
20502054 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
20512055 DAG.getConstant(0x20, MVT::i32));
2052 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2053 DAG.getConstant(31, MVT::i32));
2054 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2055 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2056 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2057 ShiftRightHi);
2056 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
2057 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2058 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2059 IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
20582060
20592061 SDValue Ops[2] = {Lo, Hi};
20602062 return DAG.getMergeValues(Ops, DL);
238238 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
239239 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
240240
241 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
242 if (Subtarget->isGP64bit()) {
243 SLTuOp = Mips::SLTu64;
244 ADDuOp = Mips::DADDu;
245 }
246
241247 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
242248 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
243249 EVT VT = LHS.getValueType();
244250
245 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
246 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
251 SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
252
253 if (Subtarget->isGP64bit()) {
254 // On 64-bit targets, sltu produces an i64 but our backend currently says
255 // that SLTu64 produces an i32. We need to fix this in the long run but for
256 // now, just make the DAG type-correct by asserting the upper bits are zero.
257 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
258 CurDAG->getTargetConstant(0, VT),
259 SDValue(Carry, 0),
260 CurDAG->getTargetConstant(Mips::sub_32, VT));
261 }
262
263 SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT,
247264 SDValue(Carry, 0), RHS);
265
248266 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
249267 SDValue(AddCarry, 0));
250268 }
643661
644662 case ISD::SUBE: {
645663 SDValue InFlag = Node->getOperand(2);
646 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
664 unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
665 Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
647666 return std::make_pair(true, Result);
648667 }
649668
651670 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
652671 break;
653672 SDValue InFlag = Node->getOperand(2);
654 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
673 unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
674 Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
655675 return std::make_pair(true, Result);
656676 }
657677
124124 setOperationAction(ISD::MUL, MVT::i64, Custom);
125125
126126 if (Subtarget.isGP64bit()) {
127 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
128 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
127129 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128130 setOperationAction(ISD::MULHU, MVT::i64, Custom);
129131 }
202204 if (Subtarget.hasMips64r6()) {
203205 // MIPS64r6 replaces the accumulator-based multiplies with a three register
204206 // instruction
207 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
208 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
205209 setOperationAction(ISD::MUL, MVT::i64, Legal);
206210 setOperationAction(ISD::MULHS, MVT::i64, Legal);
207211 setOperationAction(ISD::MULHU, MVT::i64, Legal);
8080 %r = add i64 %a, %b
8181 ret i64 %r
8282 }
83
84 define signext i128 @add_i128(i128 signext %a, i128 signext %b) {
85 entry:
86 ; ALL-LABEL: add_i128:
87
88 ; GP32: lw $[[T0:[0-9]+]], 28($sp)
89 ; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]]
90 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
91 ; GP32: lw $[[T3:[0-9]+]], 24($sp)
92 ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
93 ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]]
94 ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
95 ; GP32: lw $[[T7:[0-9]+]], 20($sp)
96 ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
97 ; GP32: lw $[[T9:[0-9]+]], 16($sp)
98 ; GP32: addu $3, $5, $[[T8]]
99 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
100 ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]]
101 ; GP32: addu $2, $4, $[[T11]]
102 ; GP32: move $4, $[[T5]]
103 ; GP32: move $5, $[[T1]]
104
105 ; GP64: daddu $3, $5, $7
106 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
107 ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
108 ; GP64: daddu $2, $4, $[[T1]]
109
110 %r = add i128 %a, %b
111 ret i128 %r
112 }
6969 %r = and i64 %a, %b
7070 ret i64 %r
7171 }
72
73 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
74 entry:
75 ; ALL-LABEL: and_i128:
76
77 ; GP32: lw $[[T0:[0-9]+]], 24($sp)
78 ; GP32: lw $[[T1:[0-9]+]], 20($sp)
79 ; GP32: lw $[[T2:[0-9]+]], 16($sp)
80 ; GP32: and $2, $4, $[[T2]]
81 ; GP32: and $3, $5, $[[T1]]
82 ; GP32: and $4, $6, $[[T0]]
83 ; GP32: lw $[[T3:[0-9]+]], 28($sp)
84 ; GP32: and $5, $7, $[[T3]]
85
86 ; GP64: and $2, $4, $6
87 ; GP64: and $3, $5, $7
88
89 %r = and i128 %a, %b
90 ret i128 %r
91 }
102102 %r = ashr i64 %a, %b
103103 ret i64 %r
104104 }
105
106 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
107 entry:
108 ; ALL-LABEL: ashr_i128:
109
110 ; GP32: lw $25, %call16(__ashrti3)($gp)
111
112 ; M3: sll $[[T0:[0-9]+]], $7, 0
113 ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
114 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
115 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
116 ; M3: move $3, $[[T1]]
117 ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
118 ; M3: dsll $[[T5:[0-9]+]], $4, 1
119 ; M3: not $[[T6:[0-9]+]], $[[T0]]
120 ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
121 ; M3: or $3, $[[T7]], $[[T4]]
122 ; M3: $[[BB0]]:
123 ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
124 ; M3: nop
125 ; M3: dsra $2, $4, 31
126 ; M3: $[[BB1]]:
127 ; M3: jr $ra
128 ; M3: nop
129
130 ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
131 ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
132 ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
133 ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
134 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
135 ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
136 ; GP64-NOT-R6: dsrav $2, $4, $[[T0]]
137 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
138
139 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
140 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31
141 ; GP64-NOT-R6: jr $ra
142 ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
143
144 ; 64R6: sll $[[T0:[0-9]+]], $7, 0
145 ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
146 ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32
147 ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
148 ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]]
149 ; 64R6: dsra $[[T5:[0-9]+]], $4, 31
150 ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
151 ; 64R6: or $2, $[[T6]], $[[T4]]
152 ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]]
153 ; 64R6: dsll $[[T8:[0-9]+]], $4, 1
154 ; 64R6: not $[[T9:[0-9]+]], $[[T0]]
155 ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
156 ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]]
157 ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]]
158 ; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]]
159 ; 64R6: jr $ra
160 ; 64R6: or $3, $[[T13]], $[[T12]]
161
162 %r = ashr i128 %a, %b
163 ret i128 %r
164 }
9595 %r = lshr i64 %a, %b
9696 ret i64 %r
9797 }
98
99 define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
100 entry:
101 ; ALL-LABEL: lshr_i128:
102
103 ; GP32: lw $25, %call16(__lshrti3)($gp)
104
105 ; M3: sll $[[T0:[0-9]+]], $7, 0
106 ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]]
107 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
108 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
109 ; M3: move $3, $[[T1]]
110 ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
111 ; M3: dsll $[[T5:[0-9]+]], $4, 1
112 ; M3: not $[[T6:[0-9]+]], $[[T0]]
113 ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
114 ; M3: or $3, $[[T7]], $[[T4]]
115 ; M3: $[[BB0]]:
116 ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
117 ; M3: daddiu $2, $zero, 0
118 ; M3: move $2, $[[T1]]
119 ; M3: $[[BB1]]:
120 ; M3: jr $ra
121 ; M3: nop
122
123 ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
124 ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
125 ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
126 ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
127 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
128 ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
129 ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]]
130 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
131 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
132 ; GP64-NOT-R6: jr $ra
133 ; GP64-NOT-R6: movn $2, $zero, $1
134
135 ; 64R6: sll $[[T0:[0-9]+]], $7, 0
136 ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
137 ; 64R6: dsll $[[T2:[0-9]+]], $4, 1
138 ; 64R6: not $[[T3:[0-9]+]], $[[T0]]
139 ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
140 ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]]
141 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
142 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
143 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
144 ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]]
145 ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
146 ; 64R6: or $3, $[[T10]], $[[T8]]
147 ; 64R6: jr $ra
148 ; 64R6: seleqz $2, $[[T0]], $[[T7]]
149
150 %r = lshr i128 %a, %b
151 ret i128 %r
152 }
None ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
1 ; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1
2 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
3 ; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2
4 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
5 ; RUN: -check-prefix=ALL -check-prefix=32R6
6 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
7 ; RUN: -check-prefix=ALL -check-prefix=64R1-R2
8 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
9 ; RUN: -check-prefix=ALL -check-prefix=64R1-R2
10 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
11 ; RUN: -check-prefix=ALL -check-prefix=64R6
0 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
1 ; RUN: -check-prefix=32R1-R2 -check-prefix=32R1 -check-prefix=GP32
2 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
3 ; RUN: -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32
4 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
5 ; RUN: -check-prefix=32R6 -check-prefix=GP32
6 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
7 ; RUN: -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6
8 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
9 ; RUN: -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
10 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
11 ; RUN: -check-prefix=64R6
1212
1313 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
1414 entry:
128128 %r = mul i64 %a, %b
129129 ret i64 %r
130130 }
131
132 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
133 entry:
134 ; ALL-LABEL: mul_i128:
135
136 ; GP32: lw $25, %call16(__multi3)($gp)
137
138 ; GP64-NOT-R6: dmult $4, $7
139 ; GP64-NOT-R6: mflo $[[T0:[0-9]+]]
140 ; GP64-NOT-R6: dmult $5, $6
141 ; GP64-NOT-R6: mflo $[[T1:[0-9]+]]
142 ; GP64-NOT-R6: dmultu $5, $7
143 ; GP64-NOT-R6: mflo $3
144 ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]
145 ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
146 ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
147
148 ; 64R6: dmul $[[T0:[0-9]+]], $5, $6
149 ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7
150 ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
151 ; 64R6: dmul $[[T3:[0-9]+]], $4, $7
152 ; 64R6: daddu $2, $[[T2]], $[[T3]]
153 ; 64R6: dmul $3, $5, $7
154
155 %r = mul i128 %a, %b
156 ret i128 %r
157 }
7070 %r = or i64 %a, %b
7171 ret i64 %r
7272 }
73
74 define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
75 entry:
76 ; ALL-LABEL: or_i128:
77
78 ; GP32: lw $[[T0:[0-9]+]], 24($sp)
79 ; GP32: lw $[[T1:[0-9]+]], 20($sp)
80 ; GP32: lw $[[T2:[0-9]+]], 16($sp)
81 ; GP32: or $2, $4, $[[T2]]
82 ; GP32: or $3, $5, $[[T1]]
83 ; GP32: or $4, $6, $[[T0]]
84 ; GP32: lw $[[T3:[0-9]+]], 28($sp)
85 ; GP32: or $5, $7, $[[T3]]
86
87 ; GP64: or $2, $4, $6
88 ; GP64: or $3, $5, $7
89
90 %r = or i128 %a, %b
91 ret i128 %r
92 }
118118 %r = sdiv i64 %a, %b
119119 ret i64 %r
120120 }
121
122 define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
123 entry:
124 ; ALL-LABEL: sdiv_i128:
125
126 ; GP32: lw $25, %call16(__divti3)($gp)
127
128 ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
129 ; 64R6: ld $25, %call16(__divti3)($gp)
130
131 %r = sdiv i128 %a, %b
132 ret i128 %r
133 }
107107 %r = shl i64 %a, %b
108108 ret i64 %r
109109 }
110
111 define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
112 entry:
113 ; ALL-LABEL: shl_i128:
114
115 ; GP32: lw $25, %call16(__ashlti3)($gp)
116
117 ; M3: sll $[[T0:[0-9]+]], $7, 0
118 ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]]
119 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
120 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
121 ; M3: move $2, $[[T1]]
122 ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]]
123 ; M3: dsrl $[[T5:[0-9]+]], $5, 1
124 ; M3: not $[[T6:[0-9]+]], $[[T0]]
125 ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
126 ; M3: or $2, $[[T4]], $[[T7]]
127 ; M3: $[[BB0]]:
128 ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
129 ; M3: daddiu $3, $zero, 0
130 ; M3: move $3, $[[T1]]
131 ; M3: $[[BB1]]:
132 ; M3: jr $ra
133 ; M3: nop
134
135 ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
136 ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
137 ; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1
138 ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
139 ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
140 ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]]
141 ; GP64-NOT-R6: dsllv $3, $5, $[[T0]]
142 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
143 ; GP64-NOT-R6: movn $2, $3, $[[T5]]
144 ; GP64-NOT-R6: jr $ra
145 ; GP64-NOT-R6: movn $3, $zero, $1
146
147 ; 64R6: sll $[[T0:[0-9]+]], $7, 0
148 ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
149 ; 64R6: dsrl $[[T2:[0-9]+]], $5, 1
150 ; 64R6: not $[[T3:[0-9]+]], $[[T0]]
151 ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
152 ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]]
153 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
154 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
155 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
156 ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]]
157 ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
158 ; 64R6: or $2, $[[T10]], $[[T8]]
159 ; 64R6: jr $ra
160 ; 64R6: seleqz $3, $[[T0]], $[[T7]]
161
162 %r = shl i128 %a, %b
163 ret i128 %r
164 }
111111 %r = srem i64 %a, %b
112112 ret i64 %r
113113 }
114
115 define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
116 entry:
117 ; ALL-LABEL: srem_i128:
118
119 ; GP32: lw $25, %call16(__modti3)($gp)
120
121 ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
122 ; 64-R6: ld $25, %call16(__modti3)($gp)
123
124 %r = srem i128 %a, %b
125 ret i128 %r
126 }
8080 %r = sub i64 %a, %b
8181 ret i64 %r
8282 }
83
84 define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
85 entry:
86 ; ALL-LABEL: sub_i128:
87
88 ; GP32: lw $[[T0:[0-9]+]], 20($sp)
89 ; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]]
90 ; GP32: lw $[[T2:[0-9]+]], 16($sp)
91 ; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]]
92 ; GP32: lw $[[T4:[0-9]+]], 24($sp)
93 ; GP32: lw $[[T5:[0-9]+]], 28($sp)
94 ; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]]
95 ; GP32: subu $2, $4, $[[T3]]
96 ; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]]
97 ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]]
98 ; GP32: subu $3, $5, $[[T9]]
99 ; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]]
100 ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]]
101 ; GP32: subu $4, $6, $[[T11]]
102 ; GP32: move $5, $[[T6]]
103
104 ; GP64: dsubu $3, $5, $7
105 ; GP64: sltu $[[T0:[0-9]+]], $5, $7
106 ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
107 ; GP64: dsubu $2, $4, $[[T1]]
108
109 %r = sub i128 %a, %b
110 ret i128 %r
111 }
9090 %r = udiv i64 %a, %b
9191 ret i64 %r
9292 }
93
94 define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
95 entry:
96 ; ALL-LABEL: udiv_i128:
97
98 ; GP32: lw $25, %call16(__udivti3)($gp)
99
100 ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
101 ; 64-R6: ld $25, %call16(__udivti3)($gp)
102
103 %r = udiv i128 %a, %b
104 ret i128 %r
105 }
127127 %r = urem i64 %a, %b
128128 ret i64 %r
129129 }
130
131 define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
132 entry:
133 ; ALL-LABEL: urem_i128:
134
135 ; GP32: lw $25, %call16(__umodti3)($gp)
136
137 ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
138 ; 64-R6: ld $25, %call16(__umodti3)($gp)
139
140 %r = urem i128 %a, %b
141 ret i128 %r
142 }
6969 %r = xor i64 %a, %b
7070 ret i64 %r
7171 }
72
73 define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
74 entry:
75 ; ALL-LABEL: xor_i128:
76
77 ; GP32: lw $[[T0:[0-9]+]], 24($sp)
78 ; GP32: lw $[[T1:[0-9]+]], 20($sp)
79 ; GP32: lw $[[T2:[0-9]+]], 16($sp)
80 ; GP32: xor $2, $4, $[[T2]]
81 ; GP32: xor $3, $5, $[[T1]]
82 ; GP32: xor $4, $6, $[[T0]]
83 ; GP32: lw $[[T3:[0-9]+]], 28($sp)
84 ; GP32: xor $5, $7, $[[T3]]
85
86 ; GP64: xor $2, $4, $6
87 ; GP64: xor $3, $5, $7
88
89 %r = xor i128 %a, %b
90 ret i128 %r
91 }