llvm.org GIT mirror llvm / a0e8333
[mips][ias] Moved most instruction emission helpers to MipsTargetStreamer. NFC. Summary: * Moved all the emit*() helpers to MipsTargetStreamer. * Moved createNop() to MipsTargetStreamer as emitNop() and emitEmptyDelaySlot(). This instruction has been split to distinguish between the 'nop' instruction and the nop used in delay slots which is sometimes a different nop to the 'nop' instruction (e.g. for short delay slots on microMIPS). * Moved createAddu() to MipsTargetStreamer as emitAddu(). * Moved createAppropriateDSLL() to MipsTargetStreamer as emitDSLL(). Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19712 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268041 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 3 years ago
3 changed file(s) with 341 addition(s) and 295 deletion(s). Raw diff Collapse all Expand all
238238
239239 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
240240 const MCSubtargetInfo *STI);
241
242 void createNop(bool hasShortDelaySlot, SMLoc IDLoc, MCStreamer &Out,
243 const MCSubtargetInfo *STI);
244
245 void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
246 bool Is64Bit, MCStreamer &Out, const MCSubtargetInfo *STI);
247241
248242 void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc,
249243 MCStreamer &Out, const MCSubtargetInfo *STI);
14871481 return 0;
14881482 }
14891483
1490 namespace {
1491 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
1492 MCStreamer &Out, const MCSubtargetInfo *STI) {
1493 MCInst tmpInst;
1494 tmpInst.setOpcode(Opcode);
1495 tmpInst.addOperand(MCOperand::createReg(Reg0));
1496 tmpInst.addOperand(Op1);
1497 tmpInst.setLoc(IDLoc);
1498 Out.EmitInstruction(tmpInst, *STI);
1499 }
1500
1501 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
1502 MCStreamer &Out, const MCSubtargetInfo *STI) {
1503 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, Out, STI);
1504 }
1505
1506 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
1507 MCStreamer &Out, const MCSubtargetInfo *STI) {
1508 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, Out, STI);
1509 }
1510
1511 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
1512 MCStreamer &Out, const MCSubtargetInfo *STI) {
1513 MCInst tmpInst;
1514 tmpInst.setOpcode(Opcode);
1515 tmpInst.addOperand(MCOperand::createImm(Imm1));
1516 tmpInst.addOperand(MCOperand::createImm(Imm2));
1517 tmpInst.setLoc(IDLoc);
1518 Out.EmitInstruction(tmpInst, *STI);
1519 }
1520
1521 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
1522 MCStreamer &Out, const MCSubtargetInfo *STI) {
1523 MCInst tmpInst;
1524 tmpInst.setOpcode(Opcode);
1525 tmpInst.addOperand(MCOperand::createReg(Reg0));
1526 tmpInst.setLoc(IDLoc);
1527 Out.EmitInstruction(tmpInst, *STI);
1528 }
1529
1530 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
1531 SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) {
1532 MCInst tmpInst;
1533 tmpInst.setOpcode(Opcode);
1534 tmpInst.addOperand(MCOperand::createReg(Reg0));
1535 tmpInst.addOperand(MCOperand::createReg(Reg1));
1536 tmpInst.addOperand(Op2);
1537 tmpInst.setLoc(IDLoc);
1538 Out.EmitInstruction(tmpInst, *STI);
1539 }
1540
1541 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
1542 SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) {
1543 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, Out, STI);
1544 }
1545
1546 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
1547 SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) {
1548 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, Out, STI);
1549 }
1550
1551 void emitAppropriateDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
1552 SMLoc IDLoc, MCStreamer &Out,
1553 const MCSubtargetInfo *STI) {
1554 if (ShiftAmount >= 32) {
1555 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, Out, STI);
1556 return;
1557 }
1558
1559 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, Out, STI);
1560 }
1561 } // end anonymous namespace.
1562
15631484 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
15641485 MCStreamer &Out,
15651486 const MCSubtargetInfo *STI) {
1487 MipsTargetStreamer &TOut = getTargetStreamer();
15661488 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
15671489 bool ExpandedJalSym = false;
15681490
17211643 const MCExpr *Got16RelocExpr = evaluateRelocExpr(JalExpr, "got");
17221644 const MCExpr *Lo16RelocExpr = evaluateRelocExpr(JalExpr, "lo");
17231645
1724 emitRRX(Mips::LW, Mips::T9, Mips::GP,
1725 MCOperand::createExpr(Got16RelocExpr), IDLoc, Out, STI);
1726 emitRRX(Mips::ADDiu, Mips::T9, Mips::T9,
1727 MCOperand::createExpr(Lo16RelocExpr), IDLoc, Out, STI);
1646 TOut.emitRRX(Mips::LW, Mips::T9, Mips::GP,
1647 MCOperand::createExpr(Got16RelocExpr), IDLoc, STI);
1648 TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9,
1649 MCOperand::createExpr(Lo16RelocExpr), IDLoc, STI);
17281650 } else if (isABI_N32() || isABI_N64()) {
17291651 // If it's a local symbol and the N32/N64 ABIs are being used,
17301652 // we expand to:
17331655 // jalr $25
17341656 const MCExpr *GotDispRelocExpr = evaluateRelocExpr(JalExpr, "got_disp");
17351657
1736 emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1737 MCOperand::createExpr(GotDispRelocExpr), IDLoc, Out, STI);
1658 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9,
1659 Mips::GP, MCOperand::createExpr(GotDispRelocExpr), IDLoc,
1660 STI);
17381661 }
17391662 } else {
17401663 // If it's an external/weak symbol, we expand to:
17431666 // jalr $25
17441667 const MCExpr *Call16RelocExpr = evaluateRelocExpr(JalExpr, "call16");
17451668
1746 emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1747 MCOperand::createExpr(Call16RelocExpr), IDLoc, Out, STI);
1669 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1670 MCOperand::createExpr(Call16RelocExpr), IDLoc, STI);
17481671 }
17491672
17501673 MCInst JalrInst;
18151738 (BaseReg.getReg() == Mips::GP ||
18161739 BaseReg.getReg() == Mips::GP_64)) {
18171740
1818 emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
1819 IDLoc, Out, STI);
1741 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
1742 IDLoc, STI);
18201743 return false;
18211744 }
18221745 }
19281851 bool FillDelaySlot =
19291852 MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
19301853 if (FillDelaySlot)
1931 getTargetStreamer().emitDirectiveSetNoReorder();
1854 TOut.emitDirectiveSetNoReorder();
19321855
19331856 MacroExpanderResultTy ExpandResult =
19341857 tryExpandInstruction(Inst, IDLoc, Out, STI);
19451868 // If this instruction has a delay slot and .set reorder is active,
19461869 // emit a NOP after it.
19471870 if (FillDelaySlot) {
1948 createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Out, STI);
1949 getTargetStreamer().emitDirectiveSetReorder();
1871 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc, STI);
1872 TOut.emitDirectiveSetReorder();
19501873 }
19511874
19521875 if ((Inst.getOpcode() == Mips::JalOneReg ||
19571880 // If .set reorder has been used, we've already emitted a NOP.
19581881 // If .set noreorder has been used, we need to emit a NOP at this point.
19591882 if (!AssemblerOptions.back()->isReorder())
1960 createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Out, STI);
1883 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc,
1884 STI);
19611885
19621886 // Load the $gp from the stack.
19631887 createCpRestoreMemOp(true /*IsLoad*/, CpRestoreOffset /*StackOffset*/,
21252049 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
21262050 MCStreamer &Out,
21272051 const MCSubtargetInfo *STI) {
2052 MipsTargetStreamer &TOut = getTargetStreamer();
2053
21282054 // Create a JALR instruction which is going to replace the pseudo-JAL.
21292055 MCInst JalrInst;
21302056 JalrInst.setLoc(IDLoc);
21592085 // If .set reorder is active and branch instruction has a delay slot,
21602086 // emit a NOP after it.
21612087 const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode());
2162 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) {
2163 createNop(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc, Out, STI);
2164 }
2088 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
2089 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc,
2090 STI);
21652091
21662092 return false;
21672093 }
21872113 unsigned SrcReg, bool Is32BitImm,
21882114 bool IsAddress, SMLoc IDLoc, MCStreamer &Out,
21892115 const MCSubtargetInfo *STI) {
2116 MipsTargetStreamer &TOut = getTargetStreamer();
2117
21902118 if (!Is32BitImm && !isGP64bit()) {
21912119 Error(IDLoc, "instruction requires a 64-bit architecture");
21922120 return true;
22302158 // traditional assembler behaviour. N32 would normally use addiu for both
22312159 // integers and addresses.
22322160 if (IsAddress && !Is32BitImm) {
2233 emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, Out, STI);
2234 return false;
2235 }
2236
2237 emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, Out, STI);
2161 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2162 return false;
2163 }
2164
2165 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
22382166 return false;
22392167 }
22402168
22462174 return true;
22472175 }
22482176
2249 emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, Out, STI);
2177 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
22502178 if (UseSrcReg)
2251 emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2179 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
22522180 return false;
22532181 }
22542182
22622190 // Traditional behaviour seems to special case this particular value. It's
22632191 // not clear why other masks are handled differently.
22642192 if (ImmValue == 0xffffffff) {
2265 emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, Out, STI);
2266 emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, Out, STI);
2193 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2194 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
22672195 if (UseSrcReg)
2268 emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2196 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
22692197 return false;
22702198 }
22712199
22722200 // Expand to an ORi instead of a LUi to avoid sign-extending into the
22732201 // upper 32 bits.
2274 emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, Out, STI);
2275 emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, Out, STI);
2202 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2203 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
22762204 if (Bits15To0)
2277 emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Out, STI);
2205 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
22782206 if (UseSrcReg)
2279 emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2280 return false;
2281 }
2282
2283 emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, Out, STI);
2207 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2208 return false;
2209 }
2210
2211 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
22842212 if (Bits15To0)
2285 emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, Out, STI);
2213 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
22862214 if (UseSrcReg)
2287 emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2215 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
22882216 return false;
22892217 }
22902218
23002228 unsigned LastSet = findLastSet((uint64_t)ImmValue);
23012229 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet));
23022230 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2303 emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, Out, STI);
2304 emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, Out, STI);
2231 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2232 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
23052233
23062234 if (UseSrcReg)
2307 emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2235 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
23082236
23092237 return false;
23102238 }
23272255 uint16_t ImmChunk = (ImmValue >> BitNum) & 0xffff;
23282256
23292257 if (ImmChunk != 0) {
2330 emitAppropriateDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc,
2331 Out, STI);
2332 emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, Out, STI);
2258 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2259 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
23332260 ShiftCarriedForwards = 0;
23342261 }
23352262
23392266
23402267 // Finish any remaining shifts left by trailing zeros.
23412268 if (ShiftCarriedForwards)
2342 emitAppropriateDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc,
2343 Out, STI);
2269 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
23442270
23452271 if (UseSrcReg)
2346 emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2272 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
23472273
23482274 return false;
23492275 }
24012327 bool Is32BitSym, SMLoc IDLoc,
24022328 MCStreamer &Out,
24032329 const MCSubtargetInfo *STI) {
2330 MipsTargetStreamer &TOut = getTargetStreamer();
24042331 warnIfNoMacro(IDLoc);
24052332
24062333 const MCExpr *Symbol = cast(SymExpr);
24352362 // dsll $at, $at, 16
24362363 // daddiu $at, $at, %lo(sym)
24372364 // daddu $rd, $at, $rd
2438 emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, Out,
2439 STI);
2440 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HigherExpr),
2441 IDLoc, Out, STI);
2442 emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Out, STI);
2443 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), IDLoc,
2444 Out, STI);
2445 emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, Out, STI);
2446 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), IDLoc,
2447 Out, STI);
2448 emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, Out, STI);
2365 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
2366 STI);
2367 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
2368 MCOperand::createExpr(HigherExpr), IDLoc, STI);
2369 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
2370 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
2371 IDLoc, STI);
2372 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
2373 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
2374 IDLoc, STI);
2375 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
24492376
24502377 return false;
24512378 }
24582385 // dsll32 $rd, $rd, 0
24592386 // daddu $rd, $rd, $at
24602387 // (daddu $rd, $rd, $rs)
2461 emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, Out,
2462 STI);
2463 emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, Out, STI);
2464 emitRRX(Mips::DADDiu, DstReg, DstReg, MCOperand::createExpr(HigherExpr),
2465 IDLoc, Out, STI);
2466 emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), IDLoc,
2467 Out, STI);
2468 emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, Out, STI);
2469 emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, Out, STI);
2388 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
2389 STI);
2390 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
2391 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
2392 MCOperand::createExpr(HigherExpr), IDLoc, STI);
2393 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
2394 IDLoc, STI);
2395 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
2396 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
24702397 if (UseSrcReg)
2471 emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, Out, STI);
2398 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
24722399
24732400 return false;
24742401 }
24932420 TmpReg = ATReg;
24942421 }
24952422
2496 emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, Out, STI);
2497 emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), IDLoc,
2498 Out, STI);
2423 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
2424 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
2425 IDLoc, STI);
24992426
25002427 if (UseSrcReg)
2501 emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Out, STI);
2428 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
25022429 else
25032430 assert(
25042431 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
25092436 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
25102437 MCStreamer &Out,
25112438 const MCSubtargetInfo *STI) {
2439 MipsTargetStreamer &TOut = getTargetStreamer();
2440
25122441 assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
25132442 "unexpected number of operands");
25142443
25442473 // emit a NOP after it.
25452474 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
25462475 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
2547 createNop(true, IDLoc, Out, STI);
2476 TOut.emitEmptyDelaySlot(true, IDLoc, STI);
25482477
25492478 return false;
25502479 }
25512480
25522481 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
25532482 const MCSubtargetInfo *STI) {
2483 MipsTargetStreamer &TOut = getTargetStreamer();
25542484 const MCOperand &DstRegOp = Inst.getOperand(0);
25552485 assert(DstRegOp.isReg() && "expected register operand kind");
25562486
25762506
25772507 int64_t ImmValue = ImmOp.getImm();
25782508 if (ImmValue == 0)
2579 emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, Out,
2580 STI);
2509 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
2510 STI);
25812511 else {
25822512 warnIfNoMacro(IDLoc);
25832513
25892519 IDLoc, Out, STI))
25902520 return true;
25912521
2592 emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, Out, STI);
2522 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
25932523 }
25942524 return false;
25952525 }
25972527 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
25982528 const MCSubtargetInfo *STI, bool isLoad,
25992529 bool isImmOpnd) {
2530 MipsTargetStreamer &TOut = getTargetStreamer();
26002531 MCOperand HiOperand, LoOperand;
26012532 unsigned TmpRegNum;
26022533 // 1st operand is either the source or destination register.
26592590 return;
26602591 }
26612592
2662 emitRX(Mips::LUi, TmpRegNum, HiOperand, IDLoc, Out, STI);
2593 TOut.emitRX(Mips::LUi, TmpRegNum, HiOperand, IDLoc, STI);
26632594 // Add temp register to base.
26642595 if (BaseRegNum != Mips::ZERO)
2665 emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, Out, STI);
2596 TOut.emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, STI);
26662597 // And finally, create original instruction with low part
26672598 // of offset and new base.
2668 emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum, LoOperand, IDLoc, Out, STI);
2599 TOut.emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum, LoOperand, IDLoc, STI);
26692600 }
26702601
26712602 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
27002631 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
27012632 MCStreamer &Out,
27022633 const MCSubtargetInfo *STI) {
2634 MipsTargetStreamer &TOut = getTargetStreamer();
27032635 bool EmittedNoMacroWarning = false;
27042636 unsigned PseudoOpcode = Inst.getOpcode();
27052637 unsigned SrcReg = Inst.getOperand(0).getReg();
28342766 // with GAS' behaviour. However, they may not generate the most efficient
28352767 // code in some circumstances.
28362768 if (PseudoOpcode == Mips::BLT) {
2837 emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2838 Out, STI);
2769 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2770 IDLoc, STI);
28392771 return false;
28402772 }
28412773 if (PseudoOpcode == Mips::BLE) {
2842 emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2843 Out, STI);
2774 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2775 IDLoc, STI);
28442776 Warning(IDLoc, "branch is always taken");
28452777 return false;
28462778 }
28472779 if (PseudoOpcode == Mips::BGE) {
2848 emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2849 Out, STI);
2780 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2781 IDLoc, STI);
28502782 Warning(IDLoc, "branch is always taken");
28512783 return false;
28522784 }
28532785 if (PseudoOpcode == Mips::BGT) {
2854 emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2855 Out, STI);
2786 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2787 IDLoc, STI);
28562788 return false;
28572789 }
28582790 if (PseudoOpcode == Mips::BGTU) {
2859 emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
2860 MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI);
2791 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
2792 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
28612793 return false;
28622794 }
28632795 if (AcceptsEquality) {
28642796 // If both registers are $0 and the pseudo-branch accepts equality, it
28652797 // will always be taken, so we emit an unconditional branch.
2866 emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2867 MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI);
2798 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2799 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
28682800 Warning(IDLoc, "branch is always taken");
28692801 return false;
28702802 }
28882820 // the pseudo-branch will always be taken, so we emit an unconditional
28892821 // branch.
28902822 // This only applies to unsigned pseudo-branches.
2891 emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2892 MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI);
2823 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2824 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
28932825 Warning(IDLoc, "branch is always taken");
28942826 return false;
28952827 }
29062838 //
29072839 // Because only BLEU and BGEU branch on equality, we can use the
29082840 // AcceptsEquality variable to decide when to emit the BEQZ.
2909 emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
2910 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
2911 MCOperand::createExpr(OffsetExpr), IDLoc, Out, STI);
2841 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
2842 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
2843 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
29122844 return false;
29132845 }
29142846 // If we have a signed pseudo-branch and one of the registers is $0,
29152847 // we can use an appropriate compare-to-zero branch. We select which one
29162848 // to use in the switch statement above.
2917 emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode,
2918 IsSrcRegZero ? TrgReg : SrcReg, MCOperand::createExpr(OffsetExpr),
2919 IDLoc, Out, STI);
2849 TOut.emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode,
2850 IsSrcRegZero ? TrgReg : SrcReg,
2851 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
29202852 return false;
29212853 }
29222854
29442876 //
29452877 // The same applies to the unsigned variants, except that SLTu is used
29462878 // instead of SLT.
2947 emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
2948 ReverseOrderSLT ? TrgReg : SrcReg, ReverseOrderSLT ? SrcReg : TrgReg,
2949 IDLoc, Out, STI);
2950
2951 emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
2952 : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
2953 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2954 Out, STI);
2879 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
2880 ReverseOrderSLT ? TrgReg : SrcReg,
2881 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI);
2882
2883 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
2884 : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
2885 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
2886 STI);
29552887 return false;
29562888 }
29572889
29582890 bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
29592891 const MCSubtargetInfo *STI, const bool IsMips64,
29602892 const bool Signed) {
2893 MipsTargetStreamer &TOut = getTargetStreamer();
2894
29612895 if (hasMips32r6()) {
29622896 Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
29632897 return false;
29912925 if (IsMips64) {
29922926 if (Signed && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
29932927 if (UseTraps) {
2994 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Out, STI);
2928 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
29952929 return false;
29962930 }
29972931
2998 emitII(Mips::BREAK, 0x7, 0, IDLoc, Out, STI);
2932 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
29992933 return false;
30002934 }
30012935 } else {
3002 emitRR(DivOp, RsReg, RtReg, IDLoc, Out, STI);
2936 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
30032937 return false;
30042938 }
30052939 }
30082942 Warning(IDLoc, "division by zero");
30092943 if (Signed) {
30102944 if (UseTraps) {
3011 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Out, STI);
2945 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
30122946 return false;
30132947 }
30142948
3015 emitII(Mips::BREAK, 0x7, 0, IDLoc, Out, STI);
2949 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
30162950 return false;
30172951 }
30182952 }
30242958
30252959 if (UseTraps) {
30262960 BranchTarget = IsMips64 ? 12 : 8;
3027 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Out, STI);
2961 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
30282962 } else {
30292963 BranchTarget = IsMips64 ? 20 : 16;
30302964 BranchTargetNoTraps = 8;
30312965 // Branch to the li instruction.
3032 emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, Out, STI);
3033 }
3034
3035 emitRR(DivOp, RsReg, RtReg, IDLoc, Out, STI);
2966 TOut.emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, STI);
2967 }
2968
2969 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
30362970
30372971 if (!UseTraps)
3038 emitII(Mips::BREAK, 0x7, 0, IDLoc, Out, STI);
2972 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
30392973
30402974 if (!Signed) {
3041 emitR(Mips::MFLO, RsReg, IDLoc, Out, STI);
2975 TOut.emitR(Mips::MFLO, RsReg, IDLoc, STI);
30422976 return false;
30432977 }
30442978
30462980 if (!ATReg)
30472981 return true;
30482982
3049 emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Out, STI);
2983 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
30502984 if (IsMips64) {
30512985 // Branch to the mflo instruction.
3052 emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Out, STI);
3053 emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, Out, STI);
3054 emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, Out, STI);
2986 TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
2987 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
2988 TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI);
30552989 } else {
30562990 // Branch to the mflo instruction.
3057 emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, Out, STI);
3058 emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, Out, STI);
2991 TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
2992 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
30592993 }
30602994
30612995 if (UseTraps)
3062 emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Out, STI);
2996 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
30632997 else {
30642998 // Branch to the mflo instruction.
3065 emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Out, STI);
3066 emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Out, STI);
3067 emitII(Mips::BREAK, 0x6, 0, IDLoc, Out, STI);
3068 }
3069 emitR(Mips::MFLO, RsReg, IDLoc, Out, STI);
2999 TOut.emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, STI);
3000 TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI);
3001 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
3002 }
3003 TOut.emitR(Mips::MFLO, RsReg, IDLoc, STI);
30703004 return false;
30713005 }
30723006
30733007 bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
30743008 SMLoc IDLoc, MCStreamer &Out,
30753009 const MCSubtargetInfo *STI) {
3010 MipsTargetStreamer &TOut = getTargetStreamer();
30763011
30773012 assert(Inst.getNumOperands() == 3 && "Invalid operand count");
30783013 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
30863021 unsigned ATReg = getATReg(IDLoc);
30873022 if (!ATReg)
30883023 return true;
3089 emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Out, STI);
3090 emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Out, STI);
3091 createNop(false, IDLoc, Out, STI);
3092 emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, Out, STI);
3093 emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, Out, STI);
3094 emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, Out, STI);
3095 createNop(false, IDLoc, Out, STI);
3096 emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
3097 : Mips::CVT_W_S,
3098 FirstReg, SecondReg, IDLoc, Out, STI);
3099 emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, Out, STI);
3100 createNop(false, IDLoc, Out, STI);
3101 return false;
3102 }
3103
3104 emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
3105 : Mips::TRUNC_W_S,
3106 FirstReg, SecondReg, IDLoc, Out, STI);
3024 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
3025 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
3026 TOut.emitNop(IDLoc, STI);
3027 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
3028 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
3029 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
3030 TOut.emitNop(IDLoc, STI);
3031 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
3032 : Mips::CVT_W_S,
3033 FirstReg, SecondReg, IDLoc, STI);
3034 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
3035 TOut.emitNop(IDLoc, STI);
3036 return false;
3037 }
3038
3039 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
3040 : Mips::TRUNC_W_S,
3041 FirstReg, SecondReg, IDLoc, STI);
31073042
31083043 return false;
31093044 }
31103045
31113046 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
31123047 MCStreamer &Out, const MCSubtargetInfo *STI) {
3048 MipsTargetStreamer &TOut = getTargetStreamer();
3049
31133050 if (hasMips32r6() || hasMips64r6()) {
31143051 Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
31153052 return false;
31543091 // NOTE: If there is no source register specified in the ULHU, the parser
31553092 // will interpret it as $0.
31563093 if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
3157 createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Out, STI);
3094 TOut.emitAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), STI);
31583095 }
31593096
31603097 unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg;
31723109
31733110 unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg;
31743111
3175 emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
3176 FirstLbuOffset, IDLoc, Out, STI);
3177
3178 emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc, Out,
3179 STI);
3180
3181 emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, Out, STI);
3182
3183 emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, Out, STI);
3112 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
3113 FirstLbuOffset, IDLoc, STI);
3114
3115 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc,
3116 STI);
3117
3118 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
3119
3120 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
31843121
31853122 return false;
31863123 }
31873124
31883125 bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
31893126 const MCSubtargetInfo *STI) {
3127 MipsTargetStreamer &TOut = getTargetStreamer();
3128
31903129 if (hasMips32r6() || hasMips64r6()) {
31913130 Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
31923131 return false;
32283167 // NOTE: If there is no source register specified in the ULW, the parser
32293168 // will interpret it as $0.
32303169 if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
3231 createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Out, STI);
3170 TOut.emitAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), STI);
32323171 }
32333172
32343173 unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg;
32413180 RightLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
32423181 }
32433182
3244 emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, Out,
3245 STI);
3246
3247 emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset, IDLoc,
3248 Out, STI);
3183 TOut.emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc,
3184 STI);
3185
3186 TOut.emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset,
3187 IDLoc, STI);
32493188
32503189 return false;
32513190 }
32533192 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
32543193 MCStreamer &Out,
32553194 const MCSubtargetInfo *STI) {
3195 MipsTargetStreamer &TOut = getTargetStreamer();
32563196
32573197 assert (Inst.getNumOperands() == 3 && "Invalid operand count");
32583198 assert (Inst.getOperand(0).isReg() &&
33083248 }
33093249
33103250 if (FinalDstReg == Mips::NoRegister)
3311 emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, Out, STI);
3251 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
33123252 else
3313 emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, Out, STI);
3253 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
33143254 return false;
33153255 }
33163256 return true;
33183258
33193259 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
33203260 const MCSubtargetInfo *STI) {
3261 MipsTargetStreamer &TOut = getTargetStreamer();
33213262 unsigned ATReg = Mips::NoRegister;
33223263 unsigned DReg = Inst.getOperand(0).getReg();
33233264 unsigned SReg = Inst.getOperand(1).getReg();
33363277 }
33373278
33383279 if (Inst.getOpcode() == Mips::ROL) {
3339 emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI);
3340 emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Out, STI);
3280 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3281 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
33413282 return false;
33423283 }
33433284
33443285 if (Inst.getOpcode() == Mips::ROR) {
3345 emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), Out, STI);
3286 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
33463287 return false;
33473288 }
33483289
33683309 if (!ATReg)
33693310 return true;
33703311
3371 emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI);
3372 emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Out, STI);
3373 emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Out, STI);
3374 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI);
3312 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3313 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
3314 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
3315 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
33753316
33763317 return false;
33773318 }
33823323 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
33833324 MCStreamer &Out,
33843325 const MCSubtargetInfo *STI) {
3385
3326 MipsTargetStreamer &TOut = getTargetStreamer();
33863327 unsigned ATReg = Mips::NoRegister;
33873328 unsigned DReg = Inst.getOperand(0).getReg();
33883329 unsigned SReg = Inst.getOperand(1).getReg();
33983339 uint64_t ShiftValue = ImmValue;
33993340 if (ImmValue != 0)
34003341 ShiftValue = MaxShift - ImmValue;
3401 emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), Out, STI);
3342 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
34023343 return false;
34033344 }
34043345
34053346 if (Inst.getOpcode() == Mips::RORImm) {
3406 emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), Out, STI);
3347 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
34073348 return false;
34083349 }
34093350
34133354 if (hasMips32()) {
34143355
34153356 if (ImmValue == 0) {
3416 emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), Out, STI);
3357 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI);
34173358 return false;
34183359 }
34193360
34343375 if (!ATReg)
34353376 return true;
34363377
3437 emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), Out, STI);
3438 emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), Out, STI);
3439 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI);
3378 TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), STI);
3379 TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI);
3380 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
34403381
34413382 return false;
34423383 }
34463387
34473388 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
34483389 const MCSubtargetInfo *STI) {
3449
3390 MipsTargetStreamer &TOut = getTargetStreamer();
34503391 unsigned ATReg = Mips::NoRegister;
34513392 unsigned DReg = Inst.getOperand(0).getReg();
34523393 unsigned SReg = Inst.getOperand(1).getReg();
34653406 }
34663407
34673408 if (Inst.getOpcode() == Mips::DROL) {
3468 emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI);
3469 emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), Out, STI);
3409 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3410 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
34703411 return false;
34713412 }
34723413
34733414 if (Inst.getOpcode() == Mips::DROR) {
3474 emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), Out, STI);
3415 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
34753416 return false;
34763417 }
34773418
34973438 if (!ATReg)
34983439 return true;
34993440
3500 emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), Out, STI);
3501 emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), Out, STI);
3502 emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), Out, STI);
3503 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI);
3441 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3442 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
3443 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
3444 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
35043445
35053446 return false;
35063447 }
35113452 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
35123453 MCStreamer &Out,
35133454 const MCSubtargetInfo *STI) {
3514
3455 MipsTargetStreamer &TOut = getTargetStreamer();
35153456 unsigned ATReg = Mips::NoRegister;
35163457 unsigned DReg = Inst.getOperand(0).getReg();
35173458 unsigned SReg = Inst.getOperand(1).getReg();
35453486 if (Inst.getOpcode() == Mips::DROLImm)
35463487 ShiftValue = (32 - ImmValue % 32) % 32;
35473488
3548 emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), Out, STI);
3489 TOut.emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
35493490
35503491 return false;
35513492 }
35533494 if (hasMips64()) {
35543495
35553496 if (ImmValue == 0) {
3556 emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), Out, STI);
3497 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI);
35573498 return false;
35583499 }
35593500
35943535 if (!ATReg)
35953536 return true;
35963537
3597 emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), Out, STI);
3598 emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32, Inst.getLoc(), Out, STI);
3599 emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), Out, STI);
3538 TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), STI);
3539 TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32,
3540 Inst.getLoc(), STI);
3541 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
36003542
36013543 return false;
36023544 }
36063548
36073549 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
36083550 const MCSubtargetInfo *STI) {
3609
3551 MipsTargetStreamer &TOut = getTargetStreamer();
36103552 unsigned FirstRegOp = Inst.getOperand(0).getReg();
36113553 unsigned SecondRegOp = Inst.getOperand(1).getReg();
36123554
3613 emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Out, STI);
3555 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
36143556 if (FirstRegOp != SecondRegOp)
3615 emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Out, STI);
3557 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
36163558 else
3617 createNop(false, IDLoc, Out, STI);
3618 emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Out, STI);
3559 TOut.emitEmptyDelaySlot(false, IDLoc, STI);
3560 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
36193561
36203562 return false;
3621 }
3622
3623 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
3624 MCStreamer &Out, const MCSubtargetInfo *STI) {
3625 if (hasShortDelaySlot)
3626 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Out, STI);
3627 else
3628 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Out, STI);
3629 }
3630
3631 void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
3632 unsigned TrgReg, bool Is64Bit, MCStreamer &Out,
3633 const MCSubtargetInfo *STI) {
3634 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
3635 Out, STI);
36363563 }
36373564
36383565 void MipsAsmParser::createCpRestoreMemOp(bool IsLoad, int StackOffset,
36393566 SMLoc IDLoc, MCStreamer &Out,
36403567 const MCSubtargetInfo *STI) {
3568 MipsTargetStreamer &TOut = getTargetStreamer();
3569
36413570 // If the offset can not fit into 16 bits, we need to expand.
36423571 if (!isInt<16>(StackOffset)) {
36433572 MCInst MemInst;
36493578 return;
36503579 }
36513580
3652 emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc,
3653 Out, STI);
3581 TOut.emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset,
3582 IDLoc, STI);
36543583 }
36553584
36563585 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
111111 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
112112 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
113113 forbidModuleDirective();
114 }
115
116 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
117 const MCSubtargetInfo *STI) {
118 MCInst TmpInst;
119 TmpInst.setOpcode(Opcode);
120 TmpInst.addOperand(MCOperand::createReg(Reg0));
121 TmpInst.setLoc(IDLoc);
122 getStreamer().EmitInstruction(TmpInst, *STI);
123 }
124
125 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
126 SMLoc IDLoc, const MCSubtargetInfo *STI) {
127 MCInst TmpInst;
128 TmpInst.setOpcode(Opcode);
129 TmpInst.addOperand(MCOperand::createReg(Reg0));
130 TmpInst.addOperand(Op1);
131 TmpInst.setLoc(IDLoc);
132 getStreamer().EmitInstruction(TmpInst, *STI);
133 }
134
135 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
136 SMLoc IDLoc, const MCSubtargetInfo *STI) {
137 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
138 }
139
140 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
141 SMLoc IDLoc, const MCSubtargetInfo *STI) {
142 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
143 }
144
145 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
146 SMLoc IDLoc, const MCSubtargetInfo *STI) {
147 MCInst TmpInst;
148 TmpInst.setOpcode(Opcode);
149 TmpInst.addOperand(MCOperand::createImm(Imm1));
150 TmpInst.addOperand(MCOperand::createImm(Imm2));
151 TmpInst.setLoc(IDLoc);
152 getStreamer().EmitInstruction(TmpInst, *STI);
153 }
154
155 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
156 MCOperand Op2, SMLoc IDLoc,
157 const MCSubtargetInfo *STI) {
158 MCInst TmpInst;
159 TmpInst.setOpcode(Opcode);
160 TmpInst.addOperand(MCOperand::createReg(Reg0));
161 TmpInst.addOperand(MCOperand::createReg(Reg1));
162 TmpInst.addOperand(Op2);
163 TmpInst.setLoc(IDLoc);
164 getStreamer().EmitInstruction(TmpInst, *STI);
165 }
166
167 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
168 unsigned Reg2, SMLoc IDLoc,
169 const MCSubtargetInfo *STI) {
170 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
171 }
172
173 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
174 int16_t Imm, SMLoc IDLoc,
175 const MCSubtargetInfo *STI) {
176 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
177 }
178
179 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
180 unsigned TrgReg, bool Is64Bit,
181 const MCSubtargetInfo *STI) {
182 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
183 STI);
184 }
185
186 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
187 int16_t ShiftAmount, SMLoc IDLoc,
188 const MCSubtargetInfo *STI) {
189 if (ShiftAmount >= 32) {
190 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
191 return;
192 }
193
194 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
195 }
196
197 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
198 const MCSubtargetInfo *STI) {
199 if (hasShortDelaySlot)
200 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
201 else
202 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
203 }
204
205 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
206 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
114207 }
115208
116209 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
9292 virtual void emitDirectiveSetOddSPReg();
9393 virtual void emitDirectiveSetNoOddSPReg();
9494
95 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
96 const MCSubtargetInfo *STI);
97 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
98 const MCSubtargetInfo *STI);
99 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
100 const MCSubtargetInfo *STI);
101 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
102 const MCSubtargetInfo *STI);
103 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
104 const MCSubtargetInfo *STI);
105 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
106 SMLoc IDLoc, const MCSubtargetInfo *STI);
107 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
108 SMLoc IDLoc, const MCSubtargetInfo *STI);
109 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
110 SMLoc IDLoc, const MCSubtargetInfo *STI);
111 void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,
112 const MCSubtargetInfo *STI);
113 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
114 SMLoc IDLoc, const MCSubtargetInfo *STI);
115 void emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
116 const MCSubtargetInfo *STI);
117 void emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI);
118
95119 void forbidModuleDirective() { ModuleDirectiveAllowed = false; }
96120 void reallowModuleDirective() { ModuleDirectiveAllowed = true; }
97121 bool isModuleDirectiveAllowed() { return ModuleDirectiveAllowed; }