llvm.org GIT mirror llvm / a036240
[Hexagon] Adding expression MC emission and removing XFAIL from test that hits this code path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236348 91177308-0d34-0410-b5e6-96231b3b80d8 Colin LeMahieu 5 years ago
9 changed file(s) with 661 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
277277 VK_Mips_PCREL_HI16,
278278 VK_Mips_PCREL_LO16,
279279
280 VK_COFF_IMGREL32 // symbol@imgrel (image-relative)
280 VK_COFF_IMGREL32, // symbol@imgrel (image-relative)
281
282 VK_Hexagon_PCREL,
283 VK_Hexagon_LO16,
284 VK_Hexagon_HI16,
285 VK_Hexagon_GPREL,
286 VK_Hexagon_GD_GOT,
287 VK_Hexagon_LD_GOT,
288 VK_Hexagon_GD_PLT,
289 VK_Hexagon_LD_PLT,
290 VK_Hexagon_IE,
291 VK_Hexagon_IE_GOT,
292 VK_TPREL,
293 VK_DTPREL
281294 };
282295
283296 private:
282282 case VK_Mips_PCREL_HI16: return "PCREL_HI16";
283283 case VK_Mips_PCREL_LO16: return "PCREL_LO16";
284284 case VK_COFF_IMGREL32: return "IMGREL";
285 case VK_Hexagon_PCREL: return "PCREL";
286 case VK_Hexagon_LO16: return "LO16";
287 case VK_Hexagon_HI16: return "HI16";
288 case VK_Hexagon_GPREL: return "GPREL";
289 case VK_Hexagon_GD_GOT: return "GDGOT";
290 case VK_Hexagon_LD_GOT: return "LDGOT";
291 case VK_Hexagon_GD_PLT: return "GDPLT";
292 case VK_Hexagon_LD_PLT: return "LDPLT";
293 case VK_Hexagon_IE: return "IE";
294 case VK_Hexagon_IE_GOT: return "IEGOT";
295 case VK_TPREL: return "tprel";
296 case VK_DTPREL: return "dtprel";
285297 }
286298 llvm_unreachable("Invalid variant kind");
287299 }
6969 PostInc = 6 // Post increment addressing mode
7070 };
7171
72 enum MemAccessSize {
72 enum class MemAccessSize {
7373 NoMemAccess = 0, // Not a memory acces instruction.
7474 ByteAccess = 1, // Byte access instruction (memb).
7575 HalfWordAccess = 2, // Half word access instruction (memh).
0 //===-- HexagonFixupKinds.h - Hexagon Specific Fixup Entries --------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_HEXAGON_HEXAGONFIXUPKINDS_H
10 #define LLVM_HEXAGON_HEXAGONFIXUPKINDS_H
11
12 #include "llvm/MC/MCFixup.h"
13
14 namespace llvm {
15 namespace Hexagon {
16 enum Fixups {
17 // Branch fixups for R_HEX_B{22,15,7}_PCREL.
18 fixup_Hexagon_B22_PCREL = FirstTargetFixupKind,
19 fixup_Hexagon_B15_PCREL,
20 fixup_Hexagon_B7_PCREL,
21 fixup_Hexagon_LO16,
22 fixup_Hexagon_HI16,
23 fixup_Hexagon_32,
24 fixup_Hexagon_16,
25 fixup_Hexagon_8,
26 fixup_Hexagon_GPREL16_0,
27 fixup_Hexagon_GPREL16_1,
28 fixup_Hexagon_GPREL16_2,
29 fixup_Hexagon_GPREL16_3,
30 fixup_Hexagon_HL16,
31 fixup_Hexagon_B13_PCREL,
32 fixup_Hexagon_B9_PCREL,
33 fixup_Hexagon_B32_PCREL_X,
34 fixup_Hexagon_32_6_X,
35 fixup_Hexagon_B22_PCREL_X,
36 fixup_Hexagon_B15_PCREL_X,
37 fixup_Hexagon_B13_PCREL_X,
38 fixup_Hexagon_B9_PCREL_X,
39 fixup_Hexagon_B7_PCREL_X,
40 fixup_Hexagon_16_X,
41 fixup_Hexagon_12_X,
42 fixup_Hexagon_11_X,
43 fixup_Hexagon_10_X,
44 fixup_Hexagon_9_X,
45 fixup_Hexagon_8_X,
46 fixup_Hexagon_7_X,
47 fixup_Hexagon_6_X,
48 fixup_Hexagon_32_PCREL,
49 fixup_Hexagon_COPY,
50 fixup_Hexagon_GLOB_DAT,
51 fixup_Hexagon_JMP_SLOT,
52 fixup_Hexagon_RELATIVE,
53 fixup_Hexagon_PLT_B22_PCREL,
54 fixup_Hexagon_GOTREL_LO16,
55 fixup_Hexagon_GOTREL_HI16,
56 fixup_Hexagon_GOTREL_32,
57 fixup_Hexagon_GOT_LO16,
58 fixup_Hexagon_GOT_HI16,
59 fixup_Hexagon_GOT_32,
60 fixup_Hexagon_GOT_16,
61 fixup_Hexagon_DTPMOD_32,
62 fixup_Hexagon_DTPREL_LO16,
63 fixup_Hexagon_DTPREL_HI16,
64 fixup_Hexagon_DTPREL_32,
65 fixup_Hexagon_DTPREL_16,
66 fixup_Hexagon_GD_PLT_B22_PCREL,
67 fixup_Hexagon_LD_PLT_B22_PCREL,
68 fixup_Hexagon_GD_GOT_LO16,
69 fixup_Hexagon_GD_GOT_HI16,
70 fixup_Hexagon_GD_GOT_32,
71 fixup_Hexagon_GD_GOT_16,
72 fixup_Hexagon_LD_GOT_LO16,
73 fixup_Hexagon_LD_GOT_HI16,
74 fixup_Hexagon_LD_GOT_32,
75 fixup_Hexagon_LD_GOT_16,
76 fixup_Hexagon_IE_LO16,
77 fixup_Hexagon_IE_HI16,
78 fixup_Hexagon_IE_32,
79 fixup_Hexagon_IE_16,
80 fixup_Hexagon_IE_GOT_LO16,
81 fixup_Hexagon_IE_GOT_HI16,
82 fixup_Hexagon_IE_GOT_32,
83 fixup_Hexagon_IE_GOT_16,
84 fixup_Hexagon_TPREL_LO16,
85 fixup_Hexagon_TPREL_HI16,
86 fixup_Hexagon_TPREL_32,
87 fixup_Hexagon_TPREL_16,
88 fixup_Hexagon_6_PCREL_X,
89 fixup_Hexagon_GOTREL_32_6_X,
90 fixup_Hexagon_GOTREL_16_X,
91 fixup_Hexagon_GOTREL_11_X,
92 fixup_Hexagon_GOT_32_6_X,
93 fixup_Hexagon_GOT_16_X,
94 fixup_Hexagon_GOT_11_X,
95 fixup_Hexagon_DTPREL_32_6_X,
96 fixup_Hexagon_DTPREL_16_X,
97 fixup_Hexagon_DTPREL_11_X,
98 fixup_Hexagon_GD_GOT_32_6_X,
99 fixup_Hexagon_GD_GOT_16_X,
100 fixup_Hexagon_GD_GOT_11_X,
101 fixup_Hexagon_LD_GOT_32_6_X,
102 fixup_Hexagon_LD_GOT_16_X,
103 fixup_Hexagon_LD_GOT_11_X,
104 fixup_Hexagon_IE_32_6_X,
105 fixup_Hexagon_IE_16_X,
106 fixup_Hexagon_IE_GOT_32_6_X,
107 fixup_Hexagon_IE_GOT_16_X,
108 fixup_Hexagon_IE_GOT_11_X,
109 fixup_Hexagon_TPREL_32_6_X,
110 fixup_Hexagon_TPREL_16_X,
111 fixup_Hexagon_TPREL_11_X,
112
113 LastTargetFixupKind,
114 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
115 };
116 enum FixupBitmaps {
117 Word8 = 0xff,
118 Word16 = 0xffff,
119 Word32 = 0xffffffff,
120 Word32_LO = 0x00c03fff,
121 Word32_HL = 0x0, // Not Implemented
122 Word32_GP = 0x0, // Not Implemented
123 Word32_B7 = 0x00001f18,
124 Word32_B9 = 0x003000fe,
125 Word32_B13 = 0x00202ffe,
126 Word32_B15 = 0x00df20fe,
127 Word32_B22 = 0x01ff3ffe,
128 Word32_R6 = 0x000007e0,
129 Word32_U6 = 0x0, // Not Implemented
130 Word32_U16 = 0x0, // Not Implemented
131 Word32_X26 = 0x0fff3fff
132 };
133 } // namespace Hexagon
134 } // namespace llvm
135
136 #endif // LLVM_HEXAGON_HEXAGONFIXUPKINDS_H
88
99 #include "Hexagon.h"
1010 #include "MCTargetDesc/HexagonBaseInfo.h"
11 #include "MCTargetDesc/HexagonFixupKinds.h"
1112 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
1213 #include "MCTargetDesc/HexagonMCInstrInfo.h"
1314 #include "MCTargetDesc/HexagonMCTargetDesc.h"
3637 /// \brief Returns the packet bits based on instruction position.
3738 uint32_t getPacketBits(MCInst const &HMI) {
3839 unsigned const ParseFieldOffset = 14;
39 ParseField Field = HexagonMCInstrInfo::isPacketEnd(HMI) ? ParseField::end : ParseField::last0;
40 return static_cast (Field) << ParseFieldOffset;
40 ParseField Field = HexagonMCInstrInfo::isPacketEnd(HMI) ? ParseField::end
41 : ParseField::last0;
42 return static_cast(Field) << ParseFieldOffset;
4143 }
4244 void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
4345 OS << static_cast((Binary >> 0x00) & 0xff);
4951
5052 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
5153 MCContext &aMCT)
52 : MCT(aMCT), MCII(aMII) {}
54 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
55 Extended(new bool(false)) {}
5356
5457 void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
5558 SmallVectorImpl &Fixups,
6265 ++MCNumEmitted;
6366 }
6467
68 static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
69 const MCOperand &MO,
70 const MCSymbolRefExpr::VariantKind kind) {
71 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
72 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
73
74 if (insnType == HexagonII::TypePREFIX) {
75 switch (kind) {
76 case llvm::MCSymbolRefExpr::VK_GOTOFF:
77 return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
78 case llvm::MCSymbolRefExpr::VK_GOT:
79 return Hexagon::fixup_Hexagon_GOT_32_6_X;
80 case llvm::MCSymbolRefExpr::VK_TPREL:
81 return Hexagon::fixup_Hexagon_TPREL_32_6_X;
82 case llvm::MCSymbolRefExpr::VK_DTPREL:
83 return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
84 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
85 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
86 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
87 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
88 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
89 return Hexagon::fixup_Hexagon_IE_32_6_X;
90 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
91 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
92 default:
93 if (MCID.isBranch())
94 return Hexagon::fixup_Hexagon_B32_PCREL_X;
95 else
96 return Hexagon::fixup_Hexagon_32_6_X;
97 }
98 } else if (MCID.isBranch())
99 return (Hexagon::fixup_Hexagon_B13_PCREL);
100
101 switch (MCID.getOpcode()) {
102 case Hexagon::HI:
103 case Hexagon::A2_tfrih:
104 switch (kind) {
105 case llvm::MCSymbolRefExpr::VK_GOT:
106 return Hexagon::fixup_Hexagon_GOT_HI16;
107 case llvm::MCSymbolRefExpr::VK_GOTOFF:
108 return Hexagon::fixup_Hexagon_GOTREL_HI16;
109 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
110 return Hexagon::fixup_Hexagon_GD_GOT_HI16;
111 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
112 return Hexagon::fixup_Hexagon_LD_GOT_HI16;
113 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
114 return Hexagon::fixup_Hexagon_IE_HI16;
115 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
116 return Hexagon::fixup_Hexagon_IE_GOT_HI16;
117 case llvm::MCSymbolRefExpr::VK_TPREL:
118 return Hexagon::fixup_Hexagon_TPREL_HI16;
119 case llvm::MCSymbolRefExpr::VK_DTPREL:
120 return Hexagon::fixup_Hexagon_DTPREL_HI16;
121 default:
122 return Hexagon::fixup_Hexagon_HI16;
123 }
124
125 case Hexagon::LO:
126 case Hexagon::A2_tfril:
127 switch (kind) {
128 case llvm::MCSymbolRefExpr::VK_GOT:
129 return Hexagon::fixup_Hexagon_GOT_LO16;
130 case llvm::MCSymbolRefExpr::VK_GOTOFF:
131 return Hexagon::fixup_Hexagon_GOTREL_LO16;
132 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
133 return Hexagon::fixup_Hexagon_GD_GOT_LO16;
134 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
135 return Hexagon::fixup_Hexagon_LD_GOT_LO16;
136 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
137 return Hexagon::fixup_Hexagon_IE_LO16;
138 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
139 return Hexagon::fixup_Hexagon_IE_GOT_LO16;
140 case llvm::MCSymbolRefExpr::VK_TPREL:
141 return Hexagon::fixup_Hexagon_TPREL_LO16;
142 case llvm::MCSymbolRefExpr::VK_DTPREL:
143 return Hexagon::fixup_Hexagon_DTPREL_LO16;
144 default:
145 return Hexagon::fixup_Hexagon_LO16;
146 }
147
148 // The only relocs left should be GP relative:
149 default:
150 if (MCID.mayStore() || MCID.mayLoad()) {
151 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses;
152 ++ImpUses) {
153 if (*ImpUses == Hexagon::GP) {
154 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
155 case HexagonII::MemAccessSize::ByteAccess:
156 return fixup_Hexagon_GPREL16_0;
157 case HexagonII::MemAccessSize::HalfWordAccess:
158 return fixup_Hexagon_GPREL16_1;
159 case HexagonII::MemAccessSize::WordAccess:
160 return fixup_Hexagon_GPREL16_2;
161 case HexagonII::MemAccessSize::DoubleWordAccess:
162 return fixup_Hexagon_GPREL16_3;
163 default:
164 llvm_unreachable("unhandled fixup");
165 }
166 }
167 }
168 } else
169 llvm_unreachable("unhandled fixup");
170 }
171
172 return LastTargetFixupKind;
173 }
174
175 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
176 const MCOperand &MO,
177 const MCExpr *ME,
178 SmallVectorImpl &Fixups,
179 const MCSubtargetInfo &STI) const
180
181 {
182 int64_t Res;
183
184 if (ME->EvaluateAsAbsolute(Res))
185 return Res;
186
187 MCExpr::ExprKind MK = ME->getKind();
188 if (MK == MCExpr::Constant) {
189 return cast(ME)->getValue();
190 }
191 if (MK == MCExpr::Binary) {
192 unsigned Res;
193 Res = getExprOpValue(MI, MO, cast(ME)->getLHS(), Fixups, STI);
194 Res +=
195 getExprOpValue(MI, MO, cast(ME)->getRHS(), Fixups, STI);
196 return Res;
197 }
198
199 assert(MK == MCExpr::SymbolRef);
200
201 Hexagon::Fixups FixupKind =
202 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
203 const MCSymbolRefExpr *MCSRE = static_cast(ME);
204 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
205 unsigned opcode = MCID.getOpcode();
206 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
207 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
208 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
209
210 DEBUG(dbgs() << "----------------------------------------\n");
211 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
212 << "\n");
213 DEBUG(dbgs() << "Opcode: " << opcode << "\n");
214 DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
215 DEBUG(dbgs() << "Addend: " << *Addend << "\n");
216 DEBUG(dbgs() << "----------------------------------------\n");
217
218 switch (bits) {
219 default:
220 DEBUG(dbgs() << "unrecognized bit count of " << bits << '\n');
221 break;
222
223 case 32:
224 switch (kind) {
225 case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
226 FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
227 break;
228 case llvm::MCSymbolRefExpr::VK_GOT:
229 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
230 : Hexagon::fixup_Hexagon_GOT_32;
231 break;
232 case llvm::MCSymbolRefExpr::VK_GOTOFF:
233 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
234 : Hexagon::fixup_Hexagon_GOTREL_32;
235 break;
236 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
237 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
238 : Hexagon::fixup_Hexagon_GD_GOT_32;
239 break;
240 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
241 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
242 : Hexagon::fixup_Hexagon_LD_GOT_32;
243 break;
244 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
245 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
246 : Hexagon::fixup_Hexagon_IE_32;
247 break;
248 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
249 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
250 : Hexagon::fixup_Hexagon_IE_GOT_32;
251 break;
252 case llvm::MCSymbolRefExpr::VK_TPREL:
253 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
254 : Hexagon::fixup_Hexagon_TPREL_32;
255 break;
256 case llvm::MCSymbolRefExpr::VK_DTPREL:
257 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
258 : Hexagon::fixup_Hexagon_DTPREL_32;
259 break;
260 default:
261 FixupKind =
262 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
263 break;
264 }
265 break;
266
267 case 22:
268 switch (kind) {
269 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_PLT:
270 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
271 break;
272 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_PLT:
273 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
274 break;
275 default:
276 if (MCID.isBranch() || MCID.isCall()) {
277 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
278 : Hexagon::fixup_Hexagon_B22_PCREL;
279 } else {
280 errs() << "unrecognized relocation, bits: " << bits << "\n";
281 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
282 }
283 break;
284 }
285 break;
286
287 case 16:
288 if (*Extended) {
289 switch (kind) {
290 default:
291 FixupKind = Hexagon::fixup_Hexagon_16_X;
292 break;
293 case llvm::MCSymbolRefExpr::VK_GOT:
294 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
295 break;
296 case llvm::MCSymbolRefExpr::VK_GOTOFF:
297 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
298 break;
299 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
300 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
301 break;
302 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
303 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
304 break;
305 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
306 FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
307 break;
308 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
309 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
310 break;
311 case llvm::MCSymbolRefExpr::VK_TPREL:
312 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
313 break;
314 case llvm::MCSymbolRefExpr::VK_DTPREL:
315 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
316 break;
317 }
318 } else
319 switch (kind) {
320 default:
321 errs() << "unrecognized relocation, bits " << bits << "\n";
322 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
323 break;
324 case llvm::MCSymbolRefExpr::VK_GOTOFF:
325 if ((MCID.getOpcode() == Hexagon::HI) ||
326 (MCID.getOpcode() == Hexagon::LO_H))
327 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
328 else
329 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
330 break;
331 case llvm::MCSymbolRefExpr::VK_Hexagon_GPREL:
332 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
333 break;
334 case llvm::MCSymbolRefExpr::VK_Hexagon_LO16:
335 FixupKind = Hexagon::fixup_Hexagon_LO16;
336 break;
337 case llvm::MCSymbolRefExpr::VK_Hexagon_HI16:
338 FixupKind = Hexagon::fixup_Hexagon_HI16;
339 break;
340 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
341 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
342 break;
343 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
344 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
345 break;
346 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
347 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
348 break;
349 case llvm::MCSymbolRefExpr::VK_TPREL:
350 FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
351 break;
352 case llvm::MCSymbolRefExpr::VK_DTPREL:
353 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
354 break;
355 }
356 break;
357
358 case 15:
359 if (MCID.isBranch() || MCID.isCall())
360 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
361 : Hexagon::fixup_Hexagon_B15_PCREL;
362 break;
363
364 case 13:
365 if (MCID.isBranch())
366 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
367 else {
368 errs() << "unrecognized relocation, bits " << bits << "\n";
369 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
370 }
371 break;
372
373 case 12:
374 if (*Extended)
375 switch (kind) {
376 default:
377 FixupKind = Hexagon::fixup_Hexagon_12_X;
378 break;
379 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
380 case llvm::MCSymbolRefExpr::VK_GOT:
381 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
382 break;
383 case llvm::MCSymbolRefExpr::VK_GOTOFF:
384 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
385 break;
386 }
387 else {
388 errs() << "unrecognized relocation, bits " << bits << "\n";
389 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
390 }
391 break;
392
393 case 11:
394 if (*Extended)
395 switch (kind) {
396 default:
397 FixupKind = Hexagon::fixup_Hexagon_11_X;
398 break;
399 case llvm::MCSymbolRefExpr::VK_GOT:
400 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
401 break;
402 case llvm::MCSymbolRefExpr::VK_GOTOFF:
403 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
404 break;
405 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
406 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
407 break;
408 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
409 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
410 break;
411 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
412 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
413 break;
414 case llvm::MCSymbolRefExpr::VK_TPREL:
415 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
416 break;
417 case llvm::MCSymbolRefExpr::VK_DTPREL:
418 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
419 break;
420 }
421 else {
422 errs() << "unrecognized relocation, bits " << bits << "\n";
423 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
424 }
425 break;
426
427 case 10:
428 if (*Extended)
429 FixupKind = Hexagon::fixup_Hexagon_10_X;
430 break;
431
432 case 9:
433 if (MCID.isBranch() ||
434 (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
435 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
436 : Hexagon::fixup_Hexagon_B9_PCREL;
437 else if (*Extended)
438 FixupKind = Hexagon::fixup_Hexagon_9_X;
439 else {
440 errs() << "unrecognized relocation, bits " << bits << "\n";
441 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
442 }
443 break;
444
445 case 8:
446 if (*Extended)
447 FixupKind = Hexagon::fixup_Hexagon_8_X;
448 else {
449 errs() << "unrecognized relocation, bits " << bits << "\n";
450 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
451 }
452 break;
453
454 case 7:
455 if (MCID.isBranch() ||
456 (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
457 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
458 : Hexagon::fixup_Hexagon_B7_PCREL;
459 else if (*Extended)
460 FixupKind = Hexagon::fixup_Hexagon_7_X;
461 else {
462 errs() << "unrecognized relocation, bits " << bits << "\n";
463 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
464 }
465 break;
466
467 case 6:
468 if (*Extended) {
469 switch (kind) {
470 default:
471 FixupKind = Hexagon::fixup_Hexagon_6_X;
472 break;
473 case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
474 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
475 break;
476 // This is part of an extender, GOT_11 is a
477 // Word32_U6 unsigned/truncated reloc.
478 case llvm::MCSymbolRefExpr::VK_GOT:
479 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
480 break;
481 case llvm::MCSymbolRefExpr::VK_GOTOFF:
482 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
483 break;
484 }
485 } else {
486 errs() << "unrecognized relocation, bits " << bits << "\n";
487 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
488 }
489 break;
490
491 case 0:
492 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
493 break;
494 }
495
496 MCFixup fixup =
497 MCFixup::Create(*Addend, MO.getExpr(), MCFixupKind(FixupKind));
498 Fixups.push_back(fixup);
499 // All of the information is in the fixup.
500 return (0);
501 }
502
65503 unsigned
66504 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
67505 SmallVectorImpl &Fixups,
70508 return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
71509 if (MO.isImm())
72510 return static_cast(MO.getImm());
73 llvm_unreachable("Only Immediates and Registers implemented right now");
511
512 // MO must be an ME.
513 assert(MO.isExpr());
514 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
74515 }
75516
76517 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
2727 class HexagonMCCodeEmitter : public MCCodeEmitter {
2828 MCContext &MCT;
2929 MCInstrInfo const &MCII;
30 std::unique_ptr Addend;
31 std::unique_ptr Extended;
32
33 // helper routine for getMachineOpValue()
34 unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
35 const MCExpr *ME, SmallVectorImpl &Fixups,
36 const MCSubtargetInfo &STI) const;
3037
3138 public:
3239 HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT);
1919 MCI.addOperand(MCOperand::CreateInst(nullptr));
2020 }
2121
22 HexagonII::MemAccessSize
23 HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
24 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
25
26 return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
27 HexagonII::MemAccesSizeMask));
28 }
29
2230 unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII,
2331 MCInst const &MCI) {
2432 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
3543 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
3644 MCInst const &MCI) {
3745 return (MCII.get(MCI.getOpcode()));
46 }
47
48 unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
49 MCInst const &MCI) {
50 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
51 return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
52 }
53
54 unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
55 MCInst const &MCI) {
56 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
57 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
3858 }
3959
4060 std::bitset<16> HexagonMCInstrInfo::GetImplicitBits(MCInst const &MCI) {
7191 return -1U << (bits - 1);
7292 else
7393 return 0;
94 }
95
96 char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
97 MCInst const &MCI) {
98 return MCII.getName(MCI.getOpcode());
7499 }
75100
76101 // Return the operand that consumes or produces a new value.
2222 class MCInstrInfo;
2323 class MCInst;
2424 class MCOperand;
25 namespace HexagonII {
26 enum class MemAccessSize;
27 }
2528 namespace HexagonMCInstrInfo {
2629 void AppendImplicitOperands(MCInst &MCI);
30
31 // Return memory access size
32 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
33 MCInst const &MCI);
2734
2835 // Return number of bits in the constant extended operand.
2936 unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI);
3239 unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI);
3340
3441 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
42
43 // Return the implicit alignment of the extendable operand
44 unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
45
46 // Return the number of logical bits of the extendable operand
47 unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
3548
3649 std::bitset<16> GetImplicitBits(MCInst const &MCI);
3750
4356 // without being extended.
4457 int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
4558
59 // Return instruction name
60 char const *getName(MCInstrInfo const &MCII, MCInst const &MCI);
61
4662 // Return the operand that consumes or produces a new value.
4763 MCOperand const &getNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
4864
5167
5268 // Return whether the instruction is a legal new-value producer.
5369 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
54
70
5571 // Return whether the insn is an actual insn.
5672 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
5773
89105 inline void SanityCheckImplicitOperands(MCInst const &MCI) {
90106 assert(MCI.getNumOperands() >= 2 && "At least the two implicit operands");
91107 assert(MCI.getOperand(MCI.getNumOperands() - 1).isInst() &&
92 "Implicit bits and flags");
93 assert(MCI.getOperand(MCI.getNumOperands() - 2).isImm() &&
94 "Parent pointer");
108 "Implicit bits and flags");
109 assert(MCI.getOperand(MCI.getNumOperands() - 2).isImm() && "Parent pointer");
95110 }
96111
97112 void SetImplicitBits(MCInst &MCI, std::bitset<16> Bits);
0 ; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
11
22 ; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
3 ; Hexagon crashes (PR23377)
4 ; XFAIL: arm,aarch64,hexagon
3 ; XFAIL: arm,aarch64
54
65 ; Make sure we have the correct weight attached to each successor.
76 define i32 @test2(i32 %x) nounwind uwtable readnone ssp {