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[test/AMDGPU] Square-braced-syntax for registers: add macro test/example. Test added as per discussion in http://reviews.llvm.org/D20588. The macro is just a demonstration, useless in practice. Coding style fixes. Differential Revision: http://reviews.llvm.org/D20797 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271675 91177308-0d34-0410-b5e6-96231b3b80d8 Artem Tamazov 4 years ago
2 changed file(s) with 81 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
775775 RegKind = IS_SPECIAL;
776776 } else {
777777 unsigned RegNumIndex = 0;
778 if (RegName[0] == 'v') { RegNumIndex = 1; RegKind = IS_VGPR; }
779 else if (RegName[0] == 's') { RegNumIndex = 1; RegKind = IS_SGPR; }
780 else if (RegName.startswith("ttmp")) { RegNumIndex = strlen("ttmp"); RegKind = IS_TTMP; }
781 else { return false; }
778 if (RegName[0] == 'v') {
779 RegNumIndex = 1;
780 RegKind = IS_VGPR;
781 } else if (RegName[0] == 's') {
782 RegNumIndex = 1;
783 RegKind = IS_SGPR;
784 } else if (RegName.startswith("ttmp")) {
785 RegNumIndex = strlen("ttmp");
786 RegKind = IS_TTMP;
787 } else {
788 return false;
789 }
782790 if (RegName.size() > RegNumIndex) {
783791 // Single 32-bit register: vXX.
784 if (RegName.substr(RegNumIndex).getAsInteger(10, RegNum)) { return false; }
792 if (RegName.substr(RegNumIndex).getAsInteger(10, RegNum))
793 return false;
785794 Parser.Lex();
786795 RegWidth = 1;
787796 } else {
788797 // Range of registers: v[XX:YY]. ":YY" is optional.
789798 Parser.Lex();
790799 int64_t RegLo, RegHi;
791 if (getLexer().isNot(AsmToken::LBrac)) { return false; }
800 if (getLexer().isNot(AsmToken::LBrac))
801 return false;
792802 Parser.Lex();
793803
794 if (getParser().parseAbsoluteExpression(RegLo)) { return false; }
804 if (getParser().parseAbsoluteExpression(RegLo))
805 return false;
795806
796807 const bool isRBrace = getLexer().is(AsmToken::RBrac);
797 if (!isRBrace && getLexer().isNot(AsmToken::Colon)) { return false; }
808 if (!isRBrace && getLexer().isNot(AsmToken::Colon))
809 return false;
798810 Parser.Lex();
799811
800812 if (isRBrace) {
801813 RegHi = RegLo;
802814 } else {
803 if (getParser().parseAbsoluteExpression(RegHi)) { return false; }
804
805 if (getLexer().isNot(AsmToken::RBrac)) { return false; }
815 if (getParser().parseAbsoluteExpression(RegHi))
816 return false;
817
818 if (getLexer().isNot(AsmToken::RBrac))
819 return false;
806820 Parser.Lex();
807821 }
808822 RegNum = (unsigned) RegLo;
812826 } else if (getLexer().is(AsmToken::LBrac)) {
813827 // List of consecutive registers: [s0,s1,s2,s3]
814828 Parser.Lex();
815 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) { return false; }
816 if (RegWidth != 1) { return false; }
829 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
830 return false;
831 if (RegWidth != 1)
832 return false;
817833 RegisterKind RegKind1;
818834 unsigned Reg1, RegNum1, RegWidth1;
819835 do {
823839 Parser.Lex();
824840 break;
825841 } else if (ParseAMDGPURegister(RegKind1, Reg1, RegNum1, RegWidth1)) {
826 if (RegWidth1 != 1) { return false; }
827 if (RegKind1 != RegKind) { return false; }
828 if (!AddNextRegisterToList(Reg, RegWidth, RegKind1, Reg1, RegNum1)) { return false; }
842 if (RegWidth1 != 1) {
843 return false;
844 }
845 if (RegKind1 != RegKind) {
846 return false;
847 }
848 if (!AddNextRegisterToList(Reg, RegWidth, RegKind1, Reg1, RegNum1)) {
849 return false;
850 }
829851 } else {
830852 return false;
831853 }
847869 // SGPR and TTMP registers must be are aligned. Max required alignment is 4 dwords.
848870 Size = std::min(RegWidth, 4u);
849871 }
850 if (RegNum % Size != 0) { return false; }
872 if (RegNum % Size != 0)
873 return false;
851874 RegNum = RegNum / Size;
852875 int RCID = getRegClass(RegKind, RegWidth);
853 if (RCID == -1) { return false; }
876 if (RCID == -1)
877 return false;
854878 const MCRegisterClass RC = TRI->getRegClass(RCID);
855 if (RegNum >= RC.getNumRegs()) { return false; }
879 if (RegNum >= RC.getNumRegs())
880 return false;
856881 Reg = RC.getRegister(RegNum);
857882 break;
858883 }
861886 assert(false); return false;
862887 }
863888
864 if (!subtargetHasRegister(*TRI, Reg)) { return false; }
889 if (!subtargetHasRegister(*TRI, Reg))
890 return false;
865891 return true;
866892 }
867893
0 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji %s | FileCheck %s --check-prefix=VI
1
2 //===----------------------------------------------------------------------===//
3 // Example of reg[expr] and reg[epxr1:expr2] syntax in macros.
4 //===----------------------------------------------------------------------===//
5
6 .macro REG_NUM_EXPR_EXAMPLE width iter iter_end
7 .if \width == 4
8 flat_load_dwordx4 v[8 + (\iter * 4):8 + (\iter * 4) + 3], v[2:3]
9 .else
10 flat_load_dword v[8 + \iter], v[2:3]
11 .endif
12
13 .if (\iter_end - \iter)
14 REG_NUM_EXPR_EXAMPLE \width, (\iter + 1), \iter_end
15 .endif
16 .endm
17
18 REG_NUM_EXPR_EXAMPLE 4, 0, 0
19 // VI: flat_load_dwordx4 v[8:11], v[2:3]
20
21 REG_NUM_EXPR_EXAMPLE 1, 0, 0
22 // VI: flat_load_dword v8, v[2:3]
23
24 REG_NUM_EXPR_EXAMPLE 4, 1, 4
25 // VI: flat_load_dwordx4 v[12:15], v[2:3]
26 // VI: flat_load_dwordx4 v[16:19], v[2:3]
27 // VI: flat_load_dwordx4 v[20:23], v[2:3]
28 // VI: flat_load_dwordx4 v[24:27], v[2:3]
29
30 REG_NUM_EXPR_EXAMPLE 1, 1, 4
31 // VI: flat_load_dword v9, v[2:3]
32 // VI: flat_load_dword v10, v[2:3]
33 // VI: flat_load_dword v11, v[2:3]
34 // VI: flat_load_dword v12, v[2:3]