llvm.org GIT mirror llvm / a031d73
Fix spelling compliment->complement. Mostly refering to 2s complement. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299970 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 2 years ago
5 changed file(s) with 7 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
5555 /// This pass provides a general RPO or "top down" propagation of
5656 /// function attributes. For a few (rare) cases, we can deduce significantly
5757 /// more about function attributes by working in RPO, so this pass
58 /// provides the compliment to the post-order pass above where the majority of
58 /// provides the complement to the post-order pass above where the majority of
5959 /// deduction is performed.
6060 // FIXME: Currently there is no RPO CGSCC pass structure to slide into and so
6161 // this is a boring module pass, but eventually it should be an RPO CGSCC pass
693693 }
694694
695695 //===----------------------------------------------------------------------===//
696 // One's/Two's Compliment
696 // One's/Two's Complement
697697 //===----------------------------------------------------------------------===//
698698 let Constraints = "$src = $rd",
699699 Defs = [SREG] in
17171717 (implicit SREG)]>;
17181718
17191719 // CBR Rd, K
1720 // Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
1720 // Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K.
17211721 // FIXME: This uses the 'complement' encoder. We need it to also use the
17221722 // imm_ldi8 encoder. This will cause no fixups to be created on this instruction.
17231723 def CBRRdK : FRdK<0b0111,
6262 SmallVectorImpl &Fixups,
6363 const MCSubtargetInfo &STI) const;
6464
65 /// Takes the compliment of a number (~0 - val).
65 /// Takes the complement of a number (~0 - val).
6666 unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
6767 SmallVectorImpl &Fixups,
6868 const MCSubtargetInfo &STI) const;
516516 defm ADD_i1 : ADD_SUB_i1;
517517 defm SUB_i1 : ADD_SUB_i1;
518518
519 // int16, int32, and int64 signed addition. Since nvptx is 2's compliment, we
519 // int16, int32, and int64 signed addition. Since nvptx is 2's complement, we
520520 // also use these for unsigned arithmetic.
521521 defm ADD : I3<"add.s", add>;
522522 defm SUB : I3<"sub.s", sub>;
901901 APInt RHSKnownOne(BitWidth, 0);
902902 computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI);
903903
904 // Addition of two 2's compliment numbers having opposite signs will never
904 // Addition of two 2's complement numbers having opposite signs will never
905905 // overflow.
906906 if ((LHSKnownOne[BitWidth - 1] && RHSKnownZero[BitWidth - 1]) ||
907907 (LHSKnownZero[BitWidth - 1] && RHSKnownOne[BitWidth - 1]))
938938 APInt RHSKnownOne(BitWidth, 0);
939939 computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI);
940940
941 // Subtraction of two 2's compliment numbers having identical signs will
941 // Subtraction of two 2's complement numbers having identical signs will
942942 // never overflow.
943943 if ((LHSKnownOne[BitWidth - 1] && RHSKnownOne[BitWidth - 1]) ||
944944 (LHSKnownZero[BitWidth - 1] && RHSKnownZero[BitWidth - 1]))